1	/*
2	* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3	*
4	* This software is available to you under a choice of one of two
5	* licenses. You may choose to be licensed under the terms of the GNU
6	* General Public License (GPL) Version 2, available from the file
7	* COPYING in the main directory of this source tree, or the
8	* OpenIB.org BSD license below:
9	*
10	* Redistribution and use in source and binary forms, with or
11	* without modification, are permitted provided that the following
12	* conditions are met:
13	*
14	* - Redistributions of source code must retain the above
15	* copyright notice, this list of conditions and the following
16	* disclaimer.
17	*
18	* - Redistributions in binary form must reproduce the above
19	* copyright notice, this list of conditions and the following
20	* disclaimer in the documentation and/or other materials
21	* provided with the distribution.
22	*
23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30	* SOFTWARE.
31	*/
32	#ifndef MLX5_IFC_H
33	#define MLX5_IFC_H
34
35	#include "mlx5_ifc_fpga.h"
36
37	enum {
38	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46	MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55	MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62	MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64	};
65
66	enum {
67	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1,
69	MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
70	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
71	MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
72	MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15,
73	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20,
74	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25,
75	};
76
77	enum {
78	MLX5_SHARED_RESOURCE_UID = 0xffff,
79	};
80
81	enum {
82	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
84	};
85
86	enum {
87	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91	(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93	};
94
95	enum {
96	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101	MLX5_OBJ_TYPE_MKEY = 0xff01,
102	MLX5_OBJ_TYPE_QP = 0xff02,
103	MLX5_OBJ_TYPE_PSV = 0xff03,
104	MLX5_OBJ_TYPE_RMP = 0xff04,
105	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106	MLX5_OBJ_TYPE_RQ = 0xff06,
107	MLX5_OBJ_TYPE_SQ = 0xff07,
108	MLX5_OBJ_TYPE_TIR = 0xff08,
109	MLX5_OBJ_TYPE_TIS = 0xff09,
110	MLX5_OBJ_TYPE_DCT = 0xff0a,
111	MLX5_OBJ_TYPE_XRQ = 0xff0b,
112	MLX5_OBJ_TYPE_RQT = 0xff0e,
113	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114	MLX5_OBJ_TYPE_CQ = 0xff10,
115	};
116
117	enum {
118	MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
119	MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
120	MLX5_CMD_OP_INIT_HCA = 0x102,
121	MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
122	MLX5_CMD_OP_ENABLE_HCA = 0x104,
123	MLX5_CMD_OP_DISABLE_HCA = 0x105,
124	MLX5_CMD_OP_QUERY_PAGES = 0x107,
125	MLX5_CMD_OP_MANAGE_PAGES = 0x108,
126	MLX5_CMD_OP_SET_HCA_CAP = 0x109,
127	MLX5_CMD_OP_QUERY_ISSI = 0x10a,
128	MLX5_CMD_OP_SET_ISSI = 0x10b,
129	MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
130	MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
131	MLX5_CMD_OP_ALLOC_SF = 0x113,
132	MLX5_CMD_OP_DEALLOC_SF = 0x114,
133	MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
134	MLX5_CMD_OP_RESUME_VHCA = 0x116,
135	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
136	MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
137	MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
138	MLX5_CMD_OP_CREATE_MKEY = 0x200,
139	MLX5_CMD_OP_QUERY_MKEY = 0x201,
140	MLX5_CMD_OP_DESTROY_MKEY = 0x202,
141	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
142	MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
143	MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
144	MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
145	MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
146	MLX5_CMD_OP_CREATE_EQ = 0x301,
147	MLX5_CMD_OP_DESTROY_EQ = 0x302,
148	MLX5_CMD_OP_QUERY_EQ = 0x303,
149	MLX5_CMD_OP_GEN_EQE = 0x304,
150	MLX5_CMD_OP_CREATE_CQ = 0x400,
151	MLX5_CMD_OP_DESTROY_CQ = 0x401,
152	MLX5_CMD_OP_QUERY_CQ = 0x402,
153	MLX5_CMD_OP_MODIFY_CQ = 0x403,
154	MLX5_CMD_OP_CREATE_QP = 0x500,
155	MLX5_CMD_OP_DESTROY_QP = 0x501,
156	MLX5_CMD_OP_RST2INIT_QP = 0x502,
157	MLX5_CMD_OP_INIT2RTR_QP = 0x503,
158	MLX5_CMD_OP_RTR2RTS_QP = 0x504,
159	MLX5_CMD_OP_RTS2RTS_QP = 0x505,
160	MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
161	MLX5_CMD_OP_2ERR_QP = 0x507,
162	MLX5_CMD_OP_2RST_QP = 0x50a,
163	MLX5_CMD_OP_QUERY_QP = 0x50b,
164	MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
165	MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
166	MLX5_CMD_OP_CREATE_PSV = 0x600,
167	MLX5_CMD_OP_DESTROY_PSV = 0x601,
168	MLX5_CMD_OP_CREATE_SRQ = 0x700,
169	MLX5_CMD_OP_DESTROY_SRQ = 0x701,
170	MLX5_CMD_OP_QUERY_SRQ = 0x702,
171	MLX5_CMD_OP_ARM_RQ = 0x703,
172	MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
173	MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
174	MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
175	MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
176	MLX5_CMD_OP_CREATE_DCT = 0x710,
177	MLX5_CMD_OP_DESTROY_DCT = 0x711,
178	MLX5_CMD_OP_DRAIN_DCT = 0x712,
179	MLX5_CMD_OP_QUERY_DCT = 0x713,
180	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
181	MLX5_CMD_OP_CREATE_XRQ = 0x717,
182	MLX5_CMD_OP_DESTROY_XRQ = 0x718,
183	MLX5_CMD_OP_QUERY_XRQ = 0x719,
184	MLX5_CMD_OP_ARM_XRQ = 0x71a,
185	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
186	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
187	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
188	MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
189	MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
190	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
191	MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
192	MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
193	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
194	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
195	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
196	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
197	MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
198	MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
199	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
200	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
201	MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
202	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
203	MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
204	MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
205	MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
206	MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
207	MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
208	MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
209	MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
210	MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
211	MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
212	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
213	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
214	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
215	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
216	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
217	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
218	MLX5_CMD_OP_ALLOC_PD = 0x800,
219	MLX5_CMD_OP_DEALLOC_PD = 0x801,
220	MLX5_CMD_OP_ALLOC_UAR = 0x802,
221	MLX5_CMD_OP_DEALLOC_UAR = 0x803,
222	MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
223	MLX5_CMD_OP_ACCESS_REG = 0x805,
224	MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
225	MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
226	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
227	MLX5_CMD_OP_MAD_IFC = 0x50d,
228	MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
229	MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
230	MLX5_CMD_OP_NOP = 0x80d,
231	MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
232	MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
233	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
234	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
235	MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
236	MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
237	MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
238	MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
239	MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
240	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
241	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
242	MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
243	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
244	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
245	MLX5_CMD_OP_SET_WOL_ROL = 0x830,
246	MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
247	MLX5_CMD_OP_CREATE_LAG = 0x840,
248	MLX5_CMD_OP_MODIFY_LAG = 0x841,
249	MLX5_CMD_OP_QUERY_LAG = 0x842,
250	MLX5_CMD_OP_DESTROY_LAG = 0x843,
251	MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
252	MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
253	MLX5_CMD_OP_CREATE_TIR = 0x900,
254	MLX5_CMD_OP_MODIFY_TIR = 0x901,
255	MLX5_CMD_OP_DESTROY_TIR = 0x902,
256	MLX5_CMD_OP_QUERY_TIR = 0x903,
257	MLX5_CMD_OP_CREATE_SQ = 0x904,
258	MLX5_CMD_OP_MODIFY_SQ = 0x905,
259	MLX5_CMD_OP_DESTROY_SQ = 0x906,
260	MLX5_CMD_OP_QUERY_SQ = 0x907,
261	MLX5_CMD_OP_CREATE_RQ = 0x908,
262	MLX5_CMD_OP_MODIFY_RQ = 0x909,
263	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
264	MLX5_CMD_OP_DESTROY_RQ = 0x90a,
265	MLX5_CMD_OP_QUERY_RQ = 0x90b,
266	MLX5_CMD_OP_CREATE_RMP = 0x90c,
267	MLX5_CMD_OP_MODIFY_RMP = 0x90d,
268	MLX5_CMD_OP_DESTROY_RMP = 0x90e,
269	MLX5_CMD_OP_QUERY_RMP = 0x90f,
270	MLX5_CMD_OP_CREATE_TIS = 0x912,
271	MLX5_CMD_OP_MODIFY_TIS = 0x913,
272	MLX5_CMD_OP_DESTROY_TIS = 0x914,
273	MLX5_CMD_OP_QUERY_TIS = 0x915,
274	MLX5_CMD_OP_CREATE_RQT = 0x916,
275	MLX5_CMD_OP_MODIFY_RQT = 0x917,
276	MLX5_CMD_OP_DESTROY_RQT = 0x918,
277	MLX5_CMD_OP_QUERY_RQT = 0x919,
278	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
279	MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
280	MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
281	MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
282	MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
283	MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
284	MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
285	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
286	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
287	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
288	MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
289	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
290	MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
291	MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
292	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
296	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
298	MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
299	MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
300	MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
301	MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
302	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
303	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
304	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
305	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
306	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
307	MLX5_CMD_OP_CREATE_UCTX = 0xa04,
308	MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
309	MLX5_CMD_OP_CREATE_UMEM = 0xa08,
310	MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
311	MLX5_CMD_OP_SYNC_STEERING = 0xb00,
312	MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
313	MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
314	MLX5_CMD_OP_SYNC_CRYPTO = 0xb12,
315	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
316	MLX5_CMD_OP_MAX
317	};
318
319	/* Valid range for general commands that don't work over an object */
320	enum {
321	MLX5_CMD_OP_GENERAL_START = 0xb00,
322	MLX5_CMD_OP_GENERAL_END = 0xd00,
323	};
324
325	enum {
326	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
327	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
328	};
329
330	enum {
331	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
332	};
333
334	struct mlx5_ifc_flow_table_fields_supported_bits {
335	u8 outer_dmac[0x1];
336	u8 outer_smac[0x1];
337	u8 outer_ether_type[0x1];
338	u8 outer_ip_version[0x1];
339	u8 outer_first_prio[0x1];
340	u8 outer_first_cfi[0x1];
341	u8 outer_first_vid[0x1];
342	u8 outer_ipv4_ttl[0x1];
343	u8 outer_second_prio[0x1];
344	u8 outer_second_cfi[0x1];
345	u8 outer_second_vid[0x1];
346	u8 reserved_at_b[0x1];
347	u8 outer_sip[0x1];
348	u8 outer_dip[0x1];
349	u8 outer_frag[0x1];
350	u8 outer_ip_protocol[0x1];
351	u8 outer_ip_ecn[0x1];
352	u8 outer_ip_dscp[0x1];
353	u8 outer_udp_sport[0x1];
354	u8 outer_udp_dport[0x1];
355	u8 outer_tcp_sport[0x1];
356	u8 outer_tcp_dport[0x1];
357	u8 outer_tcp_flags[0x1];
358	u8 outer_gre_protocol[0x1];
359	u8 outer_gre_key[0x1];
360	u8 outer_vxlan_vni[0x1];
361	u8 outer_geneve_vni[0x1];
362	u8 outer_geneve_oam[0x1];
363	u8 outer_geneve_protocol_type[0x1];
364	u8 outer_geneve_opt_len[0x1];
365	u8 source_vhca_port[0x1];
366	u8 source_eswitch_port[0x1];
367
368	u8 inner_dmac[0x1];
369	u8 inner_smac[0x1];
370	u8 inner_ether_type[0x1];
371	u8 inner_ip_version[0x1];
372	u8 inner_first_prio[0x1];
373	u8 inner_first_cfi[0x1];
374	u8 inner_first_vid[0x1];
375	u8 reserved_at_27[0x1];
376	u8 inner_second_prio[0x1];
377	u8 inner_second_cfi[0x1];
378	u8 inner_second_vid[0x1];
379	u8 reserved_at_2b[0x1];
380	u8 inner_sip[0x1];
381	u8 inner_dip[0x1];
382	u8 inner_frag[0x1];
383	u8 inner_ip_protocol[0x1];
384	u8 inner_ip_ecn[0x1];
385	u8 inner_ip_dscp[0x1];
386	u8 inner_udp_sport[0x1];
387	u8 inner_udp_dport[0x1];
388	u8 inner_tcp_sport[0x1];
389	u8 inner_tcp_dport[0x1];
390	u8 inner_tcp_flags[0x1];
391	u8 reserved_at_37[0x9];
392
393	u8 geneve_tlv_option_0_data[0x1];
394	u8 geneve_tlv_option_0_exist[0x1];
395	u8 reserved_at_42[0x3];
396	u8 outer_first_mpls_over_udp[0x4];
397	u8 outer_first_mpls_over_gre[0x4];
398	u8 inner_first_mpls[0x4];
399	u8 outer_first_mpls[0x4];
400	u8 reserved_at_55[0x2];
401	u8 outer_esp_spi[0x1];
402	u8 reserved_at_58[0x2];
403	u8 bth_dst_qp[0x1];
404	u8 reserved_at_5b[0x5];
405
406	u8 reserved_at_60[0x18];
407	u8 metadata_reg_c_7[0x1];
408	u8 metadata_reg_c_6[0x1];
409	u8 metadata_reg_c_5[0x1];
410	u8 metadata_reg_c_4[0x1];
411	u8 metadata_reg_c_3[0x1];
412	u8 metadata_reg_c_2[0x1];
413	u8 metadata_reg_c_1[0x1];
414	u8 metadata_reg_c_0[0x1];
415	};
416
417	/* Table 2170 - Flow Table Fields Supported 2 Format */
418	struct mlx5_ifc_flow_table_fields_supported_2_bits {
419	u8 reserved_at_0[0xe];
420	u8 bth_opcode[0x1];
421	u8 reserved_at_f[0x1];
422	u8 tunnel_header_0_1[0x1];
423	u8 reserved_at_11[0xf];
424
425	u8 reserved_at_20[0x60];
426	};
427
428	struct mlx5_ifc_flow_table_prop_layout_bits {
429	u8 ft_support[0x1];
430	u8 reserved_at_1[0x1];
431	u8 flow_counter[0x1];
432	u8 flow_modify_en[0x1];
433	u8 modify_root[0x1];
434	u8 identified_miss_table_mode[0x1];
435	u8 flow_table_modify[0x1];
436	u8 reformat[0x1];
437	u8 decap[0x1];
438	u8 reserved_at_9[0x1];
439	u8 pop_vlan[0x1];
440	u8 push_vlan[0x1];
441	u8 reserved_at_c[0x1];
442	u8 pop_vlan_2[0x1];
443	u8 push_vlan_2[0x1];
444	u8 reformat_and_vlan_action[0x1];
445	u8 reserved_at_10[0x1];
446	u8 sw_owner[0x1];
447	u8 reformat_l3_tunnel_to_l2[0x1];
448	u8 reformat_l2_to_l3_tunnel[0x1];
449	u8 reformat_and_modify_action[0x1];
450	u8 ignore_flow_level[0x1];
451	u8 reserved_at_16[0x1];
452	u8 table_miss_action_domain[0x1];
453	u8 termination_table[0x1];
454	u8 reformat_and_fwd_to_table[0x1];
455	u8 reserved_at_1a[0x2];
456	u8 ipsec_encrypt[0x1];
457	u8 ipsec_decrypt[0x1];
458	u8 sw_owner_v2[0x1];
459	u8 reserved_at_1f[0x1];
460
461	u8 termination_table_raw_traffic[0x1];
462	u8 reserved_at_21[0x1];
463	u8 log_max_ft_size[0x6];
464	u8 log_max_modify_header_context[0x8];
465	u8 max_modify_header_actions[0x8];
466	u8 max_ft_level[0x8];
467
468	u8 reformat_add_esp_trasport[0x1];
469	u8 reformat_l2_to_l3_esp_tunnel[0x1];
470	u8 reformat_add_esp_transport_over_udp[0x1];
471	u8 reformat_del_esp_trasport[0x1];
472	u8 reformat_l3_esp_tunnel_to_l2[0x1];
473	u8 reformat_del_esp_transport_over_udp[0x1];
474	u8 execute_aso[0x1];
475	u8 reserved_at_47[0x19];
476
477	u8 reserved_at_60[0x2];
478	u8 reformat_insert[0x1];
479	u8 reformat_remove[0x1];
480	u8 macsec_encrypt[0x1];
481	u8 macsec_decrypt[0x1];
482	u8 reserved_at_66[0x2];
483	u8 reformat_add_macsec[0x1];
484	u8 reformat_remove_macsec[0x1];
485	u8 reserved_at_6a[0xe];
486	u8 log_max_ft_num[0x8];
487
488	u8 reserved_at_80[0x10];
489	u8 log_max_flow_counter[0x8];
490	u8 log_max_destination[0x8];
491
492	u8 reserved_at_a0[0x18];
493	u8 log_max_flow[0x8];
494
495	u8 reserved_at_c0[0x40];
496
497	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
498
499	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
500	};
501
502	struct mlx5_ifc_odp_per_transport_service_cap_bits {
503	u8 send[0x1];
504	u8 receive[0x1];
505	u8 write[0x1];
506	u8 read[0x1];
507	u8 atomic[0x1];
508	u8 srq_receive[0x1];
509	u8 reserved_at_6[0x1a];
510	};
511
512	struct mlx5_ifc_ipv4_layout_bits {
513	u8 reserved_at_0[0x60];
514
515	u8 ipv4[0x20];
516	};
517
518	struct mlx5_ifc_ipv6_layout_bits {
519	u8 ipv6[16][0x8];
520	};
521
522	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
523	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
524	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
525	u8 reserved_at_0[0x80];
526	};
527
528	struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
529	u8 smac_47_16[0x20];
530
531	u8 smac_15_0[0x10];
532	u8 ethertype[0x10];
533
534	u8 dmac_47_16[0x20];
535
536	u8 dmac_15_0[0x10];
537	u8 first_prio[0x3];
538	u8 first_cfi[0x1];
539	u8 first_vid[0xc];
540
541	u8 ip_protocol[0x8];
542	u8 ip_dscp[0x6];
543	u8 ip_ecn[0x2];
544	u8 cvlan_tag[0x1];
545	u8 svlan_tag[0x1];
546	u8 frag[0x1];
547	u8 ip_version[0x4];
548	u8 tcp_flags[0x9];
549
550	u8 tcp_sport[0x10];
551	u8 tcp_dport[0x10];
552
553	u8 reserved_at_c0[0x10];
554	u8 ipv4_ihl[0x4];
555	u8 reserved_at_c4[0x4];
556
557	u8 ttl_hoplimit[0x8];
558
559	u8 udp_sport[0x10];
560	u8 udp_dport[0x10];
561
562	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
563
564	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
565	};
566
567	struct mlx5_ifc_nvgre_key_bits {
568	u8 hi[0x18];
569	u8 lo[0x8];
570	};
571
572	union mlx5_ifc_gre_key_bits {
573	struct mlx5_ifc_nvgre_key_bits nvgre;
574	u8 key[0x20];
575	};
576
577	struct mlx5_ifc_fte_match_set_misc_bits {
578	u8 gre_c_present[0x1];
579	u8 reserved_at_1[0x1];
580	u8 gre_k_present[0x1];
581	u8 gre_s_present[0x1];
582	u8 source_vhca_port[0x4];
583	u8 source_sqn[0x18];
584
585	u8 source_eswitch_owner_vhca_id[0x10];
586	u8 source_port[0x10];
587
588	u8 outer_second_prio[0x3];
589	u8 outer_second_cfi[0x1];
590	u8 outer_second_vid[0xc];
591	u8 inner_second_prio[0x3];
592	u8 inner_second_cfi[0x1];
593	u8 inner_second_vid[0xc];
594
595	u8 outer_second_cvlan_tag[0x1];
596	u8 inner_second_cvlan_tag[0x1];
597	u8 outer_second_svlan_tag[0x1];
598	u8 inner_second_svlan_tag[0x1];
599	u8 reserved_at_64[0xc];
600	u8 gre_protocol[0x10];
601
602	union mlx5_ifc_gre_key_bits gre_key;
603
604	u8 vxlan_vni[0x18];
605	u8 bth_opcode[0x8];
606
607	u8 geneve_vni[0x18];
608	u8 reserved_at_d8[0x6];
609	u8 geneve_tlv_option_0_exist[0x1];
610	u8 geneve_oam[0x1];
611
612	u8 reserved_at_e0[0xc];
613	u8 outer_ipv6_flow_label[0x14];
614
615	u8 reserved_at_100[0xc];
616	u8 inner_ipv6_flow_label[0x14];
617
618	u8 reserved_at_120[0xa];
619	u8 geneve_opt_len[0x6];
620	u8 geneve_protocol_type[0x10];
621
622	u8 reserved_at_140[0x8];
623	u8 bth_dst_qp[0x18];
624	u8 reserved_at_160[0x20];
625	u8 outer_esp_spi[0x20];
626	u8 reserved_at_1a0[0x60];
627	};
628
629	struct mlx5_ifc_fte_match_mpls_bits {
630	u8 mpls_label[0x14];
631	u8 mpls_exp[0x3];
632	u8 mpls_s_bos[0x1];
633	u8 mpls_ttl[0x8];
634	};
635
636	struct mlx5_ifc_fte_match_set_misc2_bits {
637	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
638
639	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
640
641	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
642
643	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
644
645	u8 metadata_reg_c_7[0x20];
646
647	u8 metadata_reg_c_6[0x20];
648
649	u8 metadata_reg_c_5[0x20];
650
651	u8 metadata_reg_c_4[0x20];
652
653	u8 metadata_reg_c_3[0x20];
654
655	u8 metadata_reg_c_2[0x20];
656
657	u8 metadata_reg_c_1[0x20];
658
659	u8 metadata_reg_c_0[0x20];
660
661	u8 metadata_reg_a[0x20];
662
663	u8 reserved_at_1a0[0x8];
664
665	u8 macsec_syndrome[0x8];
666	u8 ipsec_syndrome[0x8];
667	u8 reserved_at_1b8[0x8];
668
669	u8 reserved_at_1c0[0x40];
670	};
671
672	struct mlx5_ifc_fte_match_set_misc3_bits {
673	u8 inner_tcp_seq_num[0x20];
674
675	u8 outer_tcp_seq_num[0x20];
676
677	u8 inner_tcp_ack_num[0x20];
678
679	u8 outer_tcp_ack_num[0x20];
680
681	u8 reserved_at_80[0x8];
682	u8 outer_vxlan_gpe_vni[0x18];
683
684	u8 outer_vxlan_gpe_next_protocol[0x8];
685	u8 outer_vxlan_gpe_flags[0x8];
686	u8 reserved_at_b0[0x10];
687
688	u8 icmp_header_data[0x20];
689
690	u8 icmpv6_header_data[0x20];
691
692	u8 icmp_type[0x8];
693	u8 icmp_code[0x8];
694	u8 icmpv6_type[0x8];
695	u8 icmpv6_code[0x8];
696
697	u8 geneve_tlv_option_0_data[0x20];
698
699	u8 gtpu_teid[0x20];
700
701	u8 gtpu_msg_type[0x8];
702	u8 gtpu_msg_flags[0x8];
703	u8 reserved_at_170[0x10];
704
705	u8 gtpu_dw_2[0x20];
706
707	u8 gtpu_first_ext_dw_0[0x20];
708
709	u8 gtpu_dw_0[0x20];
710
711	u8 reserved_at_1e0[0x20];
712	};
713
714	struct mlx5_ifc_fte_match_set_misc4_bits {
715	u8 prog_sample_field_value_0[0x20];
716
717	u8 prog_sample_field_id_0[0x20];
718
719	u8 prog_sample_field_value_1[0x20];
720
721	u8 prog_sample_field_id_1[0x20];
722
723	u8 prog_sample_field_value_2[0x20];
724
725	u8 prog_sample_field_id_2[0x20];
726
727	u8 prog_sample_field_value_3[0x20];
728
729	u8 prog_sample_field_id_3[0x20];
730
731	u8 reserved_at_100[0x100];
732	};
733
734	struct mlx5_ifc_fte_match_set_misc5_bits {
735	u8 macsec_tag_0[0x20];
736
737	u8 macsec_tag_1[0x20];
738
739	u8 macsec_tag_2[0x20];
740
741	u8 macsec_tag_3[0x20];
742
743	u8 tunnel_header_0[0x20];
744
745	u8 tunnel_header_1[0x20];
746
747	u8 tunnel_header_2[0x20];
748
749	u8 tunnel_header_3[0x20];
750
751	u8 reserved_at_100[0x100];
752	};
753
754	struct mlx5_ifc_cmd_pas_bits {
755	u8 pa_h[0x20];
756
757	u8 pa_l[0x14];
758	u8 reserved_at_34[0xc];
759	};
760
761	struct mlx5_ifc_uint64_bits {
762	u8 hi[0x20];
763
764	u8 lo[0x20];
765	};
766
767	enum {
768	MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
769	MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
770	MLX5_ADS_STAT_RATE_10GBPS = 0x8,
771	MLX5_ADS_STAT_RATE_30GBPS = 0x9,
772	MLX5_ADS_STAT_RATE_5GBPS = 0xa,
773	MLX5_ADS_STAT_RATE_20GBPS = 0xb,
774	MLX5_ADS_STAT_RATE_40GBPS = 0xc,
775	MLX5_ADS_STAT_RATE_60GBPS = 0xd,
776	MLX5_ADS_STAT_RATE_80GBPS = 0xe,
777	MLX5_ADS_STAT_RATE_120GBPS = 0xf,
778	};
779
780	struct mlx5_ifc_ads_bits {
781	u8 fl[0x1];
782	u8 free_ar[0x1];
783	u8 reserved_at_2[0xe];
784	u8 pkey_index[0x10];
785
786	u8 reserved_at_20[0x8];
787	u8 grh[0x1];
788	u8 mlid[0x7];
789	u8 rlid[0x10];
790
791	u8 ack_timeout[0x5];
792	u8 reserved_at_45[0x3];
793	u8 src_addr_index[0x8];
794	u8 reserved_at_50[0x4];
795	u8 stat_rate[0x4];
796	u8 hop_limit[0x8];
797
798	u8 reserved_at_60[0x4];
799	u8 tclass[0x8];
800	u8 flow_label[0x14];
801
802	u8 rgid_rip[16][0x8];
803
804	u8 reserved_at_100[0x4];
805	u8 f_dscp[0x1];
806	u8 f_ecn[0x1];
807	u8 reserved_at_106[0x1];
808	u8 f_eth_prio[0x1];
809	u8 ecn[0x2];
810	u8 dscp[0x6];
811	u8 udp_sport[0x10];
812
813	u8 dei_cfi[0x1];
814	u8 eth_prio[0x3];
815	u8 sl[0x4];
816	u8 vhca_port_num[0x8];
817	u8 rmac_47_32[0x10];
818
819	u8 rmac_31_0[0x20];
820	};
821
822	struct mlx5_ifc_flow_table_nic_cap_bits {
823	u8 nic_rx_multi_path_tirs[0x1];
824	u8 nic_rx_multi_path_tirs_fts[0x1];
825	u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
826	u8 reserved_at_3[0x4];
827	u8 sw_owner_reformat_supported[0x1];
828	u8 reserved_at_8[0x18];
829
830	u8 encap_general_header[0x1];
831	u8 reserved_at_21[0xa];
832	u8 log_max_packet_reformat_context[0x5];
833	u8 reserved_at_30[0x6];
834	u8 max_encap_header_size[0xa];
835	u8 reserved_at_40[0x1c0];
836
837	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
838
839	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
840
841	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
842
843	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
844
845	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
846
847	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
848
849	u8 reserved_at_e00[0x700];
850
851	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
852
853	u8 reserved_at_1580[0x280];
854
855	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
856
857	u8 reserved_at_1880[0x780];
858
859	u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
860
861	u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
862
863	u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
864
865	u8 reserved_at_20c0[0x5f40];
866	};
867
868	struct mlx5_ifc_port_selection_cap_bits {
869	u8 reserved_at_0[0x10];
870	u8 port_select_flow_table[0x1];
871	u8 reserved_at_11[0x1];
872	u8 port_select_flow_table_bypass[0x1];
873	u8 reserved_at_13[0xd];
874
875	u8 reserved_at_20[0x1e0];
876
877	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
878
879	u8 reserved_at_400[0x7c00];
880	};
881
882	enum {
883	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
884	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
885	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
886	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
887	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
888	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
889	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
890	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
891	};
892
893	struct mlx5_ifc_flow_table_eswitch_cap_bits {
894	u8 fdb_to_vport_reg_c_id[0x8];
895	u8 reserved_at_8[0x5];
896	u8 fdb_uplink_hairpin[0x1];
897	u8 fdb_multi_path_any_table_limit_regc[0x1];
898	u8 reserved_at_f[0x3];
899	u8 fdb_multi_path_any_table[0x1];
900	u8 reserved_at_13[0x2];
901	u8 fdb_modify_header_fwd_to_table[0x1];
902	u8 fdb_ipv4_ttl_modify[0x1];
903	u8 flow_source[0x1];
904	u8 reserved_at_18[0x2];
905	u8 multi_fdb_encap[0x1];
906	u8 egress_acl_forward_to_vport[0x1];
907	u8 fdb_multi_path_to_table[0x1];
908	u8 reserved_at_1d[0x3];
909
910	u8 reserved_at_20[0x1e0];
911
912	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
913
914	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
915
916	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
917
918	u8 reserved_at_800[0xC00];
919
920	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
921
922	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
923
924	u8 reserved_at_1500[0x300];
925
926	u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
927
928	u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
929
930	u8 sw_steering_uplink_icm_address_rx[0x40];
931
932	u8 sw_steering_uplink_icm_address_tx[0x40];
933
934	u8 reserved_at_1900[0x6700];
935	};
936
937	enum {
938	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
939	MLX5_COUNTER_FLOW_ESWITCH = 0x1,
940	};
941
942	struct mlx5_ifc_e_switch_cap_bits {
943	u8 vport_svlan_strip[0x1];
944	u8 vport_cvlan_strip[0x1];
945	u8 vport_svlan_insert[0x1];
946	u8 vport_cvlan_insert_if_not_exist[0x1];
947	u8 vport_cvlan_insert_overwrite[0x1];
948	u8 reserved_at_5[0x1];
949	u8 vport_cvlan_insert_always[0x1];
950	u8 esw_shared_ingress_acl[0x1];
951	u8 esw_uplink_ingress_acl[0x1];
952	u8 root_ft_on_other_esw[0x1];
953	u8 reserved_at_a[0xf];
954	u8 esw_functions_changed[0x1];
955	u8 reserved_at_1a[0x1];
956	u8 ecpf_vport_exists[0x1];
957	u8 counter_eswitch_affinity[0x1];
958	u8 merged_eswitch[0x1];
959	u8 nic_vport_node_guid_modify[0x1];
960	u8 nic_vport_port_guid_modify[0x1];
961
962	u8 vxlan_encap_decap[0x1];
963	u8 nvgre_encap_decap[0x1];
964	u8 reserved_at_22[0x1];
965	u8 log_max_fdb_encap_uplink[0x5];
966	u8 reserved_at_21[0x3];
967	u8 log_max_packet_reformat_context[0x5];
968	u8 reserved_2b[0x6];
969	u8 max_encap_header_size[0xa];
970
971	u8 reserved_at_40[0xb];
972	u8 log_max_esw_sf[0x5];
973	u8 esw_sf_base_id[0x10];
974
975	u8 reserved_at_60[0x7a0];
976
977	};
978
979	struct mlx5_ifc_qos_cap_bits {
980	u8 packet_pacing[0x1];
981	u8 esw_scheduling[0x1];
982	u8 esw_bw_share[0x1];
983	u8 esw_rate_limit[0x1];
984	u8 reserved_at_4[0x1];
985	u8 packet_pacing_burst_bound[0x1];
986	u8 packet_pacing_typical_size[0x1];
987	u8 reserved_at_7[0x1];
988	u8 nic_sq_scheduling[0x1];
989	u8 nic_bw_share[0x1];
990	u8 nic_rate_limit[0x1];
991	u8 packet_pacing_uid[0x1];
992	u8 log_esw_max_sched_depth[0x4];
993	u8 reserved_at_10[0x10];
994
995	u8 reserved_at_20[0xb];
996	u8 log_max_qos_nic_queue_group[0x5];
997	u8 reserved_at_30[0x10];
998
999	u8 packet_pacing_max_rate[0x20];
1000
1001	u8 packet_pacing_min_rate[0x20];
1002
1003	u8 reserved_at_80[0x10];
1004	u8 packet_pacing_rate_table_size[0x10];
1005
1006	u8 esw_element_type[0x10];
1007	u8 esw_tsar_type[0x10];
1008
1009	u8 reserved_at_c0[0x10];
1010	u8 max_qos_para_vport[0x10];
1011
1012	u8 max_tsar_bw_share[0x20];
1013
1014	u8 reserved_at_100[0x20];
1015
1016	u8 reserved_at_120[0x3];
1017	u8 log_meter_aso_granularity[0x5];
1018	u8 reserved_at_128[0x3];
1019	u8 log_meter_aso_max_alloc[0x5];
1020	u8 reserved_at_130[0x3];
1021	u8 log_max_num_meter_aso[0x5];
1022	u8 reserved_at_138[0x8];
1023
1024	u8 reserved_at_140[0x6c0];
1025	};
1026
1027	struct mlx5_ifc_debug_cap_bits {
1028	u8 core_dump_general[0x1];
1029	u8 core_dump_qp[0x1];
1030	u8 reserved_at_2[0x7];
1031	u8 resource_dump[0x1];
1032	u8 reserved_at_a[0x16];
1033
1034	u8 reserved_at_20[0x2];
1035	u8 stall_detect[0x1];
1036	u8 reserved_at_23[0x1d];
1037
1038	u8 reserved_at_40[0x7c0];
1039	};
1040
1041	struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1042	u8 csum_cap[0x1];
1043	u8 vlan_cap[0x1];
1044	u8 lro_cap[0x1];
1045	u8 lro_psh_flag[0x1];
1046	u8 lro_time_stamp[0x1];
1047	u8 reserved_at_5[0x2];
1048	u8 wqe_vlan_insert[0x1];
1049	u8 self_lb_en_modifiable[0x1];
1050	u8 reserved_at_9[0x2];
1051	u8 max_lso_cap[0x5];
1052	u8 multi_pkt_send_wqe[0x2];
1053	u8 wqe_inline_mode[0x2];
1054	u8 rss_ind_tbl_cap[0x4];
1055	u8 reg_umr_sq[0x1];
1056	u8 scatter_fcs[0x1];
1057	u8 enhanced_multi_pkt_send_wqe[0x1];
1058	u8 tunnel_lso_const_out_ip_id[0x1];
1059	u8 tunnel_lro_gre[0x1];
1060	u8 tunnel_lro_vxlan[0x1];
1061	u8 tunnel_stateless_gre[0x1];
1062	u8 tunnel_stateless_vxlan[0x1];
1063
1064	u8 swp[0x1];
1065	u8 swp_csum[0x1];
1066	u8 swp_lso[0x1];
1067	u8 cqe_checksum_full[0x1];
1068	u8 tunnel_stateless_geneve_tx[0x1];
1069	u8 tunnel_stateless_mpls_over_udp[0x1];
1070	u8 tunnel_stateless_mpls_over_gre[0x1];
1071	u8 tunnel_stateless_vxlan_gpe[0x1];
1072	u8 tunnel_stateless_ipv4_over_vxlan[0x1];
1073	u8 tunnel_stateless_ip_over_ip[0x1];
1074	u8 insert_trailer[0x1];
1075	u8 reserved_at_2b[0x1];
1076	u8 tunnel_stateless_ip_over_ip_rx[0x1];
1077	u8 tunnel_stateless_ip_over_ip_tx[0x1];
1078	u8 reserved_at_2e[0x2];
1079	u8 max_vxlan_udp_ports[0x8];
1080	u8 reserved_at_38[0x6];
1081	u8 max_geneve_opt_len[0x1];
1082	u8 tunnel_stateless_geneve_rx[0x1];
1083
1084	u8 reserved_at_40[0x10];
1085	u8 lro_min_mss_size[0x10];
1086
1087	u8 reserved_at_60[0x120];
1088
1089	u8 lro_timer_supported_periods[4][0x20];
1090
1091	u8 reserved_at_200[0x600];
1092	};
1093
1094	enum {
1095	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1096	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1097	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1098	};
1099
1100	struct mlx5_ifc_roce_cap_bits {
1101	u8 roce_apm[0x1];
1102	u8 reserved_at_1[0x3];
1103	u8 sw_r_roce_src_udp_port[0x1];
1104	u8 fl_rc_qp_when_roce_disabled[0x1];
1105	u8 fl_rc_qp_when_roce_enabled[0x1];
1106	u8 reserved_at_7[0x1];
1107	u8 qp_ooo_transmit_default[0x1];
1108	u8 reserved_at_9[0x15];
1109	u8 qp_ts_format[0x2];
1110
1111	u8 reserved_at_20[0x60];
1112
1113	u8 reserved_at_80[0xc];
1114	u8 l3_type[0x4];
1115	u8 reserved_at_90[0x8];
1116	u8 roce_version[0x8];
1117
1118	u8 reserved_at_a0[0x10];
1119	u8 r_roce_dest_udp_port[0x10];
1120
1121	u8 r_roce_max_src_udp_port[0x10];
1122	u8 r_roce_min_src_udp_port[0x10];
1123
1124	u8 reserved_at_e0[0x10];
1125	u8 roce_address_table_size[0x10];
1126
1127	u8 reserved_at_100[0x700];
1128	};
1129
1130	struct mlx5_ifc_sync_steering_in_bits {
1131	u8 opcode[0x10];
1132	u8 uid[0x10];
1133
1134	u8 reserved_at_20[0x10];
1135	u8 op_mod[0x10];
1136
1137	u8 reserved_at_40[0xc0];
1138	};
1139
1140	struct mlx5_ifc_sync_steering_out_bits {
1141	u8 status[0x8];
1142	u8 reserved_at_8[0x18];
1143
1144	u8 syndrome[0x20];
1145
1146	u8 reserved_at_40[0x40];
1147	};
1148
1149	struct mlx5_ifc_sync_crypto_in_bits {
1150	u8 opcode[0x10];
1151	u8 uid[0x10];
1152
1153	u8 reserved_at_20[0x10];
1154	u8 op_mod[0x10];
1155
1156	u8 reserved_at_40[0x20];
1157
1158	u8 reserved_at_60[0x10];
1159	u8 crypto_type[0x10];
1160
1161	u8 reserved_at_80[0x80];
1162	};
1163
1164	struct mlx5_ifc_sync_crypto_out_bits {
1165	u8 status[0x8];
1166	u8 reserved_at_8[0x18];
1167
1168	u8 syndrome[0x20];
1169
1170	u8 reserved_at_40[0x40];
1171	};
1172
1173	struct mlx5_ifc_device_mem_cap_bits {
1174	u8 memic[0x1];
1175	u8 reserved_at_1[0x1f];
1176
1177	u8 reserved_at_20[0xb];
1178	u8 log_min_memic_alloc_size[0x5];
1179	u8 reserved_at_30[0x8];
1180	u8 log_max_memic_addr_alignment[0x8];
1181
1182	u8 memic_bar_start_addr[0x40];
1183
1184	u8 memic_bar_size[0x20];
1185
1186	u8 max_memic_size[0x20];
1187
1188	u8 steering_sw_icm_start_address[0x40];
1189
1190	u8 reserved_at_100[0x8];
1191	u8 log_header_modify_sw_icm_size[0x8];
1192	u8 reserved_at_110[0x2];
1193	u8 log_sw_icm_alloc_granularity[0x6];
1194	u8 log_steering_sw_icm_size[0x8];
1195
1196	u8 reserved_at_120[0x18];
1197	u8 log_header_modify_pattern_sw_icm_size[0x8];
1198
1199	u8 header_modify_sw_icm_start_address[0x40];
1200
1201	u8 reserved_at_180[0x40];
1202
1203	u8 header_modify_pattern_sw_icm_start_address[0x40];
1204
1205	u8 memic_operations[0x20];
1206
1207	u8 reserved_at_220[0x5e0];
1208	};
1209
1210	struct mlx5_ifc_device_event_cap_bits {
1211	u8 user_affiliated_events[4][0x40];
1212
1213	u8 user_unaffiliated_events[4][0x40];
1214	};
1215
1216	struct mlx5_ifc_virtio_emulation_cap_bits {
1217	u8 desc_tunnel_offload_type[0x1];
1218	u8 eth_frame_offload_type[0x1];
1219	u8 virtio_version_1_0[0x1];
1220	u8 device_features_bits_mask[0xd];
1221	u8 event_mode[0x8];
1222	u8 virtio_queue_type[0x8];
1223
1224	u8 max_tunnel_desc[0x10];
1225	u8 reserved_at_30[0x3];
1226	u8 log_doorbell_stride[0x5];
1227	u8 reserved_at_38[0x3];
1228	u8 log_doorbell_bar_size[0x5];
1229
1230	u8 doorbell_bar_offset[0x40];
1231
1232	u8 max_emulated_devices[0x8];
1233	u8 max_num_virtio_queues[0x18];
1234
1235	u8 reserved_at_a0[0x20];
1236
1237	u8 reserved_at_c0[0x13];
1238	u8 desc_group_mkey_supported[0x1];
1239	u8 reserved_at_d4[0xc];
1240
1241	u8 reserved_at_e0[0x20];
1242
1243	u8 umem_1_buffer_param_a[0x20];
1244
1245	u8 umem_1_buffer_param_b[0x20];
1246
1247	u8 umem_2_buffer_param_a[0x20];
1248
1249	u8 umem_2_buffer_param_b[0x20];
1250
1251	u8 umem_3_buffer_param_a[0x20];
1252
1253	u8 umem_3_buffer_param_b[0x20];
1254
1255	u8 reserved_at_1c0[0x640];
1256	};
1257
1258	enum {
1259	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1260	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1261	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1262	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1263	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1264	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1265	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1266	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1267	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1268	};
1269
1270	enum {
1271	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1272	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1273	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1274	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1275	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1276	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1277	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1278	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1279	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1280	};
1281
1282	struct mlx5_ifc_atomic_caps_bits {
1283	u8 reserved_at_0[0x40];
1284
1285	u8 atomic_req_8B_endianness_mode[0x2];
1286	u8 reserved_at_42[0x4];
1287	u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1288
1289	u8 reserved_at_47[0x19];
1290
1291	u8 reserved_at_60[0x20];
1292
1293	u8 reserved_at_80[0x10];
1294	u8 atomic_operations[0x10];
1295
1296	u8 reserved_at_a0[0x10];
1297	u8 atomic_size_qp[0x10];
1298
1299	u8 reserved_at_c0[0x10];
1300	u8 atomic_size_dc[0x10];
1301
1302	u8 reserved_at_e0[0x720];
1303	};
1304
1305	struct mlx5_ifc_odp_cap_bits {
1306	u8 reserved_at_0[0x40];
1307
1308	u8 sig[0x1];
1309	u8 reserved_at_41[0x1f];
1310
1311	u8 reserved_at_60[0x20];
1312
1313	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1314
1315	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1316
1317	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1318
1319	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1320
1321	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1322
1323	u8 reserved_at_120[0x6E0];
1324	};
1325
1326	struct mlx5_ifc_tls_cap_bits {
1327	u8 tls_1_2_aes_gcm_128[0x1];
1328	u8 tls_1_3_aes_gcm_128[0x1];
1329	u8 tls_1_2_aes_gcm_256[0x1];
1330	u8 tls_1_3_aes_gcm_256[0x1];
1331	u8 reserved_at_4[0x1c];
1332
1333	u8 reserved_at_20[0x7e0];
1334	};
1335
1336	struct mlx5_ifc_ipsec_cap_bits {
1337	u8 ipsec_full_offload[0x1];
1338	u8 ipsec_crypto_offload[0x1];
1339	u8 ipsec_esn[0x1];
1340	u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1341	u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1342	u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1343	u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1344	u8 reserved_at_7[0x4];
1345	u8 log_max_ipsec_offload[0x5];
1346	u8 reserved_at_10[0x10];
1347
1348	u8 min_log_ipsec_full_replay_window[0x8];
1349	u8 max_log_ipsec_full_replay_window[0x8];
1350	u8 reserved_at_30[0x7d0];
1351	};
1352
1353	struct mlx5_ifc_macsec_cap_bits {
1354	u8 macsec_epn[0x1];
1355	u8 reserved_at_1[0x2];
1356	u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1357	u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1358	u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1359	u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1360	u8 reserved_at_7[0x4];
1361	u8 log_max_macsec_offload[0x5];
1362	u8 reserved_at_10[0x10];
1363
1364	u8 min_log_macsec_full_replay_window[0x8];
1365	u8 max_log_macsec_full_replay_window[0x8];
1366	u8 reserved_at_30[0x10];
1367
1368	u8 reserved_at_40[0x7c0];
1369	};
1370
1371	enum {
1372	MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1373	MLX5_WQ_TYPE_CYCLIC = 0x1,
1374	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1375	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1376	};
1377
1378	enum {
1379	MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1380	MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1381	};
1382
1383	enum {
1384	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1385	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1386	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1387	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1388	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1389	};
1390
1391	enum {
1392	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1393	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1394	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1395	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1396	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1397	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1398	};
1399
1400	enum {
1401	MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1402	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1403	};
1404
1405	enum {
1406	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1407	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1408	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1409	};
1410
1411	enum {
1412	MLX5_CAP_PORT_TYPE_IB = 0x0,
1413	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1414	};
1415
1416	enum {
1417	MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1418	MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1419	MLX5_CAP_UMR_FENCE_NONE = 0x2,
1420	};
1421
1422	enum {
1423	MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1424	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
1425	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1426	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1427	MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1428	MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1429	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1430	MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1431	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1432	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1433	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1434	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
1435	};
1436
1437	enum {
1438	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1439	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1440	};
1441
1442	#define MLX5_FC_BULK_SIZE_FACTOR 128
1443
1444	enum mlx5_fc_bulk_alloc_bitmask {
1445	MLX5_FC_BULK_128 = (1 << 0),
1446	MLX5_FC_BULK_256 = (1 << 1),
1447	MLX5_FC_BULK_512 = (1 << 2),
1448	MLX5_FC_BULK_1024 = (1 << 3),
1449	MLX5_FC_BULK_2048 = (1 << 4),
1450	MLX5_FC_BULK_4096 = (1 << 5),
1451	MLX5_FC_BULK_8192 = (1 << 6),
1452	MLX5_FC_BULK_16384 = (1 << 7),
1453	};
1454
1455	#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1456
1457	#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1458
1459	enum {
1460	MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1461	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1462	MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
1463	};
1464
1465	struct mlx5_ifc_cmd_hca_cap_bits {
1466	u8 reserved_at_0[0x10];
1467	u8 shared_object_to_user_object_allowed[0x1];
1468	u8 reserved_at_13[0xe];
1469	u8 vhca_resource_manager[0x1];
1470
1471	u8 hca_cap_2[0x1];
1472	u8 create_lag_when_not_master_up[0x1];
1473	u8 dtor[0x1];
1474	u8 event_on_vhca_state_teardown_request[0x1];
1475	u8 event_on_vhca_state_in_use[0x1];
1476	u8 event_on_vhca_state_active[0x1];
1477	u8 event_on_vhca_state_allocated[0x1];
1478	u8 event_on_vhca_state_invalid[0x1];
1479	u8 reserved_at_28[0x8];
1480	u8 vhca_id[0x10];
1481
1482	u8 reserved_at_40[0x40];
1483
1484	u8 log_max_srq_sz[0x8];
1485	u8 log_max_qp_sz[0x8];
1486	u8 event_cap[0x1];
1487	u8 reserved_at_91[0x2];
1488	u8 isolate_vl_tc_new[0x1];
1489	u8 reserved_at_94[0x4];
1490	u8 prio_tag_required[0x1];
1491	u8 reserved_at_99[0x2];
1492	u8 log_max_qp[0x5];
1493
1494	u8 reserved_at_a0[0x3];
1495	u8 ece_support[0x1];
1496	u8 reserved_at_a4[0x5];
1497	u8 reg_c_preserve[0x1];
1498	u8 reserved_at_aa[0x1];
1499	u8 log_max_srq[0x5];
1500	u8 reserved_at_b0[0x1];
1501	u8 uplink_follow[0x1];
1502	u8 ts_cqe_to_dest_cqn[0x1];
1503	u8 reserved_at_b3[0x6];
1504	u8 go_back_n[0x1];
1505	u8 shampo[0x1];
1506	u8 reserved_at_bb[0x5];
1507
1508	u8 max_sgl_for_optimized_performance[0x8];
1509	u8 log_max_cq_sz[0x8];
1510	u8 relaxed_ordering_write_umr[0x1];
1511	u8 relaxed_ordering_read_umr[0x1];
1512	u8 reserved_at_d2[0x7];
1513	u8 virtio_net_device_emualtion_manager[0x1];
1514	u8 virtio_blk_device_emualtion_manager[0x1];
1515	u8 log_max_cq[0x5];
1516
1517	u8 log_max_eq_sz[0x8];
1518	u8 relaxed_ordering_write[0x1];
1519	u8 relaxed_ordering_read_pci_enabled[0x1];
1520	u8 log_max_mkey[0x6];
1521	u8 reserved_at_f0[0x6];
1522	u8 terminate_scatter_list_mkey[0x1];
1523	u8 repeated_mkey[0x1];
1524	u8 dump_fill_mkey[0x1];
1525	u8 reserved_at_f9[0x2];
1526	u8 fast_teardown[0x1];
1527	u8 log_max_eq[0x4];
1528
1529	u8 max_indirection[0x8];
1530	u8 fixed_buffer_size[0x1];
1531	u8 log_max_mrw_sz[0x7];
1532	u8 force_teardown[0x1];
1533	u8 reserved_at_111[0x1];
1534	u8 log_max_bsf_list_size[0x6];
1535	u8 umr_extended_translation_offset[0x1];
1536	u8 null_mkey[0x1];
1537	u8 log_max_klm_list_size[0x6];
1538
1539	u8 reserved_at_120[0x2];
1540	u8 qpc_extension[0x1];
1541	u8 reserved_at_123[0x7];
1542	u8 log_max_ra_req_dc[0x6];
1543	u8 reserved_at_130[0x2];
1544	u8 eth_wqe_too_small[0x1];
1545	u8 reserved_at_133[0x6];
1546	u8 vnic_env_cq_overrun[0x1];
1547	u8 log_max_ra_res_dc[0x6];
1548
1549	u8 reserved_at_140[0x5];
1550	u8 release_all_pages[0x1];
1551	u8 must_not_use[0x1];
1552	u8 reserved_at_147[0x2];
1553	u8 roce_accl[0x1];
1554	u8 log_max_ra_req_qp[0x6];
1555	u8 reserved_at_150[0xa];
1556	u8 log_max_ra_res_qp[0x6];
1557
1558	u8 end_pad[0x1];
1559	u8 cc_query_allowed[0x1];
1560	u8 cc_modify_allowed[0x1];
1561	u8 start_pad[0x1];
1562	u8 cache_line_128byte[0x1];
1563	u8 reserved_at_165[0x4];
1564	u8 rts2rts_qp_counters_set_id[0x1];
1565	u8 reserved_at_16a[0x2];
1566	u8 vnic_env_int_rq_oob[0x1];
1567	u8 sbcam_reg[0x1];
1568	u8 reserved_at_16e[0x1];
1569	u8 qcam_reg[0x1];
1570	u8 gid_table_size[0x10];
1571
1572	u8 out_of_seq_cnt[0x1];
1573	u8 vport_counters[0x1];
1574	u8 retransmission_q_counters[0x1];
1575	u8 debug[0x1];
1576	u8 modify_rq_counter_set_id[0x1];
1577	u8 rq_delay_drop[0x1];
1578	u8 max_qp_cnt[0xa];
1579	u8 pkey_table_size[0x10];
1580
1581	u8 vport_group_manager[0x1];
1582	u8 vhca_group_manager[0x1];
1583	u8 ib_virt[0x1];
1584	u8 eth_virt[0x1];
1585	u8 vnic_env_queue_counters[0x1];
1586	u8 ets[0x1];
1587	u8 nic_flow_table[0x1];
1588	u8 eswitch_manager[0x1];
1589	u8 device_memory[0x1];
1590	u8 mcam_reg[0x1];
1591	u8 pcam_reg[0x1];
1592	u8 local_ca_ack_delay[0x5];
1593	u8 port_module_event[0x1];
1594	u8 enhanced_error_q_counters[0x1];
1595	u8 ports_check[0x1];
1596	u8 reserved_at_1b3[0x1];
1597	u8 disable_link_up[0x1];
1598	u8 beacon_led[0x1];
1599	u8 port_type[0x2];
1600	u8 num_ports[0x8];
1601
1602	u8 reserved_at_1c0[0x1];
1603	u8 pps[0x1];
1604	u8 pps_modify[0x1];
1605	u8 log_max_msg[0x5];
1606	u8 reserved_at_1c8[0x4];
1607	u8 max_tc[0x4];
1608	u8 temp_warn_event[0x1];
1609	u8 dcbx[0x1];
1610	u8 general_notification_event[0x1];
1611	u8 reserved_at_1d3[0x2];
1612	u8 fpga[0x1];
1613	u8 rol_s[0x1];
1614	u8 rol_g[0x1];
1615	u8 reserved_at_1d8[0x1];
1616	u8 wol_s[0x1];
1617	u8 wol_g[0x1];
1618	u8 wol_a[0x1];
1619	u8 wol_b[0x1];
1620	u8 wol_m[0x1];
1621	u8 wol_u[0x1];
1622	u8 wol_p[0x1];
1623
1624	u8 stat_rate_support[0x10];
1625	u8 reserved_at_1f0[0x1];
1626	u8 pci_sync_for_fw_update_event[0x1];
1627	u8 reserved_at_1f2[0x6];
1628	u8 init2_lag_tx_port_affinity[0x1];
1629	u8 reserved_at_1fa[0x3];
1630	u8 cqe_version[0x4];
1631
1632	u8 compact_address_vector[0x1];
1633	u8 striding_rq[0x1];
1634	u8 reserved_at_202[0x1];
1635	u8 ipoib_enhanced_offloads[0x1];
1636	u8 ipoib_basic_offloads[0x1];
1637	u8 reserved_at_205[0x1];
1638	u8 repeated_block_disabled[0x1];
1639	u8 umr_modify_entity_size_disabled[0x1];
1640	u8 umr_modify_atomic_disabled[0x1];
1641	u8 umr_indirect_mkey_disabled[0x1];
1642	u8 umr_fence[0x2];
1643	u8 dc_req_scat_data_cqe[0x1];
1644	u8 reserved_at_20d[0x2];
1645	u8 drain_sigerr[0x1];
1646	u8 cmdif_checksum[0x2];
1647	u8 sigerr_cqe[0x1];
1648	u8 reserved_at_213[0x1];
1649	u8 wq_signature[0x1];
1650	u8 sctr_data_cqe[0x1];
1651	u8 reserved_at_216[0x1];
1652	u8 sho[0x1];
1653	u8 tph[0x1];
1654	u8 rf[0x1];
1655	u8 dct[0x1];
1656	u8 qos[0x1];
1657	u8 eth_net_offloads[0x1];
1658	u8 roce[0x1];
1659	u8 atomic[0x1];
1660	u8 reserved_at_21f[0x1];
1661
1662	u8 cq_oi[0x1];
1663	u8 cq_resize[0x1];
1664	u8 cq_moderation[0x1];
1665	u8 reserved_at_223[0x3];
1666	u8 cq_eq_remap[0x1];
1667	u8 pg[0x1];
1668	u8 block_lb_mc[0x1];
1669	u8 reserved_at_229[0x1];
1670	u8 scqe_break_moderation[0x1];
1671	u8 cq_period_start_from_cqe[0x1];
1672	u8 cd[0x1];
1673	u8 reserved_at_22d[0x1];
1674	u8 apm[0x1];
1675	u8 vector_calc[0x1];
1676	u8 umr_ptr_rlky[0x1];
1677	u8 imaicl[0x1];
1678	u8 qp_packet_based[0x1];
1679	u8 reserved_at_233[0x3];
1680	u8 qkv[0x1];
1681	u8 pkv[0x1];
1682	u8 set_deth_sqpn[0x1];
1683	u8 reserved_at_239[0x3];
1684	u8 xrc[0x1];
1685	u8 ud[0x1];
1686	u8 uc[0x1];
1687	u8 rc[0x1];
1688
1689	u8 uar_4k[0x1];
1690	u8 reserved_at_241[0x7];
1691	u8 fl_rc_qp_when_roce_disabled[0x1];
1692	u8 regexp_params[0x1];
1693	u8 uar_sz[0x6];
1694	u8 port_selection_cap[0x1];
1695	u8 reserved_at_251[0x1];
1696	u8 umem_uid_0[0x1];
1697	u8 reserved_at_253[0x5];
1698	u8 log_pg_sz[0x8];
1699
1700	u8 bf[0x1];
1701	u8 driver_version[0x1];
1702	u8 pad_tx_eth_packet[0x1];
1703	u8 reserved_at_263[0x3];
1704	u8 mkey_by_name[0x1];
1705	u8 reserved_at_267[0x4];
1706
1707	u8 log_bf_reg_size[0x5];
1708
1709	u8 reserved_at_270[0x3];
1710	u8 qp_error_syndrome[0x1];
1711	u8 reserved_at_274[0x2];
1712	u8 lag_dct[0x2];
1713	u8 lag_tx_port_affinity[0x1];
1714	u8 lag_native_fdb_selection[0x1];
1715	u8 reserved_at_27a[0x1];
1716	u8 lag_master[0x1];
1717	u8 num_lag_ports[0x4];
1718
1719	u8 reserved_at_280[0x10];
1720	u8 max_wqe_sz_sq[0x10];
1721
1722	u8 reserved_at_2a0[0x10];
1723	u8 max_wqe_sz_rq[0x10];
1724
1725	u8 max_flow_counter_31_16[0x10];
1726	u8 max_wqe_sz_sq_dc[0x10];
1727
1728	u8 reserved_at_2e0[0x7];
1729	u8 max_qp_mcg[0x19];
1730
1731	u8 reserved_at_300[0x10];
1732	u8 flow_counter_bulk_alloc[0x8];
1733	u8 log_max_mcg[0x8];
1734
1735	u8 reserved_at_320[0x3];
1736	u8 log_max_transport_domain[0x5];
1737	u8 reserved_at_328[0x2];
1738	u8 relaxed_ordering_read[0x1];
1739	u8 log_max_pd[0x5];
1740	u8 reserved_at_330[0x6];
1741	u8 pci_sync_for_fw_update_with_driver_unload[0x1];
1742	u8 vnic_env_cnt_steering_fail[0x1];
1743	u8 vport_counter_local_loopback[0x1];
1744	u8 q_counter_aggregation[0x1];
1745	u8 q_counter_other_vport[0x1];
1746	u8 log_max_xrcd[0x5];
1747
1748	u8 nic_receive_steering_discard[0x1];
1749	u8 receive_discard_vport_down[0x1];
1750	u8 transmit_discard_vport_down[0x1];
1751	u8 eq_overrun_count[0x1];
1752	u8 reserved_at_344[0x1];
1753	u8 invalid_command_count[0x1];
1754	u8 quota_exceeded_count[0x1];
1755	u8 reserved_at_347[0x1];
1756	u8 log_max_flow_counter_bulk[0x8];
1757	u8 max_flow_counter_15_0[0x10];
1758
1759
1760	u8 reserved_at_360[0x3];
1761	u8 log_max_rq[0x5];
1762	u8 reserved_at_368[0x3];
1763	u8 log_max_sq[0x5];
1764	u8 reserved_at_370[0x3];
1765	u8 log_max_tir[0x5];
1766	u8 reserved_at_378[0x3];
1767	u8 log_max_tis[0x5];
1768
1769	u8 basic_cyclic_rcv_wqe[0x1];
1770	u8 reserved_at_381[0x2];
1771	u8 log_max_rmp[0x5];
1772	u8 reserved_at_388[0x3];
1773	u8 log_max_rqt[0x5];
1774	u8 reserved_at_390[0x3];
1775	u8 log_max_rqt_size[0x5];
1776	u8 reserved_at_398[0x3];
1777	u8 log_max_tis_per_sq[0x5];
1778
1779	u8 ext_stride_num_range[0x1];
1780	u8 roce_rw_supported[0x1];
1781	u8 log_max_current_uc_list_wr_supported[0x1];
1782	u8 log_max_stride_sz_rq[0x5];
1783	u8 reserved_at_3a8[0x3];
1784	u8 log_min_stride_sz_rq[0x5];
1785	u8 reserved_at_3b0[0x3];
1786	u8 log_max_stride_sz_sq[0x5];
1787	u8 reserved_at_3b8[0x3];
1788	u8 log_min_stride_sz_sq[0x5];
1789
1790	u8 hairpin[0x1];
1791	u8 reserved_at_3c1[0x2];
1792	u8 log_max_hairpin_queues[0x5];
1793	u8 reserved_at_3c8[0x3];
1794	u8 log_max_hairpin_wq_data_sz[0x5];
1795	u8 reserved_at_3d0[0x3];
1796	u8 log_max_hairpin_num_packets[0x5];
1797	u8 reserved_at_3d8[0x3];
1798	u8 log_max_wq_sz[0x5];
1799
1800	u8 nic_vport_change_event[0x1];
1801	u8 disable_local_lb_uc[0x1];
1802	u8 disable_local_lb_mc[0x1];
1803	u8 log_min_hairpin_wq_data_sz[0x5];
1804	u8 reserved_at_3e8[0x2];
1805	u8 vhca_state[0x1];
1806	u8 log_max_vlan_list[0x5];
1807	u8 reserved_at_3f0[0x3];
1808	u8 log_max_current_mc_list[0x5];
1809	u8 reserved_at_3f8[0x3];
1810	u8 log_max_current_uc_list[0x5];
1811
1812	u8 general_obj_types[0x40];
1813
1814	u8 sq_ts_format[0x2];
1815	u8 rq_ts_format[0x2];
1816	u8 steering_format_version[0x4];
1817	u8 create_qp_start_hint[0x18];
1818
1819	u8 reserved_at_460[0x1];
1820	u8 ats[0x1];
1821	u8 reserved_at_462[0x1];
1822	u8 log_max_uctx[0x5];
1823	u8 reserved_at_468[0x1];
1824	u8 crypto[0x1];
1825	u8 ipsec_offload[0x1];
1826	u8 log_max_umem[0x5];
1827	u8 max_num_eqs[0x10];
1828
1829	u8 reserved_at_480[0x1];
1830	u8 tls_tx[0x1];
1831	u8 tls_rx[0x1];
1832	u8 log_max_l2_table[0x5];
1833	u8 reserved_at_488[0x8];
1834	u8 log_uar_page_sz[0x10];
1835
1836	u8 reserved_at_4a0[0x20];
1837	u8 device_frequency_mhz[0x20];
1838	u8 device_frequency_khz[0x20];
1839
1840	u8 reserved_at_500[0x20];
1841	u8 num_of_uars_per_page[0x20];
1842
1843	u8 flex_parser_protocols[0x20];
1844
1845	u8 max_geneve_tlv_options[0x8];
1846	u8 reserved_at_568[0x3];
1847	u8 max_geneve_tlv_option_data_len[0x5];
1848	u8 reserved_at_570[0x9];
1849	u8 adv_virtualization[0x1];
1850	u8 reserved_at_57a[0x6];
1851
1852	u8 reserved_at_580[0xb];
1853	u8 log_max_dci_stream_channels[0x5];
1854	u8 reserved_at_590[0x3];
1855	u8 log_max_dci_errored_streams[0x5];
1856	u8 reserved_at_598[0x8];
1857
1858	u8 reserved_at_5a0[0x10];
1859	u8 enhanced_cqe_compression[0x1];
1860	u8 reserved_at_5b1[0x2];
1861	u8 log_max_dek[0x5];
1862	u8 reserved_at_5b8[0x4];
1863	u8 mini_cqe_resp_stride_index[0x1];
1864	u8 cqe_128_always[0x1];
1865	u8 cqe_compression_128[0x1];
1866	u8 cqe_compression[0x1];
1867
1868	u8 cqe_compression_timeout[0x10];
1869	u8 cqe_compression_max_num[0x10];
1870
1871	u8 reserved_at_5e0[0x8];
1872	u8 flex_parser_id_gtpu_dw_0[0x4];
1873	u8 reserved_at_5ec[0x4];
1874	u8 tag_matching[0x1];
1875	u8 rndv_offload_rc[0x1];
1876	u8 rndv_offload_dc[0x1];
1877	u8 log_tag_matching_list_sz[0x5];
1878	u8 reserved_at_5f8[0x3];
1879	u8 log_max_xrq[0x5];
1880
1881	u8 affiliate_nic_vport_criteria[0x8];
1882	u8 native_port_num[0x8];
1883	u8 num_vhca_ports[0x8];
1884	u8 flex_parser_id_gtpu_teid[0x4];
1885	u8 reserved_at_61c[0x2];
1886	u8 sw_owner_id[0x1];
1887	u8 reserved_at_61f[0x1];
1888
1889	u8 max_num_of_monitor_counters[0x10];
1890	u8 num_ppcnt_monitor_counters[0x10];
1891
1892	u8 max_num_sf[0x10];
1893	u8 num_q_monitor_counters[0x10];
1894
1895	u8 reserved_at_660[0x20];
1896
1897	u8 sf[0x1];
1898	u8 sf_set_partition[0x1];
1899	u8 reserved_at_682[0x1];
1900	u8 log_max_sf[0x5];
1901	u8 apu[0x1];
1902	u8 reserved_at_689[0x4];
1903	u8 migration[0x1];
1904	u8 reserved_at_68e[0x2];
1905	u8 log_min_sf_size[0x8];
1906	u8 max_num_sf_partitions[0x8];
1907
1908	u8 uctx_cap[0x20];
1909
1910	u8 reserved_at_6c0[0x4];
1911	u8 flex_parser_id_geneve_tlv_option_0[0x4];
1912	u8 flex_parser_id_icmp_dw1[0x4];
1913	u8 flex_parser_id_icmp_dw0[0x4];
1914	u8 flex_parser_id_icmpv6_dw1[0x4];
1915	u8 flex_parser_id_icmpv6_dw0[0x4];
1916	u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1917	u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1918
1919	u8 max_num_match_definer[0x10];
1920	u8 sf_base_id[0x10];
1921
1922	u8 flex_parser_id_gtpu_dw_2[0x4];
1923	u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1924	u8 num_total_dynamic_vf_msix[0x18];
1925	u8 reserved_at_720[0x14];
1926	u8 dynamic_msix_table_size[0xc];
1927	u8 reserved_at_740[0xc];
1928	u8 min_dynamic_vf_msix_table_size[0x4];
1929	u8 reserved_at_750[0x4];
1930	u8 max_dynamic_vf_msix_table_size[0xc];
1931
1932	u8 reserved_at_760[0x3];
1933	u8 log_max_num_header_modify_argument[0x5];
1934	u8 reserved_at_768[0x4];
1935	u8 log_header_modify_argument_granularity[0x4];
1936	u8 reserved_at_770[0x3];
1937	u8 log_header_modify_argument_max_alloc[0x5];
1938	u8 reserved_at_778[0x8];
1939
1940	u8 vhca_tunnel_commands[0x40];
1941	u8 match_definer_format_supported[0x40];
1942	};
1943
1944	enum {
1945	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000,
1946	};
1947
1948	enum {
1949	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200,
1950	};
1951
1952	struct mlx5_ifc_cmd_hca_cap_2_bits {
1953	u8 reserved_at_0[0x80];
1954
1955	u8 migratable[0x1];
1956	u8 reserved_at_81[0x1f];
1957
1958	u8 max_reformat_insert_size[0x8];
1959	u8 max_reformat_insert_offset[0x8];
1960	u8 max_reformat_remove_size[0x8];
1961	u8 max_reformat_remove_offset[0x8];
1962
1963	u8 reserved_at_c0[0x8];
1964	u8 migration_multi_load[0x1];
1965	u8 migration_tracking_state[0x1];
1966	u8 reserved_at_ca[0x6];
1967	u8 migration_in_chunks[0x1];
1968	u8 reserved_at_d1[0xf];
1969
1970	u8 cross_vhca_object_to_object_supported[0x20];
1971
1972	u8 allowed_object_for_other_vhca_access[0x40];
1973
1974	u8 reserved_at_140[0x60];
1975
1976	u8 flow_table_type_2_type[0x8];
1977	u8 reserved_at_1a8[0x3];
1978	u8 log_min_mkey_entity_size[0x5];
1979	u8 reserved_at_1b0[0x10];
1980
1981	u8 reserved_at_1c0[0x60];
1982
1983	u8 reserved_at_220[0x1];
1984	u8 sw_vhca_id_valid[0x1];
1985	u8 sw_vhca_id[0xe];
1986	u8 reserved_at_230[0x10];
1987
1988	u8 reserved_at_240[0xb];
1989	u8 ts_cqe_metadata_size2wqe_counter[0x5];
1990	u8 reserved_at_250[0x10];
1991
1992	u8 reserved_at_260[0x120];
1993	u8 reserved_at_380[0x10];
1994	u8 ec_vf_vport_base[0x10];
1995	u8 reserved_at_3a0[0x460];
1996	};
1997
1998	enum mlx5_ifc_flow_destination_type {
1999	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
2000	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
2001	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
2002	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2003	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
2004	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
2005	};
2006
2007	enum mlx5_flow_table_miss_action {
2008	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2009	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2010	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2011	};
2012
2013	struct mlx5_ifc_dest_format_struct_bits {
2014	u8 destination_type[0x8];
2015	u8 destination_id[0x18];
2016
2017	u8 destination_eswitch_owner_vhca_id_valid[0x1];
2018	u8 packet_reformat[0x1];
2019	u8 reserved_at_22[0x6];
2020	u8 destination_table_type[0x8];
2021	u8 destination_eswitch_owner_vhca_id[0x10];
2022	};
2023
2024	struct mlx5_ifc_flow_counter_list_bits {
2025	u8 flow_counter_id[0x20];
2026
2027	u8 reserved_at_20[0x20];
2028	};
2029
2030	struct mlx5_ifc_extended_dest_format_bits {
2031	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2032
2033	u8 packet_reformat_id[0x20];
2034
2035	u8 reserved_at_60[0x20];
2036	};
2037
2038	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2039	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2040	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2041	};
2042
2043	struct mlx5_ifc_fte_match_param_bits {
2044	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2045
2046	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2047
2048	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2049
2050	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2051
2052	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2053
2054	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2055
2056	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2057
2058	u8 reserved_at_e00[0x200];
2059	};
2060
2061	enum {
2062	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2063	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2064	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2065	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2066	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2067	};
2068
2069	struct mlx5_ifc_rx_hash_field_select_bits {
2070	u8 l3_prot_type[0x1];
2071	u8 l4_prot_type[0x1];
2072	u8 selected_fields[0x1e];
2073	};
2074
2075	enum {
2076	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
2077	MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
2078	};
2079
2080	enum {
2081	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
2082	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
2083	};
2084
2085	struct mlx5_ifc_wq_bits {
2086	u8 wq_type[0x4];
2087	u8 wq_signature[0x1];
2088	u8 end_padding_mode[0x2];
2089	u8 cd_slave[0x1];
2090	u8 reserved_at_8[0x18];
2091
2092	u8 hds_skip_first_sge[0x1];
2093	u8 log2_hds_buf_size[0x3];
2094	u8 reserved_at_24[0x7];
2095	u8 page_offset[0x5];
2096	u8 lwm[0x10];
2097
2098	u8 reserved_at_40[0x8];
2099	u8 pd[0x18];
2100
2101	u8 reserved_at_60[0x8];
2102	u8 uar_page[0x18];
2103
2104	u8 dbr_addr[0x40];
2105
2106	u8 hw_counter[0x20];
2107
2108	u8 sw_counter[0x20];
2109
2110	u8 reserved_at_100[0xc];
2111	u8 log_wq_stride[0x4];
2112	u8 reserved_at_110[0x3];
2113	u8 log_wq_pg_sz[0x5];
2114	u8 reserved_at_118[0x3];
2115	u8 log_wq_sz[0x5];
2116
2117	u8 dbr_umem_valid[0x1];
2118	u8 wq_umem_valid[0x1];
2119	u8 reserved_at_122[0x1];
2120	u8 log_hairpin_num_packets[0x5];
2121	u8 reserved_at_128[0x3];
2122	u8 log_hairpin_data_sz[0x5];
2123
2124	u8 reserved_at_130[0x4];
2125	u8 log_wqe_num_of_strides[0x4];
2126	u8 two_byte_shift_en[0x1];
2127	u8 reserved_at_139[0x4];
2128	u8 log_wqe_stride_size[0x3];
2129
2130	u8 reserved_at_140[0x80];
2131
2132	u8 headers_mkey[0x20];
2133
2134	u8 shampo_enable[0x1];
2135	u8 reserved_at_1e1[0x4];
2136	u8 log_reservation_size[0x3];
2137	u8 reserved_at_1e8[0x5];
2138	u8 log_max_num_of_packets_per_reservation[0x3];
2139	u8 reserved_at_1f0[0x6];
2140	u8 log_headers_entry_size[0x2];
2141	u8 reserved_at_1f8[0x4];
2142	u8 log_headers_buffer_entry_num[0x4];
2143
2144	u8 reserved_at_200[0x400];
2145
2146	struct mlx5_ifc_cmd_pas_bits pas[];
2147	};
2148
2149	struct mlx5_ifc_rq_num_bits {
2150	u8 reserved_at_0[0x8];
2151	u8 rq_num[0x18];
2152	};
2153
2154	struct mlx5_ifc_mac_address_layout_bits {
2155	u8 reserved_at_0[0x10];
2156	u8 mac_addr_47_32[0x10];
2157
2158	u8 mac_addr_31_0[0x20];
2159	};
2160
2161	struct mlx5_ifc_vlan_layout_bits {
2162	u8 reserved_at_0[0x14];
2163	u8 vlan[0x0c];
2164
2165	u8 reserved_at_20[0x20];
2166	};
2167
2168	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2169	u8 reserved_at_0[0xa0];
2170
2171	u8 min_time_between_cnps[0x20];
2172
2173	u8 reserved_at_c0[0x12];
2174	u8 cnp_dscp[0x6];
2175	u8 reserved_at_d8[0x4];
2176	u8 cnp_prio_mode[0x1];
2177	u8 cnp_802p_prio[0x3];
2178
2179	u8 reserved_at_e0[0x720];
2180	};
2181
2182	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2183	u8 reserved_at_0[0x60];
2184
2185	u8 reserved_at_60[0x4];
2186	u8 clamp_tgt_rate[0x1];
2187	u8 reserved_at_65[0x3];
2188	u8 clamp_tgt_rate_after_time_inc[0x1];
2189	u8 reserved_at_69[0x17];
2190
2191	u8 reserved_at_80[0x20];
2192
2193	u8 rpg_time_reset[0x20];
2194
2195	u8 rpg_byte_reset[0x20];
2196
2197	u8 rpg_threshold[0x20];
2198
2199	u8 rpg_max_rate[0x20];
2200
2201	u8 rpg_ai_rate[0x20];
2202
2203	u8 rpg_hai_rate[0x20];
2204
2205	u8 rpg_gd[0x20];
2206
2207	u8 rpg_min_dec_fac[0x20];
2208
2209	u8 rpg_min_rate[0x20];
2210
2211	u8 reserved_at_1c0[0xe0];
2212
2213	u8 rate_to_set_on_first_cnp[0x20];
2214
2215	u8 dce_tcp_g[0x20];
2216
2217	u8 dce_tcp_rtt[0x20];
2218
2219	u8 rate_reduce_monitor_period[0x20];
2220
2221	u8 reserved_at_320[0x20];
2222
2223	u8 initial_alpha_value[0x20];
2224
2225	u8 reserved_at_360[0x4a0];
2226	};
2227
2228	struct mlx5_ifc_cong_control_r_roce_general_bits {
2229	u8 reserved_at_0[0x80];
2230
2231	u8 reserved_at_80[0x10];
2232	u8 rtt_resp_dscp_valid[0x1];
2233	u8 reserved_at_91[0x9];
2234	u8 rtt_resp_dscp[0x6];
2235
2236	u8 reserved_at_a0[0x760];
2237	};
2238
2239	struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2240	u8 reserved_at_0[0x80];
2241
2242	u8 rppp_max_rps[0x20];
2243
2244	u8 rpg_time_reset[0x20];
2245
2246	u8 rpg_byte_reset[0x20];
2247
2248	u8 rpg_threshold[0x20];
2249
2250	u8 rpg_max_rate[0x20];
2251
2252	u8 rpg_ai_rate[0x20];
2253
2254	u8 rpg_hai_rate[0x20];
2255
2256	u8 rpg_gd[0x20];
2257
2258	u8 rpg_min_dec_fac[0x20];
2259
2260	u8 rpg_min_rate[0x20];
2261
2262	u8 reserved_at_1c0[0x640];
2263	};
2264
2265	enum {
2266	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2267	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2268	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2269	};
2270
2271	struct mlx5_ifc_resize_field_select_bits {
2272	u8 resize_field_select[0x20];
2273	};
2274
2275	struct mlx5_ifc_resource_dump_bits {
2276	u8 more_dump[0x1];
2277	u8 inline_dump[0x1];
2278	u8 reserved_at_2[0xa];
2279	u8 seq_num[0x4];
2280	u8 segment_type[0x10];
2281
2282	u8 reserved_at_20[0x10];
2283	u8 vhca_id[0x10];
2284
2285	u8 index1[0x20];
2286
2287	u8 index2[0x20];
2288
2289	u8 num_of_obj1[0x10];
2290	u8 num_of_obj2[0x10];
2291
2292	u8 reserved_at_a0[0x20];
2293
2294	u8 device_opaque[0x40];
2295
2296	u8 mkey[0x20];
2297
2298	u8 size[0x20];
2299
2300	u8 address[0x40];
2301
2302	u8 inline_data[52][0x20];
2303	};
2304
2305	struct mlx5_ifc_resource_dump_menu_record_bits {
2306	u8 reserved_at_0[0x4];
2307	u8 num_of_obj2_supports_active[0x1];
2308	u8 num_of_obj2_supports_all[0x1];
2309	u8 must_have_num_of_obj2[0x1];
2310	u8 support_num_of_obj2[0x1];
2311	u8 num_of_obj1_supports_active[0x1];
2312	u8 num_of_obj1_supports_all[0x1];
2313	u8 must_have_num_of_obj1[0x1];
2314	u8 support_num_of_obj1[0x1];
2315	u8 must_have_index2[0x1];
2316	u8 support_index2[0x1];
2317	u8 must_have_index1[0x1];
2318	u8 support_index1[0x1];
2319	u8 segment_type[0x10];
2320
2321	u8 segment_name[4][0x20];
2322
2323	u8 index1_name[4][0x20];
2324
2325	u8 index2_name[4][0x20];
2326	};
2327
2328	struct mlx5_ifc_resource_dump_segment_header_bits {
2329	u8 length_dw[0x10];
2330	u8 segment_type[0x10];
2331	};
2332
2333	struct mlx5_ifc_resource_dump_command_segment_bits {
2334	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2335
2336	u8 segment_called[0x10];
2337	u8 vhca_id[0x10];
2338
2339	u8 index1[0x20];
2340
2341	u8 index2[0x20];
2342
2343	u8 num_of_obj1[0x10];
2344	u8 num_of_obj2[0x10];
2345	};
2346
2347	struct mlx5_ifc_resource_dump_error_segment_bits {
2348	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2349
2350	u8 reserved_at_20[0x10];
2351	u8 syndrome_id[0x10];
2352
2353	u8 reserved_at_40[0x40];
2354
2355	u8 error[8][0x20];
2356	};
2357
2358	struct mlx5_ifc_resource_dump_info_segment_bits {
2359	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2360
2361	u8 reserved_at_20[0x18];
2362	u8 dump_version[0x8];
2363
2364	u8 hw_version[0x20];
2365
2366	u8 fw_version[0x20];
2367	};
2368
2369	struct mlx5_ifc_resource_dump_menu_segment_bits {
2370	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2371
2372	u8 reserved_at_20[0x10];
2373	u8 num_of_records[0x10];
2374
2375	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2376	};
2377
2378	struct mlx5_ifc_resource_dump_resource_segment_bits {
2379	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2380
2381	u8 reserved_at_20[0x20];
2382
2383	u8 index1[0x20];
2384
2385	u8 index2[0x20];
2386
2387	u8 payload[][0x20];
2388	};
2389
2390	struct mlx5_ifc_resource_dump_terminate_segment_bits {
2391	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2392	};
2393
2394	struct mlx5_ifc_menu_resource_dump_response_bits {
2395	struct mlx5_ifc_resource_dump_info_segment_bits info;
2396	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2397	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2398	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2399	};
2400
2401	enum {
2402	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2403	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2404	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2405	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2406	};
2407
2408	struct mlx5_ifc_modify_field_select_bits {
2409	u8 modify_field_select[0x20];
2410	};
2411
2412	struct mlx5_ifc_field_select_r_roce_np_bits {
2413	u8 field_select_r_roce_np[0x20];
2414	};
2415
2416	struct mlx5_ifc_field_select_r_roce_rp_bits {
2417	u8 field_select_r_roce_rp[0x20];
2418	};
2419
2420	enum {
2421	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2422	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2423	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2424	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2425	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2426	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2427	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2428	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2429	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2430	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2431	};
2432
2433	struct mlx5_ifc_field_select_802_1qau_rp_bits {
2434	u8 field_select_8021qaurp[0x20];
2435	};
2436
2437	struct mlx5_ifc_phys_layer_cntrs_bits {
2438	u8 time_since_last_clear_high[0x20];
2439
2440	u8 time_since_last_clear_low[0x20];
2441
2442	u8 symbol_errors_high[0x20];
2443
2444	u8 symbol_errors_low[0x20];
2445
2446	u8 sync_headers_errors_high[0x20];
2447
2448	u8 sync_headers_errors_low[0x20];
2449
2450	u8 edpl_bip_errors_lane0_high[0x20];
2451
2452	u8 edpl_bip_errors_lane0_low[0x20];
2453
2454	u8 edpl_bip_errors_lane1_high[0x20];
2455
2456	u8 edpl_bip_errors_lane1_low[0x20];
2457
2458	u8 edpl_bip_errors_lane2_high[0x20];
2459
2460	u8 edpl_bip_errors_lane2_low[0x20];
2461
2462	u8 edpl_bip_errors_lane3_high[0x20];
2463
2464	u8 edpl_bip_errors_lane3_low[0x20];
2465
2466	u8 fc_fec_corrected_blocks_lane0_high[0x20];
2467
2468	u8 fc_fec_corrected_blocks_lane0_low[0x20];
2469
2470	u8 fc_fec_corrected_blocks_lane1_high[0x20];
2471
2472	u8 fc_fec_corrected_blocks_lane1_low[0x20];
2473
2474	u8 fc_fec_corrected_blocks_lane2_high[0x20];
2475
2476	u8 fc_fec_corrected_blocks_lane2_low[0x20];
2477
2478	u8 fc_fec_corrected_blocks_lane3_high[0x20];
2479
2480	u8 fc_fec_corrected_blocks_lane3_low[0x20];
2481
2482	u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2483
2484	u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2485
2486	u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2487
2488	u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2489
2490	u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2491
2492	u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2493
2494	u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2495
2496	u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2497
2498	u8 rs_fec_corrected_blocks_high[0x20];
2499
2500	u8 rs_fec_corrected_blocks_low[0x20];
2501
2502	u8 rs_fec_uncorrectable_blocks_high[0x20];
2503
2504	u8 rs_fec_uncorrectable_blocks_low[0x20];
2505
2506	u8 rs_fec_no_errors_blocks_high[0x20];
2507
2508	u8 rs_fec_no_errors_blocks_low[0x20];
2509
2510	u8 rs_fec_single_error_blocks_high[0x20];
2511
2512	u8 rs_fec_single_error_blocks_low[0x20];
2513
2514	u8 rs_fec_corrected_symbols_total_high[0x20];
2515
2516	u8 rs_fec_corrected_symbols_total_low[0x20];
2517
2518	u8 rs_fec_corrected_symbols_lane0_high[0x20];
2519
2520	u8 rs_fec_corrected_symbols_lane0_low[0x20];
2521
2522	u8 rs_fec_corrected_symbols_lane1_high[0x20];
2523
2524	u8 rs_fec_corrected_symbols_lane1_low[0x20];
2525
2526	u8 rs_fec_corrected_symbols_lane2_high[0x20];
2527
2528	u8 rs_fec_corrected_symbols_lane2_low[0x20];
2529
2530	u8 rs_fec_corrected_symbols_lane3_high[0x20];
2531
2532	u8 rs_fec_corrected_symbols_lane3_low[0x20];
2533
2534	u8 link_down_events[0x20];
2535
2536	u8 successful_recovery_events[0x20];
2537
2538	u8 reserved_at_640[0x180];
2539	};
2540
2541	struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2542	u8 time_since_last_clear_high[0x20];
2543
2544	u8 time_since_last_clear_low[0x20];
2545
2546	u8 phy_received_bits_high[0x20];
2547
2548	u8 phy_received_bits_low[0x20];
2549
2550	u8 phy_symbol_errors_high[0x20];
2551
2552	u8 phy_symbol_errors_low[0x20];
2553
2554	u8 phy_corrected_bits_high[0x20];
2555
2556	u8 phy_corrected_bits_low[0x20];
2557
2558	u8 phy_corrected_bits_lane0_high[0x20];
2559
2560	u8 phy_corrected_bits_lane0_low[0x20];
2561
2562	u8 phy_corrected_bits_lane1_high[0x20];
2563
2564	u8 phy_corrected_bits_lane1_low[0x20];
2565
2566	u8 phy_corrected_bits_lane2_high[0x20];
2567
2568	u8 phy_corrected_bits_lane2_low[0x20];
2569
2570	u8 phy_corrected_bits_lane3_high[0x20];
2571
2572	u8 phy_corrected_bits_lane3_low[0x20];
2573
2574	u8 reserved_at_200[0x5c0];
2575	};
2576
2577	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2578	u8 symbol_error_counter[0x10];
2579
2580	u8 link_error_recovery_counter[0x8];
2581
2582	u8 link_downed_counter[0x8];
2583
2584	u8 port_rcv_errors[0x10];
2585
2586	u8 port_rcv_remote_physical_errors[0x10];
2587
2588	u8 port_rcv_switch_relay_errors[0x10];
2589
2590	u8 port_xmit_discards[0x10];
2591
2592	u8 port_xmit_constraint_errors[0x8];
2593
2594	u8 port_rcv_constraint_errors[0x8];
2595
2596	u8 reserved_at_70[0x8];
2597
2598	u8 link_overrun_errors[0x8];
2599
2600	u8 reserved_at_80[0x10];
2601
2602	u8 vl_15_dropped[0x10];
2603
2604	u8 reserved_at_a0[0x80];
2605
2606	u8 port_xmit_wait[0x20];
2607	};
2608
2609	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2610	u8 transmit_queue_high[0x20];
2611
2612	u8 transmit_queue_low[0x20];
2613
2614	u8 no_buffer_discard_uc_high[0x20];
2615
2616	u8 no_buffer_discard_uc_low[0x20];
2617
2618	u8 reserved_at_80[0x740];
2619	};
2620
2621	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2622	u8 wred_discard_high[0x20];
2623
2624	u8 wred_discard_low[0x20];
2625
2626	u8 ecn_marked_tc_high[0x20];
2627
2628	u8 ecn_marked_tc_low[0x20];
2629
2630	u8 reserved_at_80[0x740];
2631	};
2632
2633	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2634	u8 rx_octets_high[0x20];
2635
2636	u8 rx_octets_low[0x20];
2637
2638	u8 reserved_at_40[0xc0];
2639
2640	u8 rx_frames_high[0x20];
2641
2642	u8 rx_frames_low[0x20];
2643
2644	u8 tx_octets_high[0x20];
2645
2646	u8 tx_octets_low[0x20];
2647
2648	u8 reserved_at_180[0xc0];
2649
2650	u8 tx_frames_high[0x20];
2651
2652	u8 tx_frames_low[0x20];
2653
2654	u8 rx_pause_high[0x20];
2655
2656	u8 rx_pause_low[0x20];
2657
2658	u8 rx_pause_duration_high[0x20];
2659
2660	u8 rx_pause_duration_low[0x20];
2661
2662	u8 tx_pause_high[0x20];
2663
2664	u8 tx_pause_low[0x20];
2665
2666	u8 tx_pause_duration_high[0x20];
2667
2668	u8 tx_pause_duration_low[0x20];
2669
2670	u8 rx_pause_transition_high[0x20];
2671
2672	u8 rx_pause_transition_low[0x20];
2673
2674	u8 rx_discards_high[0x20];
2675
2676	u8 rx_discards_low[0x20];
2677
2678	u8 device_stall_minor_watermark_cnt_high[0x20];
2679
2680	u8 device_stall_minor_watermark_cnt_low[0x20];
2681
2682	u8 device_stall_critical_watermark_cnt_high[0x20];
2683
2684	u8 device_stall_critical_watermark_cnt_low[0x20];
2685
2686	u8 reserved_at_480[0x340];
2687	};
2688
2689	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2690	u8 port_transmit_wait_high[0x20];
2691
2692	u8 port_transmit_wait_low[0x20];
2693
2694	u8 reserved_at_40[0x100];
2695
2696	u8 rx_buffer_almost_full_high[0x20];
2697
2698	u8 rx_buffer_almost_full_low[0x20];
2699
2700	u8 rx_buffer_full_high[0x20];
2701
2702	u8 rx_buffer_full_low[0x20];
2703
2704	u8 rx_icrc_encapsulated_high[0x20];
2705
2706	u8 rx_icrc_encapsulated_low[0x20];
2707
2708	u8 reserved_at_200[0x5c0];
2709	};
2710
2711	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2712	u8 dot3stats_alignment_errors_high[0x20];
2713
2714	u8 dot3stats_alignment_errors_low[0x20];
2715
2716	u8 dot3stats_fcs_errors_high[0x20];
2717
2718	u8 dot3stats_fcs_errors_low[0x20];
2719
2720	u8 dot3stats_single_collision_frames_high[0x20];
2721
2722	u8 dot3stats_single_collision_frames_low[0x20];
2723
2724	u8 dot3stats_multiple_collision_frames_high[0x20];
2725
2726	u8 dot3stats_multiple_collision_frames_low[0x20];
2727
2728	u8 dot3stats_sqe_test_errors_high[0x20];
2729
2730	u8 dot3stats_sqe_test_errors_low[0x20];
2731
2732	u8 dot3stats_deferred_transmissions_high[0x20];
2733
2734	u8 dot3stats_deferred_transmissions_low[0x20];
2735
2736	u8 dot3stats_late_collisions_high[0x20];
2737
2738	u8 dot3stats_late_collisions_low[0x20];
2739
2740	u8 dot3stats_excessive_collisions_high[0x20];
2741
2742	u8 dot3stats_excessive_collisions_low[0x20];
2743
2744	u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2745
2746	u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2747
2748	u8 dot3stats_carrier_sense_errors_high[0x20];
2749
2750	u8 dot3stats_carrier_sense_errors_low[0x20];
2751
2752	u8 dot3stats_frame_too_longs_high[0x20];
2753
2754	u8 dot3stats_frame_too_longs_low[0x20];
2755
2756	u8 dot3stats_internal_mac_receive_errors_high[0x20];
2757
2758	u8 dot3stats_internal_mac_receive_errors_low[0x20];
2759
2760	u8 dot3stats_symbol_errors_high[0x20];
2761
2762	u8 dot3stats_symbol_errors_low[0x20];
2763
2764	u8 dot3control_in_unknown_opcodes_high[0x20];
2765
2766	u8 dot3control_in_unknown_opcodes_low[0x20];
2767
2768	u8 dot3in_pause_frames_high[0x20];
2769
2770	u8 dot3in_pause_frames_low[0x20];
2771
2772	u8 dot3out_pause_frames_high[0x20];
2773
2774	u8 dot3out_pause_frames_low[0x20];
2775
2776	u8 reserved_at_400[0x3c0];
2777	};
2778
2779	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2780	u8 ether_stats_drop_events_high[0x20];
2781
2782	u8 ether_stats_drop_events_low[0x20];
2783
2784	u8 ether_stats_octets_high[0x20];
2785
2786	u8 ether_stats_octets_low[0x20];
2787
2788	u8 ether_stats_pkts_high[0x20];
2789
2790	u8 ether_stats_pkts_low[0x20];
2791
2792	u8 ether_stats_broadcast_pkts_high[0x20];
2793
2794	u8 ether_stats_broadcast_pkts_low[0x20];
2795
2796	u8 ether_stats_multicast_pkts_high[0x20];
2797
2798	u8 ether_stats_multicast_pkts_low[0x20];
2799
2800	u8 ether_stats_crc_align_errors_high[0x20];
2801
2802	u8 ether_stats_crc_align_errors_low[0x20];
2803
2804	u8 ether_stats_undersize_pkts_high[0x20];
2805
2806	u8 ether_stats_undersize_pkts_low[0x20];
2807
2808	u8 ether_stats_oversize_pkts_high[0x20];
2809
2810	u8 ether_stats_oversize_pkts_low[0x20];
2811
2812	u8 ether_stats_fragments_high[0x20];
2813
2814	u8 ether_stats_fragments_low[0x20];
2815
2816	u8 ether_stats_jabbers_high[0x20];
2817
2818	u8 ether_stats_jabbers_low[0x20];
2819
2820	u8 ether_stats_collisions_high[0x20];
2821
2822	u8 ether_stats_collisions_low[0x20];
2823
2824	u8 ether_stats_pkts64octets_high[0x20];
2825
2826	u8 ether_stats_pkts64octets_low[0x20];
2827
2828	u8 ether_stats_pkts65to127octets_high[0x20];
2829
2830	u8 ether_stats_pkts65to127octets_low[0x20];
2831
2832	u8 ether_stats_pkts128to255octets_high[0x20];
2833
2834	u8 ether_stats_pkts128to255octets_low[0x20];
2835
2836	u8 ether_stats_pkts256to511octets_high[0x20];
2837
2838	u8 ether_stats_pkts256to511octets_low[0x20];
2839
2840	u8 ether_stats_pkts512to1023octets_high[0x20];
2841
2842	u8 ether_stats_pkts512to1023octets_low[0x20];
2843
2844	u8 ether_stats_pkts1024to1518octets_high[0x20];
2845
2846	u8 ether_stats_pkts1024to1518octets_low[0x20];
2847
2848	u8 ether_stats_pkts1519to2047octets_high[0x20];
2849
2850	u8 ether_stats_pkts1519to2047octets_low[0x20];
2851
2852	u8 ether_stats_pkts2048to4095octets_high[0x20];
2853
2854	u8 ether_stats_pkts2048to4095octets_low[0x20];
2855
2856	u8 ether_stats_pkts4096to8191octets_high[0x20];
2857
2858	u8 ether_stats_pkts4096to8191octets_low[0x20];
2859
2860	u8 ether_stats_pkts8192to10239octets_high[0x20];
2861
2862	u8 ether_stats_pkts8192to10239octets_low[0x20];
2863
2864	u8 reserved_at_540[0x280];
2865	};
2866
2867	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2868	u8 if_in_octets_high[0x20];
2869
2870	u8 if_in_octets_low[0x20];
2871
2872	u8 if_in_ucast_pkts_high[0x20];
2873
2874	u8 if_in_ucast_pkts_low[0x20];
2875
2876	u8 if_in_discards_high[0x20];
2877
2878	u8 if_in_discards_low[0x20];
2879
2880	u8 if_in_errors_high[0x20];
2881
2882	u8 if_in_errors_low[0x20];
2883
2884	u8 if_in_unknown_protos_high[0x20];
2885
2886	u8 if_in_unknown_protos_low[0x20];
2887
2888	u8 if_out_octets_high[0x20];
2889
2890	u8 if_out_octets_low[0x20];
2891
2892	u8 if_out_ucast_pkts_high[0x20];
2893
2894	u8 if_out_ucast_pkts_low[0x20];
2895
2896	u8 if_out_discards_high[0x20];
2897
2898	u8 if_out_discards_low[0x20];
2899
2900	u8 if_out_errors_high[0x20];
2901
2902	u8 if_out_errors_low[0x20];
2903
2904	u8 if_in_multicast_pkts_high[0x20];
2905
2906	u8 if_in_multicast_pkts_low[0x20];
2907
2908	u8 if_in_broadcast_pkts_high[0x20];
2909
2910	u8 if_in_broadcast_pkts_low[0x20];
2911
2912	u8 if_out_multicast_pkts_high[0x20];
2913
2914	u8 if_out_multicast_pkts_low[0x20];
2915
2916	u8 if_out_broadcast_pkts_high[0x20];
2917
2918	u8 if_out_broadcast_pkts_low[0x20];
2919
2920	u8 reserved_at_340[0x480];
2921	};
2922
2923	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2924	u8 a_frames_transmitted_ok_high[0x20];
2925
2926	u8 a_frames_transmitted_ok_low[0x20];
2927
2928	u8 a_frames_received_ok_high[0x20];
2929
2930	u8 a_frames_received_ok_low[0x20];
2931
2932	u8 a_frame_check_sequence_errors_high[0x20];
2933
2934	u8 a_frame_check_sequence_errors_low[0x20];
2935
2936	u8 a_alignment_errors_high[0x20];
2937
2938	u8 a_alignment_errors_low[0x20];
2939
2940	u8 a_octets_transmitted_ok_high[0x20];
2941
2942	u8 a_octets_transmitted_ok_low[0x20];
2943
2944	u8 a_octets_received_ok_high[0x20];
2945
2946	u8 a_octets_received_ok_low[0x20];
2947
2948	u8 a_multicast_frames_xmitted_ok_high[0x20];
2949
2950	u8 a_multicast_frames_xmitted_ok_low[0x20];
2951
2952	u8 a_broadcast_frames_xmitted_ok_high[0x20];
2953
2954	u8 a_broadcast_frames_xmitted_ok_low[0x20];
2955
2956	u8 a_multicast_frames_received_ok_high[0x20];
2957
2958	u8 a_multicast_frames_received_ok_low[0x20];
2959
2960	u8 a_broadcast_frames_received_ok_high[0x20];
2961
2962	u8 a_broadcast_frames_received_ok_low[0x20];
2963
2964	u8 a_in_range_length_errors_high[0x20];
2965
2966	u8 a_in_range_length_errors_low[0x20];
2967
2968	u8 a_out_of_range_length_field_high[0x20];
2969
2970	u8 a_out_of_range_length_field_low[0x20];
2971
2972	u8 a_frame_too_long_errors_high[0x20];
2973
2974	u8 a_frame_too_long_errors_low[0x20];
2975
2976	u8 a_symbol_error_during_carrier_high[0x20];
2977
2978	u8 a_symbol_error_during_carrier_low[0x20];
2979
2980	u8 a_mac_control_frames_transmitted_high[0x20];
2981
2982	u8 a_mac_control_frames_transmitted_low[0x20];
2983
2984	u8 a_mac_control_frames_received_high[0x20];
2985
2986	u8 a_mac_control_frames_received_low[0x20];
2987
2988	u8 a_unsupported_opcodes_received_high[0x20];
2989
2990	u8 a_unsupported_opcodes_received_low[0x20];
2991
2992	u8 a_pause_mac_ctrl_frames_received_high[0x20];
2993
2994	u8 a_pause_mac_ctrl_frames_received_low[0x20];
2995
2996	u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2997
2998	u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2999
3000	u8 reserved_at_4c0[0x300];
3001	};
3002
3003	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3004	u8 life_time_counter_high[0x20];
3005
3006	u8 life_time_counter_low[0x20];
3007
3008	u8 rx_errors[0x20];
3009
3010	u8 tx_errors[0x20];
3011
3012	u8 l0_to_recovery_eieos[0x20];
3013
3014	u8 l0_to_recovery_ts[0x20];
3015
3016	u8 l0_to_recovery_framing[0x20];
3017
3018	u8 l0_to_recovery_retrain[0x20];
3019
3020	u8 crc_error_dllp[0x20];
3021
3022	u8 crc_error_tlp[0x20];
3023
3024	u8 tx_overflow_buffer_pkt_high[0x20];
3025
3026	u8 tx_overflow_buffer_pkt_low[0x20];
3027
3028	u8 outbound_stalled_reads[0x20];
3029
3030	u8 outbound_stalled_writes[0x20];
3031
3032	u8 outbound_stalled_reads_events[0x20];
3033
3034	u8 outbound_stalled_writes_events[0x20];
3035
3036	u8 reserved_at_200[0x5c0];
3037	};
3038
3039	struct mlx5_ifc_cmd_inter_comp_event_bits {
3040	u8 command_completion_vector[0x20];
3041
3042	u8 reserved_at_20[0xc0];
3043	};
3044
3045	struct mlx5_ifc_stall_vl_event_bits {
3046	u8 reserved_at_0[0x18];
3047	u8 port_num[0x1];
3048	u8 reserved_at_19[0x3];
3049	u8 vl[0x4];
3050
3051	u8 reserved_at_20[0xa0];
3052	};
3053
3054	struct mlx5_ifc_db_bf_congestion_event_bits {
3055	u8 event_subtype[0x8];
3056	u8 reserved_at_8[0x8];
3057	u8 congestion_level[0x8];
3058	u8 reserved_at_18[0x8];
3059
3060	u8 reserved_at_20[0xa0];
3061	};
3062
3063	struct mlx5_ifc_gpio_event_bits {
3064	u8 reserved_at_0[0x60];
3065
3066	u8 gpio_event_hi[0x20];
3067
3068	u8 gpio_event_lo[0x20];
3069
3070	u8 reserved_at_a0[0x40];
3071	};
3072
3073	struct mlx5_ifc_port_state_change_event_bits {
3074	u8 reserved_at_0[0x40];
3075
3076	u8 port_num[0x4];
3077	u8 reserved_at_44[0x1c];
3078
3079	u8 reserved_at_60[0x80];
3080	};
3081
3082	struct mlx5_ifc_dropped_packet_logged_bits {
3083	u8 reserved_at_0[0xe0];
3084	};
3085
3086	struct mlx5_ifc_default_timeout_bits {
3087	u8 to_multiplier[0x3];
3088	u8 reserved_at_3[0x9];
3089	u8 to_value[0x14];
3090	};
3091
3092	struct mlx5_ifc_dtor_reg_bits {
3093	u8 reserved_at_0[0x20];
3094
3095	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3096
3097	u8 reserved_at_40[0x60];
3098
3099	struct mlx5_ifc_default_timeout_bits health_poll_to;
3100
3101	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3102
3103	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3104
3105	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3106
3107	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3108
3109	struct mlx5_ifc_default_timeout_bits tear_down_to;
3110
3111	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3112
3113	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3114
3115	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3116
3117	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3118
3119	u8 reserved_at_1c0[0x20];
3120	};
3121
3122	enum {
3123	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3124	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3125	};
3126
3127	struct mlx5_ifc_cq_error_bits {
3128	u8 reserved_at_0[0x8];
3129	u8 cqn[0x18];
3130
3131	u8 reserved_at_20[0x20];
3132
3133	u8 reserved_at_40[0x18];
3134	u8 syndrome[0x8];
3135
3136	u8 reserved_at_60[0x80];
3137	};
3138
3139	struct mlx5_ifc_rdma_page_fault_event_bits {
3140	u8 bytes_committed[0x20];
3141
3142	u8 r_key[0x20];
3143
3144	u8 reserved_at_40[0x10];
3145	u8 packet_len[0x10];
3146
3147	u8 rdma_op_len[0x20];
3148
3149	u8 rdma_va[0x40];
3150
3151	u8 reserved_at_c0[0x5];
3152	u8 rdma[0x1];
3153	u8 write[0x1];
3154	u8 requestor[0x1];
3155	u8 qp_number[0x18];
3156	};
3157
3158	struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3159	u8 bytes_committed[0x20];
3160
3161	u8 reserved_at_20[0x10];
3162	u8 wqe_index[0x10];
3163
3164	u8 reserved_at_40[0x10];
3165	u8 len[0x10];
3166
3167	u8 reserved_at_60[0x60];
3168
3169	u8 reserved_at_c0[0x5];
3170	u8 rdma[0x1];
3171	u8 write_read[0x1];
3172	u8 requestor[0x1];
3173	u8 qpn[0x18];
3174	};
3175
3176	struct mlx5_ifc_qp_events_bits {
3177	u8 reserved_at_0[0xa0];
3178
3179	u8 type[0x8];
3180	u8 reserved_at_a8[0x18];
3181
3182	u8 reserved_at_c0[0x8];
3183	u8 qpn_rqn_sqn[0x18];
3184	};
3185
3186	struct mlx5_ifc_dct_events_bits {
3187	u8 reserved_at_0[0xc0];
3188
3189	u8 reserved_at_c0[0x8];
3190	u8 dct_number[0x18];
3191	};
3192
3193	struct mlx5_ifc_comp_event_bits {
3194	u8 reserved_at_0[0xc0];
3195
3196	u8 reserved_at_c0[0x8];
3197	u8 cq_number[0x18];
3198	};
3199
3200	enum {
3201	MLX5_QPC_STATE_RST = 0x0,
3202	MLX5_QPC_STATE_INIT = 0x1,
3203	MLX5_QPC_STATE_RTR = 0x2,
3204	MLX5_QPC_STATE_RTS = 0x3,
3205	MLX5_QPC_STATE_SQER = 0x4,
3206	MLX5_QPC_STATE_ERR = 0x6,
3207	MLX5_QPC_STATE_SQD = 0x7,
3208	MLX5_QPC_STATE_SUSPENDED = 0x9,
3209	};
3210
3211	enum {
3212	MLX5_QPC_ST_RC = 0x0,
3213	MLX5_QPC_ST_UC = 0x1,
3214	MLX5_QPC_ST_UD = 0x2,
3215	MLX5_QPC_ST_XRC = 0x3,
3216	MLX5_QPC_ST_DCI = 0x5,
3217	MLX5_QPC_ST_QP0 = 0x7,
3218	MLX5_QPC_ST_QP1 = 0x8,
3219	MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3220	MLX5_QPC_ST_REG_UMR = 0xc,
3221	};
3222
3223	enum {
3224	MLX5_QPC_PM_STATE_ARMED = 0x0,
3225	MLX5_QPC_PM_STATE_REARM = 0x1,
3226	MLX5_QPC_PM_STATE_RESERVED = 0x2,
3227	MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3228	};
3229
3230	enum {
3231	MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3232	};
3233
3234	enum {
3235	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3236	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3237	};
3238
3239	enum {
3240	MLX5_QPC_MTU_256_BYTES = 0x1,
3241	MLX5_QPC_MTU_512_BYTES = 0x2,
3242	MLX5_QPC_MTU_1K_BYTES = 0x3,
3243	MLX5_QPC_MTU_2K_BYTES = 0x4,
3244	MLX5_QPC_MTU_4K_BYTES = 0x5,
3245	MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3246	};
3247
3248	enum {
3249	MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3250	MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3251	MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3252	MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3253	MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3254	MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3255	MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3256	MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3257	};
3258
3259	enum {
3260	MLX5_QPC_CS_REQ_DISABLE = 0x0,
3261	MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3262	MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3263	};
3264
3265	enum {
3266	MLX5_QPC_CS_RES_DISABLE = 0x0,
3267	MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3268	MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3269	};
3270
3271	enum {
3272	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3273	MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3274	MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3275	};
3276
3277	struct mlx5_ifc_qpc_bits {
3278	u8 state[0x4];
3279	u8 lag_tx_port_affinity[0x4];
3280	u8 st[0x8];
3281	u8 reserved_at_10[0x2];
3282	u8 isolate_vl_tc[0x1];
3283	u8 pm_state[0x2];
3284	u8 reserved_at_15[0x1];
3285	u8 req_e2e_credit_mode[0x2];
3286	u8 offload_type[0x4];
3287	u8 end_padding_mode[0x2];
3288	u8 reserved_at_1e[0x2];
3289
3290	u8 wq_signature[0x1];
3291	u8 block_lb_mc[0x1];
3292	u8 atomic_like_write_en[0x1];
3293	u8 latency_sensitive[0x1];
3294	u8 reserved_at_24[0x1];
3295	u8 drain_sigerr[0x1];
3296	u8 reserved_at_26[0x2];
3297	u8 pd[0x18];
3298
3299	u8 mtu[0x3];
3300	u8 log_msg_max[0x5];
3301	u8 reserved_at_48[0x1];
3302	u8 log_rq_size[0x4];
3303	u8 log_rq_stride[0x3];
3304	u8 no_sq[0x1];
3305	u8 log_sq_size[0x4];
3306	u8 reserved_at_55[0x1];
3307	u8 retry_mode[0x2];
3308	u8 ts_format[0x2];
3309	u8 reserved_at_5a[0x1];
3310	u8 rlky[0x1];
3311	u8 ulp_stateless_offload_mode[0x4];
3312
3313	u8 counter_set_id[0x8];
3314	u8 uar_page[0x18];
3315
3316	u8 reserved_at_80[0x8];
3317	u8 user_index[0x18];
3318
3319	u8 reserved_at_a0[0x3];
3320	u8 log_page_size[0x5];
3321	u8 remote_qpn[0x18];
3322
3323	struct mlx5_ifc_ads_bits primary_address_path;
3324
3325	struct mlx5_ifc_ads_bits secondary_address_path;
3326
3327	u8 log_ack_req_freq[0x4];
3328	u8 reserved_at_384[0x4];
3329	u8 log_sra_max[0x3];
3330	u8 reserved_at_38b[0x2];
3331	u8 retry_count[0x3];
3332	u8 rnr_retry[0x3];
3333	u8 reserved_at_393[0x1];
3334	u8 fre[0x1];
3335	u8 cur_rnr_retry[0x3];
3336	u8 cur_retry_count[0x3];
3337	u8 reserved_at_39b[0x5];
3338
3339	u8 reserved_at_3a0[0x20];
3340
3341	u8 reserved_at_3c0[0x8];
3342	u8 next_send_psn[0x18];
3343
3344	u8 reserved_at_3e0[0x3];
3345	u8 log_num_dci_stream_channels[0x5];
3346	u8 cqn_snd[0x18];
3347
3348	u8 reserved_at_400[0x3];
3349	u8 log_num_dci_errored_streams[0x5];
3350	u8 deth_sqpn[0x18];
3351
3352	u8 reserved_at_420[0x20];
3353
3354	u8 reserved_at_440[0x8];
3355	u8 last_acked_psn[0x18];
3356
3357	u8 reserved_at_460[0x8];
3358	u8 ssn[0x18];
3359
3360	u8 reserved_at_480[0x8];
3361	u8 log_rra_max[0x3];
3362	u8 reserved_at_48b[0x1];
3363	u8 atomic_mode[0x4];
3364	u8 rre[0x1];
3365	u8 rwe[0x1];
3366	u8 rae[0x1];
3367	u8 reserved_at_493[0x1];
3368	u8 page_offset[0x6];
3369	u8 reserved_at_49a[0x3];
3370	u8 cd_slave_receive[0x1];
3371	u8 cd_slave_send[0x1];
3372	u8 cd_master[0x1];
3373
3374	u8 reserved_at_4a0[0x3];
3375	u8 min_rnr_nak[0x5];
3376	u8 next_rcv_psn[0x18];
3377
3378	u8 reserved_at_4c0[0x8];
3379	u8 xrcd[0x18];
3380
3381	u8 reserved_at_4e0[0x8];
3382	u8 cqn_rcv[0x18];
3383
3384	u8 dbr_addr[0x40];
3385
3386	u8 q_key[0x20];
3387
3388	u8 reserved_at_560[0x5];
3389	u8 rq_type[0x3];
3390	u8 srqn_rmpn_xrqn[0x18];
3391
3392	u8 reserved_at_580[0x8];
3393	u8 rmsn[0x18];
3394
3395	u8 hw_sq_wqebb_counter[0x10];
3396	u8 sw_sq_wqebb_counter[0x10];
3397
3398	u8 hw_rq_counter[0x20];
3399
3400	u8 sw_rq_counter[0x20];
3401
3402	u8 reserved_at_600[0x20];
3403
3404	u8 reserved_at_620[0xf];
3405	u8 cgs[0x1];
3406	u8 cs_req[0x8];
3407	u8 cs_res[0x8];
3408
3409	u8 dc_access_key[0x40];
3410
3411	u8 reserved_at_680[0x3];
3412	u8 dbr_umem_valid[0x1];
3413
3414	u8 reserved_at_684[0xbc];
3415	};
3416
3417	struct mlx5_ifc_roce_addr_layout_bits {
3418	u8 source_l3_address[16][0x8];
3419
3420	u8 reserved_at_80[0x3];
3421	u8 vlan_valid[0x1];
3422	u8 vlan_id[0xc];
3423	u8 source_mac_47_32[0x10];
3424
3425	u8 source_mac_31_0[0x20];
3426
3427	u8 reserved_at_c0[0x14];
3428	u8 roce_l3_type[0x4];
3429	u8 roce_version[0x8];
3430
3431	u8 reserved_at_e0[0x20];
3432	};
3433
3434	struct mlx5_ifc_crypto_cap_bits {
3435	u8 reserved_at_0[0x3];
3436	u8 synchronize_dek[0x1];
3437	u8 int_kek_manual[0x1];
3438	u8 int_kek_auto[0x1];
3439	u8 reserved_at_6[0x1a];
3440
3441	u8 reserved_at_20[0x3];
3442	u8 log_dek_max_alloc[0x5];
3443	u8 reserved_at_28[0x3];
3444	u8 log_max_num_deks[0x5];
3445	u8 reserved_at_30[0x10];
3446
3447	u8 reserved_at_40[0x20];
3448
3449	u8 reserved_at_60[0x3];
3450	u8 log_dek_granularity[0x5];
3451	u8 reserved_at_68[0x3];
3452	u8 log_max_num_int_kek[0x5];
3453	u8 sw_wrapped_dek[0x10];
3454
3455	u8 reserved_at_80[0x780];
3456	};
3457
3458	union mlx5_ifc_hca_cap_union_bits {
3459	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3460	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3461	struct mlx5_ifc_odp_cap_bits odp_cap;
3462	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3463	struct mlx5_ifc_roce_cap_bits roce_cap;
3464	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3465	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3466	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3467	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3468	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3469	struct mlx5_ifc_qos_cap_bits qos_cap;
3470	struct mlx5_ifc_debug_cap_bits debug_cap;
3471	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3472	struct mlx5_ifc_tls_cap_bits tls_cap;
3473	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3474	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3475	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3476	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3477	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3478	u8 reserved_at_0[0x8000];
3479	};
3480
3481	enum {
3482	MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3483	MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3484	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3485	MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3486	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3487	MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3488	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3489	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3490	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3491	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3492	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3493	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3494	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3495	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3496	};
3497
3498	enum {
3499	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3500	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3501	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3502	};
3503
3504	enum {
3505	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
3506	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
3507	};
3508
3509	struct mlx5_ifc_vlan_bits {
3510	u8 ethtype[0x10];
3511	u8 prio[0x3];
3512	u8 cfi[0x1];
3513	u8 vid[0xc];
3514	};
3515
3516	enum {
3517	MLX5_FLOW_METER_COLOR_RED = 0x0,
3518	MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3519	MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3520	MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3521	};
3522
3523	enum {
3524	MLX5_EXE_ASO_FLOW_METER = 0x2,
3525	};
3526
3527	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3528	u8 return_reg_id[0x4];
3529	u8 aso_type[0x4];
3530	u8 reserved_at_8[0x14];
3531	u8 action[0x1];
3532	u8 init_color[0x2];
3533	u8 meter_id[0x1];
3534	};
3535
3536	union mlx5_ifc_exe_aso_ctrl {
3537	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3538	};
3539
3540	struct mlx5_ifc_execute_aso_bits {
3541	u8 valid[0x1];
3542	u8 reserved_at_1[0x7];
3543	u8 aso_object_id[0x18];
3544
3545	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3546	};
3547
3548	struct mlx5_ifc_flow_context_bits {
3549	struct mlx5_ifc_vlan_bits push_vlan;
3550
3551	u8 group_id[0x20];
3552
3553	u8 reserved_at_40[0x8];
3554	u8 flow_tag[0x18];
3555
3556	u8 reserved_at_60[0x10];
3557	u8 action[0x10];
3558
3559	u8 extended_destination[0x1];
3560	u8 reserved_at_81[0x1];
3561	u8 flow_source[0x2];
3562	u8 encrypt_decrypt_type[0x4];
3563	u8 destination_list_size[0x18];
3564
3565	u8 reserved_at_a0[0x8];
3566	u8 flow_counter_list_size[0x18];
3567
3568	u8 packet_reformat_id[0x20];
3569
3570	u8 modify_header_id[0x20];
3571
3572	struct mlx5_ifc_vlan_bits push_vlan_2;
3573
3574	u8 encrypt_decrypt_obj_id[0x20];
3575	u8 reserved_at_140[0xc0];
3576
3577	struct mlx5_ifc_fte_match_param_bits match_value;
3578
3579	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3580
3581	u8 reserved_at_1300[0x500];
3582
3583	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3584	};
3585
3586	enum {
3587	MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3588	MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3589	};
3590
3591	struct mlx5_ifc_xrc_srqc_bits {
3592	u8 state[0x4];
3593	u8 log_xrc_srq_size[0x4];
3594	u8 reserved_at_8[0x18];
3595
3596	u8 wq_signature[0x1];
3597	u8 cont_srq[0x1];
3598	u8 reserved_at_22[0x1];
3599	u8 rlky[0x1];
3600	u8 basic_cyclic_rcv_wqe[0x1];
3601	u8 log_rq_stride[0x3];
3602	u8 xrcd[0x18];
3603
3604	u8 page_offset[0x6];
3605	u8 reserved_at_46[0x1];
3606	u8 dbr_umem_valid[0x1];
3607	u8 cqn[0x18];
3608
3609	u8 reserved_at_60[0x20];
3610
3611	u8 user_index_equal_xrc_srqn[0x1];
3612	u8 reserved_at_81[0x1];
3613	u8 log_page_size[0x6];
3614	u8 user_index[0x18];
3615
3616	u8 reserved_at_a0[0x20];
3617
3618	u8 reserved_at_c0[0x8];
3619	u8 pd[0x18];
3620
3621	u8 lwm[0x10];
3622	u8 wqe_cnt[0x10];
3623
3624	u8 reserved_at_100[0x40];
3625
3626	u8 db_record_addr_h[0x20];
3627
3628	u8 db_record_addr_l[0x1e];
3629	u8 reserved_at_17e[0x2];
3630
3631	u8 reserved_at_180[0x80];
3632	};
3633
3634	struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3635	u8 counter_error_queues[0x20];
3636
3637	u8 total_error_queues[0x20];
3638
3639	u8 send_queue_priority_update_flow[0x20];
3640
3641	u8 reserved_at_60[0x20];
3642
3643	u8 nic_receive_steering_discard[0x40];
3644
3645	u8 receive_discard_vport_down[0x40];
3646
3647	u8 transmit_discard_vport_down[0x40];
3648
3649	u8 async_eq_overrun[0x20];
3650
3651	u8 comp_eq_overrun[0x20];
3652
3653	u8 reserved_at_180[0x20];
3654
3655	u8 invalid_command[0x20];
3656
3657	u8 quota_exceeded_command[0x20];
3658
3659	u8 internal_rq_out_of_buffer[0x20];
3660
3661	u8 cq_overrun[0x20];
3662
3663	u8 eth_wqe_too_small[0x20];
3664
3665	u8 reserved_at_220[0xc0];
3666
3667	u8 generated_pkt_steering_fail[0x40];
3668
3669	u8 handled_pkt_steering_fail[0x40];
3670
3671	u8 reserved_at_360[0xc80];
3672	};
3673
3674	struct mlx5_ifc_traffic_counter_bits {
3675	u8 packets[0x40];
3676
3677	u8 octets[0x40];
3678	};
3679
3680	struct mlx5_ifc_tisc_bits {
3681	u8 strict_lag_tx_port_affinity[0x1];
3682	u8 tls_en[0x1];
3683	u8 reserved_at_2[0x2];
3684	u8 lag_tx_port_affinity[0x04];
3685
3686	u8 reserved_at_8[0x4];
3687	u8 prio[0x4];
3688	u8 reserved_at_10[0x10];
3689
3690	u8 reserved_at_20[0x100];
3691
3692	u8 reserved_at_120[0x8];
3693	u8 transport_domain[0x18];
3694
3695	u8 reserved_at_140[0x8];
3696	u8 underlay_qpn[0x18];
3697
3698	u8 reserved_at_160[0x8];
3699	u8 pd[0x18];
3700
3701	u8 reserved_at_180[0x380];
3702	};
3703
3704	enum {
3705	MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3706	MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3707	};
3708
3709	enum {
3710	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3711	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
3712	};
3713
3714	enum {
3715	MLX5_RX_HASH_FN_NONE = 0x0,
3716	MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3717	MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3718	};
3719
3720	enum {
3721	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3722	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3723	};
3724
3725	struct mlx5_ifc_tirc_bits {
3726	u8 reserved_at_0[0x20];
3727
3728	u8 disp_type[0x4];
3729	u8 tls_en[0x1];
3730	u8 reserved_at_25[0x1b];
3731
3732	u8 reserved_at_40[0x40];
3733
3734	u8 reserved_at_80[0x4];
3735	u8 lro_timeout_period_usecs[0x10];
3736	u8 packet_merge_mask[0x4];
3737	u8 lro_max_ip_payload_size[0x8];
3738
3739	u8 reserved_at_a0[0x40];
3740
3741	u8 reserved_at_e0[0x8];
3742	u8 inline_rqn[0x18];
3743
3744	u8 rx_hash_symmetric[0x1];
3745	u8 reserved_at_101[0x1];
3746	u8 tunneled_offload_en[0x1];
3747	u8 reserved_at_103[0x5];
3748	u8 indirect_table[0x18];
3749
3750	u8 rx_hash_fn[0x4];
3751	u8 reserved_at_124[0x2];
3752	u8 self_lb_block[0x2];
3753	u8 transport_domain[0x18];
3754
3755	u8 rx_hash_toeplitz_key[10][0x20];
3756
3757	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3758
3759	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3760
3761	u8 reserved_at_2c0[0x4c0];
3762	};
3763
3764	enum {
3765	MLX5_SRQC_STATE_GOOD = 0x0,
3766	MLX5_SRQC_STATE_ERROR = 0x1,
3767	};
3768
3769	struct mlx5_ifc_srqc_bits {
3770	u8 state[0x4];
3771	u8 log_srq_size[0x4];
3772	u8 reserved_at_8[0x18];
3773
3774	u8 wq_signature[0x1];
3775	u8 cont_srq[0x1];
3776	u8 reserved_at_22[0x1];
3777	u8 rlky[0x1];
3778	u8 reserved_at_24[0x1];
3779	u8 log_rq_stride[0x3];
3780	u8 xrcd[0x18];
3781
3782	u8 page_offset[0x6];
3783	u8 reserved_at_46[0x2];
3784	u8 cqn[0x18];
3785
3786	u8 reserved_at_60[0x20];
3787
3788	u8 reserved_at_80[0x2];
3789	u8 log_page_size[0x6];
3790	u8 reserved_at_88[0x18];
3791
3792	u8 reserved_at_a0[0x20];
3793
3794	u8 reserved_at_c0[0x8];
3795	u8 pd[0x18];
3796
3797	u8 lwm[0x10];
3798	u8 wqe_cnt[0x10];
3799
3800	u8 reserved_at_100[0x40];
3801
3802	u8 dbr_addr[0x40];
3803
3804	u8 reserved_at_180[0x80];
3805	};
3806
3807	enum {
3808	MLX5_SQC_STATE_RST = 0x0,
3809	MLX5_SQC_STATE_RDY = 0x1,
3810	MLX5_SQC_STATE_ERR = 0x3,
3811	};
3812
3813	struct mlx5_ifc_sqc_bits {
3814	u8 rlky[0x1];
3815	u8 cd_master[0x1];
3816	u8 fre[0x1];
3817	u8 flush_in_error_en[0x1];
3818	u8 allow_multi_pkt_send_wqe[0x1];
3819	u8 min_wqe_inline_mode[0x3];
3820	u8 state[0x4];
3821	u8 reg_umr[0x1];
3822	u8 allow_swp[0x1];
3823	u8 hairpin[0x1];
3824	u8 reserved_at_f[0xb];
3825	u8 ts_format[0x2];
3826	u8 reserved_at_1c[0x4];
3827
3828	u8 reserved_at_20[0x8];
3829	u8 user_index[0x18];
3830
3831	u8 reserved_at_40[0x8];
3832	u8 cqn[0x18];
3833
3834	u8 reserved_at_60[0x8];
3835	u8 hairpin_peer_rq[0x18];
3836
3837	u8 reserved_at_80[0x10];
3838	u8 hairpin_peer_vhca[0x10];
3839
3840	u8 reserved_at_a0[0x20];
3841
3842	u8 reserved_at_c0[0x8];
3843	u8 ts_cqe_to_dest_cqn[0x18];
3844
3845	u8 reserved_at_e0[0x10];
3846	u8 packet_pacing_rate_limit_index[0x10];
3847	u8 tis_lst_sz[0x10];
3848	u8 qos_queue_group_id[0x10];
3849
3850	u8 reserved_at_120[0x40];
3851
3852	u8 reserved_at_160[0x8];
3853	u8 tis_num_0[0x18];
3854
3855	struct mlx5_ifc_wq_bits wq;
3856	};
3857
3858	enum {
3859	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3860	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3861	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3862	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3863	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3864	};
3865
3866	enum {
3867	ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3868	ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3869	ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3870	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3871	};
3872
3873	struct mlx5_ifc_scheduling_context_bits {
3874	u8 element_type[0x8];
3875	u8 reserved_at_8[0x18];
3876
3877	u8 element_attributes[0x20];
3878
3879	u8 parent_element_id[0x20];
3880
3881	u8 reserved_at_60[0x40];
3882
3883	u8 bw_share[0x20];
3884
3885	u8 max_average_bw[0x20];
3886
3887	u8 reserved_at_e0[0x120];
3888	};
3889
3890	struct mlx5_ifc_rqtc_bits {
3891	u8 reserved_at_0[0xa0];
3892
3893	u8 reserved_at_a0[0x5];
3894	u8 list_q_type[0x3];
3895	u8 reserved_at_a8[0x8];
3896	u8 rqt_max_size[0x10];
3897
3898	u8 rq_vhca_id_format[0x1];
3899	u8 reserved_at_c1[0xf];
3900	u8 rqt_actual_size[0x10];
3901
3902	u8 reserved_at_e0[0x6a0];
3903
3904	struct mlx5_ifc_rq_num_bits rq_num[];
3905	};
3906
3907	enum {
3908	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3909	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3910	};
3911
3912	enum {
3913	MLX5_RQC_STATE_RST = 0x0,
3914	MLX5_RQC_STATE_RDY = 0x1,
3915	MLX5_RQC_STATE_ERR = 0x3,
3916	};
3917
3918	enum {
3919	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3920	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3921	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3922	};
3923
3924	enum {
3925	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3926	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3927	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3928	};
3929
3930	struct mlx5_ifc_rqc_bits {
3931	u8 rlky[0x1];
3932	u8 delay_drop_en[0x1];
3933	u8 scatter_fcs[0x1];
3934	u8 vsd[0x1];
3935	u8 mem_rq_type[0x4];
3936	u8 state[0x4];
3937	u8 reserved_at_c[0x1];
3938	u8 flush_in_error_en[0x1];
3939	u8 hairpin[0x1];
3940	u8 reserved_at_f[0xb];
3941	u8 ts_format[0x2];
3942	u8 reserved_at_1c[0x4];
3943
3944	u8 reserved_at_20[0x8];
3945	u8 user_index[0x18];
3946
3947	u8 reserved_at_40[0x8];
3948	u8 cqn[0x18];
3949
3950	u8 counter_set_id[0x8];
3951	u8 reserved_at_68[0x18];
3952
3953	u8 reserved_at_80[0x8];
3954	u8 rmpn[0x18];
3955
3956	u8 reserved_at_a0[0x8];
3957	u8 hairpin_peer_sq[0x18];
3958
3959	u8 reserved_at_c0[0x10];
3960	u8 hairpin_peer_vhca[0x10];
3961
3962	u8 reserved_at_e0[0x46];
3963	u8 shampo_no_match_alignment_granularity[0x2];
3964	u8 reserved_at_128[0x6];
3965	u8 shampo_match_criteria_type[0x2];
3966	u8 reservation_timeout[0x10];
3967
3968	u8 reserved_at_140[0x40];
3969
3970	struct mlx5_ifc_wq_bits wq;
3971	};
3972
3973	enum {
3974	MLX5_RMPC_STATE_RDY = 0x1,
3975	MLX5_RMPC_STATE_ERR = 0x3,
3976	};
3977
3978	struct mlx5_ifc_rmpc_bits {
3979	u8 reserved_at_0[0x8];
3980	u8 state[0x4];
3981	u8 reserved_at_c[0x14];
3982
3983	u8 basic_cyclic_rcv_wqe[0x1];
3984	u8 reserved_at_21[0x1f];
3985
3986	u8 reserved_at_40[0x140];
3987
3988	struct mlx5_ifc_wq_bits wq;
3989	};
3990
3991	enum {
3992	VHCA_ID_TYPE_HW = 0,
3993	VHCA_ID_TYPE_SW = 1,
3994	};
3995
3996	struct mlx5_ifc_nic_vport_context_bits {
3997	u8 reserved_at_0[0x5];
3998	u8 min_wqe_inline_mode[0x3];
3999	u8 reserved_at_8[0x15];
4000	u8 disable_mc_local_lb[0x1];
4001	u8 disable_uc_local_lb[0x1];
4002	u8 roce_en[0x1];
4003
4004	u8 arm_change_event[0x1];
4005	u8 reserved_at_21[0x1a];
4006	u8 event_on_mtu[0x1];
4007	u8 event_on_promisc_change[0x1];
4008	u8 event_on_vlan_change[0x1];
4009	u8 event_on_mc_address_change[0x1];
4010	u8 event_on_uc_address_change[0x1];
4011
4012	u8 vhca_id_type[0x1];
4013	u8 reserved_at_41[0xb];
4014	u8 affiliation_criteria[0x4];
4015	u8 affiliated_vhca_id[0x10];
4016
4017	u8 reserved_at_60[0xd0];
4018
4019	u8 mtu[0x10];
4020
4021	u8 system_image_guid[0x40];
4022	u8 port_guid[0x40];
4023	u8 node_guid[0x40];
4024
4025	u8 reserved_at_200[0x140];
4026	u8 qkey_violation_counter[0x10];
4027	u8 reserved_at_350[0x430];
4028
4029	u8 promisc_uc[0x1];
4030	u8 promisc_mc[0x1];
4031	u8 promisc_all[0x1];
4032	u8 reserved_at_783[0x2];
4033	u8 allowed_list_type[0x3];
4034	u8 reserved_at_788[0xc];
4035	u8 allowed_list_size[0xc];
4036
4037	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4038
4039	u8 reserved_at_7e0[0x20];
4040
4041	u8 current_uc_mac_address[][0x40];
4042	};
4043
4044	enum {
4045	MLX5_MKC_ACCESS_MODE_PA = 0x0,
4046	MLX5_MKC_ACCESS_MODE_MTT = 0x1,
4047	MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
4048	MLX5_MKC_ACCESS_MODE_KSM = 0x3,
4049	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4050	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4051	};
4052
4053	struct mlx5_ifc_mkc_bits {
4054	u8 reserved_at_0[0x1];
4055	u8 free[0x1];
4056	u8 reserved_at_2[0x1];
4057	u8 access_mode_4_2[0x3];
4058	u8 reserved_at_6[0x7];
4059	u8 relaxed_ordering_write[0x1];
4060	u8 reserved_at_e[0x1];
4061	u8 small_fence_on_rdma_read_response[0x1];
4062	u8 umr_en[0x1];
4063	u8 a[0x1];
4064	u8 rw[0x1];
4065	u8 rr[0x1];
4066	u8 lw[0x1];
4067	u8 lr[0x1];
4068	u8 access_mode_1_0[0x2];
4069	u8 reserved_at_18[0x2];
4070	u8 ma_translation_mode[0x2];
4071	u8 reserved_at_1c[0x4];
4072
4073	u8 qpn[0x18];
4074	u8 mkey_7_0[0x8];
4075
4076	u8 reserved_at_40[0x20];
4077
4078	u8 length64[0x1];
4079	u8 bsf_en[0x1];
4080	u8 sync_umr[0x1];
4081	u8 reserved_at_63[0x2];
4082	u8 expected_sigerr_count[0x1];
4083	u8 reserved_at_66[0x1];
4084	u8 en_rinval[0x1];
4085	u8 pd[0x18];
4086
4087	u8 start_addr[0x40];
4088
4089	u8 len[0x40];
4090
4091	u8 bsf_octword_size[0x20];
4092
4093	u8 reserved_at_120[0x80];
4094
4095	u8 translations_octword_size[0x20];
4096
4097	u8 reserved_at_1c0[0x19];
4098	u8 relaxed_ordering_read[0x1];
4099	u8 reserved_at_1d9[0x1];
4100	u8 log_page_size[0x5];
4101
4102	u8 reserved_at_1e0[0x20];
4103	};
4104
4105	struct mlx5_ifc_pkey_bits {
4106	u8 reserved_at_0[0x10];
4107	u8 pkey[0x10];
4108	};
4109
4110	struct mlx5_ifc_array128_auto_bits {
4111	u8 array128_auto[16][0x8];
4112	};
4113
4114	struct mlx5_ifc_hca_vport_context_bits {
4115	u8 field_select[0x20];
4116
4117	u8 reserved_at_20[0xe0];
4118
4119	u8 sm_virt_aware[0x1];
4120	u8 has_smi[0x1];
4121	u8 has_raw[0x1];
4122	u8 grh_required[0x1];
4123	u8 reserved_at_104[0xc];
4124	u8 port_physical_state[0x4];
4125	u8 vport_state_policy[0x4];
4126	u8 port_state[0x4];
4127	u8 vport_state[0x4];
4128
4129	u8 reserved_at_120[0x20];
4130
4131	u8 system_image_guid[0x40];
4132
4133	u8 port_guid[0x40];
4134
4135	u8 node_guid[0x40];
4136
4137	u8 cap_mask1[0x20];
4138
4139	u8 cap_mask1_field_select[0x20];
4140
4141	u8 cap_mask2[0x20];
4142
4143	u8 cap_mask2_field_select[0x20];
4144
4145	u8 reserved_at_280[0x80];
4146
4147	u8 lid[0x10];
4148	u8 reserved_at_310[0x4];
4149	u8 init_type_reply[0x4];
4150	u8 lmc[0x3];
4151	u8 subnet_timeout[0x5];
4152
4153	u8 sm_lid[0x10];
4154	u8 sm_sl[0x4];
4155	u8 reserved_at_334[0xc];
4156
4157	u8 qkey_violation_counter[0x10];
4158	u8 pkey_violation_counter[0x10];
4159
4160	u8 reserved_at_360[0xca0];
4161	};
4162
4163	struct mlx5_ifc_esw_vport_context_bits {
4164	u8 fdb_to_vport_reg_c[0x1];
4165	u8 reserved_at_1[0x2];
4166	u8 vport_svlan_strip[0x1];
4167	u8 vport_cvlan_strip[0x1];
4168	u8 vport_svlan_insert[0x1];
4169	u8 vport_cvlan_insert[0x2];
4170	u8 fdb_to_vport_reg_c_id[0x8];
4171	u8 reserved_at_10[0x10];
4172
4173	u8 reserved_at_20[0x20];
4174
4175	u8 svlan_cfi[0x1];
4176	u8 svlan_pcp[0x3];
4177	u8 svlan_id[0xc];
4178	u8 cvlan_cfi[0x1];
4179	u8 cvlan_pcp[0x3];
4180	u8 cvlan_id[0xc];
4181
4182	u8 reserved_at_60[0x720];
4183
4184	u8 sw_steering_vport_icm_address_rx[0x40];
4185
4186	u8 sw_steering_vport_icm_address_tx[0x40];
4187	};
4188
4189	enum {
4190	MLX5_EQC_STATUS_OK = 0x0,
4191	MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4192	};
4193
4194	enum {
4195	MLX5_EQC_ST_ARMED = 0x9,
4196	MLX5_EQC_ST_FIRED = 0xa,
4197	};
4198
4199	struct mlx5_ifc_eqc_bits {
4200	u8 status[0x4];
4201	u8 reserved_at_4[0x9];
4202	u8 ec[0x1];
4203	u8 oi[0x1];
4204	u8 reserved_at_f[0x5];
4205	u8 st[0x4];
4206	u8 reserved_at_18[0x8];
4207
4208	u8 reserved_at_20[0x20];
4209
4210	u8 reserved_at_40[0x14];
4211	u8 page_offset[0x6];
4212	u8 reserved_at_5a[0x6];
4213
4214	u8 reserved_at_60[0x3];
4215	u8 log_eq_size[0x5];
4216	u8 uar_page[0x18];
4217
4218	u8 reserved_at_80[0x20];
4219
4220	u8 reserved_at_a0[0x14];
4221	u8 intr[0xc];
4222
4223	u8 reserved_at_c0[0x3];
4224	u8 log_page_size[0x5];
4225	u8 reserved_at_c8[0x18];
4226
4227	u8 reserved_at_e0[0x60];
4228
4229	u8 reserved_at_140[0x8];
4230	u8 consumer_counter[0x18];
4231
4232	u8 reserved_at_160[0x8];
4233	u8 producer_counter[0x18];
4234
4235	u8 reserved_at_180[0x80];
4236	};
4237
4238	enum {
4239	MLX5_DCTC_STATE_ACTIVE = 0x0,
4240	MLX5_DCTC_STATE_DRAINING = 0x1,
4241	MLX5_DCTC_STATE_DRAINED = 0x2,
4242	};
4243
4244	enum {
4245	MLX5_DCTC_CS_RES_DISABLE = 0x0,
4246	MLX5_DCTC_CS_RES_NA = 0x1,
4247	MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4248	};
4249
4250	enum {
4251	MLX5_DCTC_MTU_256_BYTES = 0x1,
4252	MLX5_DCTC_MTU_512_BYTES = 0x2,
4253	MLX5_DCTC_MTU_1K_BYTES = 0x3,
4254	MLX5_DCTC_MTU_2K_BYTES = 0x4,
4255	MLX5_DCTC_MTU_4K_BYTES = 0x5,
4256	};
4257
4258	struct mlx5_ifc_dctc_bits {
4259	u8 reserved_at_0[0x4];
4260	u8 state[0x4];
4261	u8 reserved_at_8[0x18];
4262
4263	u8 reserved_at_20[0x8];
4264	u8 user_index[0x18];
4265
4266	u8 reserved_at_40[0x8];
4267	u8 cqn[0x18];
4268
4269	u8 counter_set_id[0x8];
4270	u8 atomic_mode[0x4];
4271	u8 rre[0x1];
4272	u8 rwe[0x1];
4273	u8 rae[0x1];
4274	u8 atomic_like_write_en[0x1];
4275	u8 latency_sensitive[0x1];
4276	u8 rlky[0x1];
4277	u8 free_ar[0x1];
4278	u8 reserved_at_73[0xd];
4279
4280	u8 reserved_at_80[0x8];
4281	u8 cs_res[0x8];
4282	u8 reserved_at_90[0x3];
4283	u8 min_rnr_nak[0x5];
4284	u8 reserved_at_98[0x8];
4285
4286	u8 reserved_at_a0[0x8];
4287	u8 srqn_xrqn[0x18];
4288
4289	u8 reserved_at_c0[0x8];
4290	u8 pd[0x18];
4291
4292	u8 tclass[0x8];
4293	u8 reserved_at_e8[0x4];
4294	u8 flow_label[0x14];
4295
4296	u8 dc_access_key[0x40];
4297
4298	u8 reserved_at_140[0x5];
4299	u8 mtu[0x3];
4300	u8 port[0x8];
4301	u8 pkey_index[0x10];
4302
4303	u8 reserved_at_160[0x8];
4304	u8 my_addr_index[0x8];
4305	u8 reserved_at_170[0x8];
4306	u8 hop_limit[0x8];
4307
4308	u8 dc_access_key_violation_count[0x20];
4309
4310	u8 reserved_at_1a0[0x14];
4311	u8 dei_cfi[0x1];
4312	u8 eth_prio[0x3];
4313	u8 ecn[0x2];
4314	u8 dscp[0x6];
4315
4316	u8 reserved_at_1c0[0x20];
4317	u8 ece[0x20];
4318	};
4319
4320	enum {
4321	MLX5_CQC_STATUS_OK = 0x0,
4322	MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4323	MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4324	};
4325
4326	enum {
4327	MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4328	MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4329	};
4330
4331	enum {
4332	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4333	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4334	MLX5_CQC_ST_FIRED = 0xa,
4335	};
4336
4337	enum {
4338	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4339	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4340	MLX5_CQ_PERIOD_NUM_MODES
4341	};
4342
4343	struct mlx5_ifc_cqc_bits {
4344	u8 status[0x4];
4345	u8 reserved_at_4[0x2];
4346	u8 dbr_umem_valid[0x1];
4347	u8 apu_cq[0x1];
4348	u8 cqe_sz[0x3];
4349	u8 cc[0x1];
4350	u8 reserved_at_c[0x1];
4351	u8 scqe_break_moderation_en[0x1];
4352	u8 oi[0x1];
4353	u8 cq_period_mode[0x2];
4354	u8 cqe_comp_en[0x1];
4355	u8 mini_cqe_res_format[0x2];
4356	u8 st[0x4];
4357	u8 reserved_at_18[0x6];
4358	u8 cqe_compression_layout[0x2];
4359
4360	u8 reserved_at_20[0x20];
4361
4362	u8 reserved_at_40[0x14];
4363	u8 page_offset[0x6];
4364	u8 reserved_at_5a[0x6];
4365
4366	u8 reserved_at_60[0x3];
4367	u8 log_cq_size[0x5];
4368	u8 uar_page[0x18];
4369
4370	u8 reserved_at_80[0x4];
4371	u8 cq_period[0xc];
4372	u8 cq_max_count[0x10];
4373
4374	u8 c_eqn_or_apu_element[0x20];
4375
4376	u8 reserved_at_c0[0x3];
4377	u8 log_page_size[0x5];
4378	u8 reserved_at_c8[0x18];
4379
4380	u8 reserved_at_e0[0x20];
4381
4382	u8 reserved_at_100[0x8];
4383	u8 last_notified_index[0x18];
4384
4385	u8 reserved_at_120[0x8];
4386	u8 last_solicit_index[0x18];
4387
4388	u8 reserved_at_140[0x8];
4389	u8 consumer_counter[0x18];
4390
4391	u8 reserved_at_160[0x8];
4392	u8 producer_counter[0x18];
4393
4394	u8 reserved_at_180[0x40];
4395
4396	u8 dbr_addr[0x40];
4397	};
4398
4399	union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4400	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4401	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4402	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4403	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4404	u8 reserved_at_0[0x800];
4405	};
4406
4407	struct mlx5_ifc_query_adapter_param_block_bits {
4408	u8 reserved_at_0[0xc0];
4409
4410	u8 reserved_at_c0[0x8];
4411	u8 ieee_vendor_id[0x18];
4412
4413	u8 reserved_at_e0[0x10];
4414	u8 vsd_vendor_id[0x10];
4415
4416	u8 vsd[208][0x8];
4417
4418	u8 vsd_contd_psid[16][0x8];
4419	};
4420
4421	enum {
4422	MLX5_XRQC_STATE_GOOD = 0x0,
4423	MLX5_XRQC_STATE_ERROR = 0x1,
4424	};
4425
4426	enum {
4427	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4428	MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4429	};
4430
4431	enum {
4432	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4433	};
4434
4435	struct mlx5_ifc_tag_matching_topology_context_bits {
4436	u8 log_matching_list_sz[0x4];
4437	u8 reserved_at_4[0xc];
4438	u8 append_next_index[0x10];
4439
4440	u8 sw_phase_cnt[0x10];
4441	u8 hw_phase_cnt[0x10];
4442
4443	u8 reserved_at_40[0x40];
4444	};
4445
4446	struct mlx5_ifc_xrqc_bits {
4447	u8 state[0x4];
4448	u8 rlkey[0x1];
4449	u8 reserved_at_5[0xf];
4450	u8 topology[0x4];
4451	u8 reserved_at_18[0x4];
4452	u8 offload[0x4];
4453
4454	u8 reserved_at_20[0x8];
4455	u8 user_index[0x18];
4456
4457	u8 reserved_at_40[0x8];
4458	u8 cqn[0x18];
4459
4460	u8 reserved_at_60[0xa0];
4461
4462	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4463
4464	u8 reserved_at_180[0x280];
4465
4466	struct mlx5_ifc_wq_bits wq;
4467	};
4468
4469	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4470	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4471	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4472	u8 reserved_at_0[0x20];
4473	};
4474
4475	union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4476	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4477	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4478	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4479	u8 reserved_at_0[0x20];
4480	};
4481
4482	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4483	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4484	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4485	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4486	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4487	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4488	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4489	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4490	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4491	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4492	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4493	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4494	u8 reserved_at_0[0x7c0];
4495	};
4496
4497	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4498	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4499	u8 reserved_at_0[0x7c0];
4500	};
4501
4502	union mlx5_ifc_event_auto_bits {
4503	struct mlx5_ifc_comp_event_bits comp_event;
4504	struct mlx5_ifc_dct_events_bits dct_events;
4505	struct mlx5_ifc_qp_events_bits qp_events;
4506	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4507	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4508	struct mlx5_ifc_cq_error_bits cq_error;
4509	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4510	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4511	struct mlx5_ifc_gpio_event_bits gpio_event;
4512	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4513	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4514	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4515	u8 reserved_at_0[0xe0];
4516	};
4517
4518	struct mlx5_ifc_health_buffer_bits {
4519	u8 reserved_at_0[0x100];
4520
4521	u8 assert_existptr[0x20];
4522
4523	u8 assert_callra[0x20];
4524
4525	u8 reserved_at_140[0x20];
4526
4527	u8 time[0x20];
4528
4529	u8 fw_version[0x20];
4530
4531	u8 hw_id[0x20];
4532
4533	u8 rfr[0x1];
4534	u8 reserved_at_1c1[0x3];
4535	u8 valid[0x1];
4536	u8 severity[0x3];
4537	u8 reserved_at_1c8[0x18];
4538
4539	u8 irisc_index[0x8];
4540	u8 synd[0x8];
4541	u8 ext_synd[0x10];
4542	};
4543
4544	struct mlx5_ifc_register_loopback_control_bits {
4545	u8 no_lb[0x1];
4546	u8 reserved_at_1[0x7];
4547	u8 port[0x8];
4548	u8 reserved_at_10[0x10];
4549
4550	u8 reserved_at_20[0x60];
4551	};
4552
4553	struct mlx5_ifc_vport_tc_element_bits {
4554	u8 traffic_class[0x4];
4555	u8 reserved_at_4[0xc];
4556	u8 vport_number[0x10];
4557	};
4558
4559	struct mlx5_ifc_vport_element_bits {
4560	u8 reserved_at_0[0x10];
4561	u8 vport_number[0x10];
4562	};
4563
4564	enum {
4565	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4566	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4567	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4568	};
4569
4570	struct mlx5_ifc_tsar_element_bits {
4571	u8 reserved_at_0[0x8];
4572	u8 tsar_type[0x8];
4573	u8 reserved_at_10[0x10];
4574	};
4575
4576	enum {
4577	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4578	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4579	};
4580
4581	struct mlx5_ifc_teardown_hca_out_bits {
4582	u8 status[0x8];
4583	u8 reserved_at_8[0x18];
4584
4585	u8 syndrome[0x20];
4586
4587	u8 reserved_at_40[0x3f];
4588
4589	u8 state[0x1];
4590	};
4591
4592	enum {
4593	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4594	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4595	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4596	};
4597
4598	struct mlx5_ifc_teardown_hca_in_bits {
4599	u8 opcode[0x10];
4600	u8 reserved_at_10[0x10];
4601
4602	u8 reserved_at_20[0x10];
4603	u8 op_mod[0x10];
4604
4605	u8 reserved_at_40[0x10];
4606	u8 profile[0x10];
4607
4608	u8 reserved_at_60[0x20];
4609	};
4610
4611	struct mlx5_ifc_sqerr2rts_qp_out_bits {
4612	u8 status[0x8];
4613	u8 reserved_at_8[0x18];
4614
4615	u8 syndrome[0x20];
4616
4617	u8 reserved_at_40[0x40];
4618	};
4619
4620	struct mlx5_ifc_sqerr2rts_qp_in_bits {
4621	u8 opcode[0x10];
4622	u8 uid[0x10];
4623
4624	u8 reserved_at_20[0x10];
4625	u8 op_mod[0x10];
4626
4627	u8 reserved_at_40[0x8];
4628	u8 qpn[0x18];
4629
4630	u8 reserved_at_60[0x20];
4631
4632	u8 opt_param_mask[0x20];
4633
4634	u8 reserved_at_a0[0x20];
4635
4636	struct mlx5_ifc_qpc_bits qpc;
4637
4638	u8 reserved_at_800[0x80];
4639	};
4640
4641	struct mlx5_ifc_sqd2rts_qp_out_bits {
4642	u8 status[0x8];
4643	u8 reserved_at_8[0x18];
4644
4645	u8 syndrome[0x20];
4646
4647	u8 reserved_at_40[0x40];
4648	};
4649
4650	struct mlx5_ifc_sqd2rts_qp_in_bits {
4651	u8 opcode[0x10];
4652	u8 uid[0x10];
4653
4654	u8 reserved_at_20[0x10];
4655	u8 op_mod[0x10];
4656
4657	u8 reserved_at_40[0x8];
4658	u8 qpn[0x18];
4659
4660	u8 reserved_at_60[0x20];
4661
4662	u8 opt_param_mask[0x20];
4663
4664	u8 reserved_at_a0[0x20];
4665
4666	struct mlx5_ifc_qpc_bits qpc;
4667
4668	u8 reserved_at_800[0x80];
4669	};
4670
4671	struct mlx5_ifc_set_roce_address_out_bits {
4672	u8 status[0x8];
4673	u8 reserved_at_8[0x18];
4674
4675	u8 syndrome[0x20];
4676
4677	u8 reserved_at_40[0x40];
4678	};
4679
4680	struct mlx5_ifc_set_roce_address_in_bits {
4681	u8 opcode[0x10];
4682	u8 reserved_at_10[0x10];
4683
4684	u8 reserved_at_20[0x10];
4685	u8 op_mod[0x10];
4686
4687	u8 roce_address_index[0x10];
4688	u8 reserved_at_50[0xc];
4689	u8 vhca_port_num[0x4];
4690
4691	u8 reserved_at_60[0x20];
4692
4693	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4694	};
4695
4696	struct mlx5_ifc_set_mad_demux_out_bits {
4697	u8 status[0x8];
4698	u8 reserved_at_8[0x18];
4699
4700	u8 syndrome[0x20];
4701
4702	u8 reserved_at_40[0x40];
4703	};
4704
4705	enum {
4706	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4707	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4708	};
4709
4710	struct mlx5_ifc_set_mad_demux_in_bits {
4711	u8 opcode[0x10];
4712	u8 reserved_at_10[0x10];
4713
4714	u8 reserved_at_20[0x10];
4715	u8 op_mod[0x10];
4716
4717	u8 reserved_at_40[0x20];
4718
4719	u8 reserved_at_60[0x6];
4720	u8 demux_mode[0x2];
4721	u8 reserved_at_68[0x18];
4722	};
4723
4724	struct mlx5_ifc_set_l2_table_entry_out_bits {
4725	u8 status[0x8];
4726	u8 reserved_at_8[0x18];
4727
4728	u8 syndrome[0x20];
4729
4730	u8 reserved_at_40[0x40];
4731	};
4732
4733	struct mlx5_ifc_set_l2_table_entry_in_bits {
4734	u8 opcode[0x10];
4735	u8 reserved_at_10[0x10];
4736
4737	u8 reserved_at_20[0x10];
4738	u8 op_mod[0x10];
4739
4740	u8 reserved_at_40[0x60];
4741
4742	u8 reserved_at_a0[0x8];
4743	u8 table_index[0x18];
4744
4745	u8 reserved_at_c0[0x20];
4746
4747	u8 reserved_at_e0[0x13];
4748	u8 vlan_valid[0x1];
4749	u8 vlan[0xc];
4750
4751	struct mlx5_ifc_mac_address_layout_bits mac_address;
4752
4753	u8 reserved_at_140[0xc0];
4754	};
4755
4756	struct mlx5_ifc_set_issi_out_bits {
4757	u8 status[0x8];
4758	u8 reserved_at_8[0x18];
4759
4760	u8 syndrome[0x20];
4761
4762	u8 reserved_at_40[0x40];
4763	};
4764
4765	struct mlx5_ifc_set_issi_in_bits {
4766	u8 opcode[0x10];
4767	u8 reserved_at_10[0x10];
4768
4769	u8 reserved_at_20[0x10];
4770	u8 op_mod[0x10];
4771
4772	u8 reserved_at_40[0x10];
4773	u8 current_issi[0x10];
4774
4775	u8 reserved_at_60[0x20];
4776	};
4777
4778	struct mlx5_ifc_set_hca_cap_out_bits {
4779	u8 status[0x8];
4780	u8 reserved_at_8[0x18];
4781
4782	u8 syndrome[0x20];
4783
4784	u8 reserved_at_40[0x40];
4785	};
4786
4787	struct mlx5_ifc_set_hca_cap_in_bits {
4788	u8 opcode[0x10];
4789	u8 reserved_at_10[0x10];
4790
4791	u8 reserved_at_20[0x10];
4792	u8 op_mod[0x10];
4793
4794	u8 other_function[0x1];
4795	u8 ec_vf_function[0x1];
4796	u8 reserved_at_42[0xe];
4797	u8 function_id[0x10];
4798
4799	u8 reserved_at_60[0x20];
4800
4801	union mlx5_ifc_hca_cap_union_bits capability;
4802	};
4803
4804	enum {
4805	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4806	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4807	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4808	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4809	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4810	};
4811
4812	struct mlx5_ifc_set_fte_out_bits {
4813	u8 status[0x8];
4814	u8 reserved_at_8[0x18];
4815
4816	u8 syndrome[0x20];
4817
4818	u8 reserved_at_40[0x40];
4819	};
4820
4821	struct mlx5_ifc_set_fte_in_bits {
4822	u8 opcode[0x10];
4823	u8 reserved_at_10[0x10];
4824
4825	u8 reserved_at_20[0x10];
4826	u8 op_mod[0x10];
4827
4828	u8 other_vport[0x1];
4829	u8 reserved_at_41[0xf];
4830	u8 vport_number[0x10];
4831
4832	u8 reserved_at_60[0x20];
4833
4834	u8 table_type[0x8];
4835	u8 reserved_at_88[0x18];
4836
4837	u8 reserved_at_a0[0x8];
4838	u8 table_id[0x18];
4839
4840	u8 ignore_flow_level[0x1];
4841	u8 reserved_at_c1[0x17];
4842	u8 modify_enable_mask[0x8];
4843
4844	u8 reserved_at_e0[0x20];
4845
4846	u8 flow_index[0x20];
4847
4848	u8 reserved_at_120[0xe0];
4849
4850	struct mlx5_ifc_flow_context_bits flow_context;
4851	};
4852
4853	struct mlx5_ifc_rts2rts_qp_out_bits {
4854	u8 status[0x8];
4855	u8 reserved_at_8[0x18];
4856
4857	u8 syndrome[0x20];
4858
4859	u8 reserved_at_40[0x20];
4860	u8 ece[0x20];
4861	};
4862
4863	struct mlx5_ifc_rts2rts_qp_in_bits {
4864	u8 opcode[0x10];
4865	u8 uid[0x10];
4866
4867	u8 reserved_at_20[0x10];
4868	u8 op_mod[0x10];
4869
4870	u8 reserved_at_40[0x8];
4871	u8 qpn[0x18];
4872
4873	u8 reserved_at_60[0x20];
4874
4875	u8 opt_param_mask[0x20];
4876
4877	u8 ece[0x20];
4878
4879	struct mlx5_ifc_qpc_bits qpc;
4880
4881	u8 reserved_at_800[0x80];
4882	};
4883
4884	struct mlx5_ifc_rtr2rts_qp_out_bits {
4885	u8 status[0x8];
4886	u8 reserved_at_8[0x18];
4887
4888	u8 syndrome[0x20];
4889
4890	u8 reserved_at_40[0x20];
4891	u8 ece[0x20];
4892	};
4893
4894	struct mlx5_ifc_rtr2rts_qp_in_bits {
4895	u8 opcode[0x10];
4896	u8 uid[0x10];
4897
4898	u8 reserved_at_20[0x10];
4899	u8 op_mod[0x10];
4900
4901	u8 reserved_at_40[0x8];
4902	u8 qpn[0x18];
4903
4904	u8 reserved_at_60[0x20];
4905
4906	u8 opt_param_mask[0x20];
4907
4908	u8 ece[0x20];
4909
4910	struct mlx5_ifc_qpc_bits qpc;
4911
4912	u8 reserved_at_800[0x80];
4913	};
4914
4915	struct mlx5_ifc_rst2init_qp_out_bits {
4916	u8 status[0x8];
4917	u8 reserved_at_8[0x18];
4918
4919	u8 syndrome[0x20];
4920
4921	u8 reserved_at_40[0x20];
4922	u8 ece[0x20];
4923	};
4924
4925	struct mlx5_ifc_rst2init_qp_in_bits {
4926	u8 opcode[0x10];
4927	u8 uid[0x10];
4928
4929	u8 reserved_at_20[0x10];
4930	u8 op_mod[0x10];
4931
4932	u8 reserved_at_40[0x8];
4933	u8 qpn[0x18];
4934
4935	u8 reserved_at_60[0x20];
4936
4937	u8 opt_param_mask[0x20];
4938
4939	u8 ece[0x20];
4940
4941	struct mlx5_ifc_qpc_bits qpc;
4942
4943	u8 reserved_at_800[0x80];
4944	};
4945
4946	struct mlx5_ifc_query_xrq_out_bits {
4947	u8 status[0x8];
4948	u8 reserved_at_8[0x18];
4949
4950	u8 syndrome[0x20];
4951
4952	u8 reserved_at_40[0x40];
4953
4954	struct mlx5_ifc_xrqc_bits xrq_context;
4955	};
4956
4957	struct mlx5_ifc_query_xrq_in_bits {
4958	u8 opcode[0x10];
4959	u8 reserved_at_10[0x10];
4960
4961	u8 reserved_at_20[0x10];
4962	u8 op_mod[0x10];
4963
4964	u8 reserved_at_40[0x8];
4965	u8 xrqn[0x18];
4966
4967	u8 reserved_at_60[0x20];
4968	};
4969
4970	struct mlx5_ifc_query_xrc_srq_out_bits {
4971	u8 status[0x8];
4972	u8 reserved_at_8[0x18];
4973
4974	u8 syndrome[0x20];
4975
4976	u8 reserved_at_40[0x40];
4977
4978	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4979
4980	u8 reserved_at_280[0x600];
4981
4982	u8 pas[][0x40];
4983	};
4984
4985	struct mlx5_ifc_query_xrc_srq_in_bits {
4986	u8 opcode[0x10];
4987	u8 reserved_at_10[0x10];
4988
4989	u8 reserved_at_20[0x10];
4990	u8 op_mod[0x10];
4991
4992	u8 reserved_at_40[0x8];
4993	u8 xrc_srqn[0x18];
4994
4995	u8 reserved_at_60[0x20];
4996	};
4997
4998	enum {
4999	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
5000	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
5001	};
5002
5003	struct mlx5_ifc_query_vport_state_out_bits {
5004	u8 status[0x8];
5005	u8 reserved_at_8[0x18];
5006
5007	u8 syndrome[0x20];
5008
5009	u8 reserved_at_40[0x20];
5010
5011	u8 reserved_at_60[0x18];
5012	u8 admin_state[0x4];
5013	u8 state[0x4];
5014	};
5015
5016	enum {
5017	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
5018	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
5019	MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
5020	};
5021
5022	struct mlx5_ifc_arm_monitor_counter_in_bits {
5023	u8 opcode[0x10];
5024	u8 uid[0x10];
5025
5026	u8 reserved_at_20[0x10];
5027	u8 op_mod[0x10];
5028
5029	u8 reserved_at_40[0x20];
5030
5031	u8 reserved_at_60[0x20];
5032	};
5033
5034	struct mlx5_ifc_arm_monitor_counter_out_bits {
5035	u8 status[0x8];
5036	u8 reserved_at_8[0x18];
5037
5038	u8 syndrome[0x20];
5039
5040	u8 reserved_at_40[0x40];
5041	};
5042
5043	enum {
5044	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
5045	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5046	};
5047
5048	enum mlx5_monitor_counter_ppcnt {
5049	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
5050	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
5051	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
5052	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5053	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
5054	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
5055	};
5056
5057	enum {
5058	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
5059	};
5060
5061	struct mlx5_ifc_monitor_counter_output_bits {
5062	u8 reserved_at_0[0x4];
5063	u8 type[0x4];
5064	u8 reserved_at_8[0x8];
5065	u8 counter[0x10];
5066
5067	u8 counter_group_id[0x20];
5068	};
5069
5070	#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5071	#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
5072	#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5073	MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5074
5075	struct mlx5_ifc_set_monitor_counter_in_bits {
5076	u8 opcode[0x10];
5077	u8 uid[0x10];
5078
5079	u8 reserved_at_20[0x10];
5080	u8 op_mod[0x10];
5081
5082	u8 reserved_at_40[0x10];
5083	u8 num_of_counters[0x10];
5084
5085	u8 reserved_at_60[0x20];
5086
5087	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5088	};
5089
5090	struct mlx5_ifc_set_monitor_counter_out_bits {
5091	u8 status[0x8];
5092	u8 reserved_at_8[0x18];
5093
5094	u8 syndrome[0x20];
5095
5096	u8 reserved_at_40[0x40];
5097	};
5098
5099	struct mlx5_ifc_query_vport_state_in_bits {
5100	u8 opcode[0x10];
5101	u8 reserved_at_10[0x10];
5102
5103	u8 reserved_at_20[0x10];
5104	u8 op_mod[0x10];
5105
5106	u8 other_vport[0x1];
5107	u8 reserved_at_41[0xf];
5108	u8 vport_number[0x10];
5109
5110	u8 reserved_at_60[0x20];
5111	};
5112
5113	struct mlx5_ifc_query_vnic_env_out_bits {
5114	u8 status[0x8];
5115	u8 reserved_at_8[0x18];
5116
5117	u8 syndrome[0x20];
5118
5119	u8 reserved_at_40[0x40];
5120
5121	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5122	};
5123
5124	enum {
5125	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5126	};
5127
5128	struct mlx5_ifc_query_vnic_env_in_bits {
5129	u8 opcode[0x10];
5130	u8 reserved_at_10[0x10];
5131
5132	u8 reserved_at_20[0x10];
5133	u8 op_mod[0x10];
5134
5135	u8 other_vport[0x1];
5136	u8 reserved_at_41[0xf];
5137	u8 vport_number[0x10];
5138
5139	u8 reserved_at_60[0x20];
5140	};
5141
5142	struct mlx5_ifc_query_vport_counter_out_bits {
5143	u8 status[0x8];
5144	u8 reserved_at_8[0x18];
5145
5146	u8 syndrome[0x20];
5147
5148	u8 reserved_at_40[0x40];
5149
5150	struct mlx5_ifc_traffic_counter_bits received_errors;
5151
5152	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5153
5154	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5155
5156	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5157
5158	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5159
5160	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5161
5162	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5163
5164	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5165
5166	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5167
5168	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5169
5170	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5171
5172	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5173
5174	struct mlx5_ifc_traffic_counter_bits local_loopback;
5175
5176	u8 reserved_at_700[0x980];
5177	};
5178
5179	enum {
5180	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5181	};
5182
5183	struct mlx5_ifc_query_vport_counter_in_bits {
5184	u8 opcode[0x10];
5185	u8 reserved_at_10[0x10];
5186
5187	u8 reserved_at_20[0x10];
5188	u8 op_mod[0x10];
5189
5190	u8 other_vport[0x1];
5191	u8 reserved_at_41[0xb];
5192	u8 port_num[0x4];
5193	u8 vport_number[0x10];
5194
5195	u8 reserved_at_60[0x60];
5196
5197	u8 clear[0x1];
5198	u8 reserved_at_c1[0x1f];
5199
5200	u8 reserved_at_e0[0x20];
5201	};
5202
5203	struct mlx5_ifc_query_tis_out_bits {
5204	u8 status[0x8];
5205	u8 reserved_at_8[0x18];
5206
5207	u8 syndrome[0x20];
5208
5209	u8 reserved_at_40[0x40];
5210
5211	struct mlx5_ifc_tisc_bits tis_context;
5212	};
5213
5214	struct mlx5_ifc_query_tis_in_bits {
5215	u8 opcode[0x10];
5216	u8 reserved_at_10[0x10];
5217
5218	u8 reserved_at_20[0x10];
5219	u8 op_mod[0x10];
5220
5221	u8 reserved_at_40[0x8];
5222	u8 tisn[0x18];
5223
5224	u8 reserved_at_60[0x20];
5225	};
5226
5227	struct mlx5_ifc_query_tir_out_bits {
5228	u8 status[0x8];
5229	u8 reserved_at_8[0x18];
5230
5231	u8 syndrome[0x20];
5232
5233	u8 reserved_at_40[0xc0];
5234
5235	struct mlx5_ifc_tirc_bits tir_context;
5236	};
5237
5238	struct mlx5_ifc_query_tir_in_bits {
5239	u8 opcode[0x10];
5240	u8 reserved_at_10[0x10];
5241
5242	u8 reserved_at_20[0x10];
5243	u8 op_mod[0x10];
5244
5245	u8 reserved_at_40[0x8];
5246	u8 tirn[0x18];
5247
5248	u8 reserved_at_60[0x20];
5249	};
5250
5251	struct mlx5_ifc_query_srq_out_bits {
5252	u8 status[0x8];
5253	u8 reserved_at_8[0x18];
5254
5255	u8 syndrome[0x20];
5256
5257	u8 reserved_at_40[0x40];
5258
5259	struct mlx5_ifc_srqc_bits srq_context_entry;
5260
5261	u8 reserved_at_280[0x600];
5262
5263	u8 pas[][0x40];
5264	};
5265
5266	struct mlx5_ifc_query_srq_in_bits {
5267	u8 opcode[0x10];
5268	u8 reserved_at_10[0x10];
5269
5270	u8 reserved_at_20[0x10];
5271	u8 op_mod[0x10];
5272
5273	u8 reserved_at_40[0x8];
5274	u8 srqn[0x18];
5275
5276	u8 reserved_at_60[0x20];
5277	};
5278
5279	struct mlx5_ifc_query_sq_out_bits {
5280	u8 status[0x8];
5281	u8 reserved_at_8[0x18];
5282
5283	u8 syndrome[0x20];
5284
5285	u8 reserved_at_40[0xc0];
5286
5287	struct mlx5_ifc_sqc_bits sq_context;
5288	};
5289
5290	struct mlx5_ifc_query_sq_in_bits {
5291	u8 opcode[0x10];
5292	u8 reserved_at_10[0x10];
5293
5294	u8 reserved_at_20[0x10];
5295	u8 op_mod[0x10];
5296
5297	u8 reserved_at_40[0x8];
5298	u8 sqn[0x18];
5299
5300	u8 reserved_at_60[0x20];
5301	};
5302
5303	struct mlx5_ifc_query_special_contexts_out_bits {
5304	u8 status[0x8];
5305	u8 reserved_at_8[0x18];
5306
5307	u8 syndrome[0x20];
5308
5309	u8 dump_fill_mkey[0x20];
5310
5311	u8 resd_lkey[0x20];
5312
5313	u8 null_mkey[0x20];
5314
5315	u8 terminate_scatter_list_mkey[0x20];
5316
5317	u8 repeated_mkey[0x20];
5318
5319	u8 reserved_at_a0[0x20];
5320	};
5321
5322	struct mlx5_ifc_query_special_contexts_in_bits {
5323	u8 opcode[0x10];
5324	u8 reserved_at_10[0x10];
5325
5326	u8 reserved_at_20[0x10];
5327	u8 op_mod[0x10];
5328
5329	u8 reserved_at_40[0x40];
5330	};
5331
5332	struct mlx5_ifc_query_scheduling_element_out_bits {
5333	u8 opcode[0x10];
5334	u8 reserved_at_10[0x10];
5335
5336	u8 reserved_at_20[0x10];
5337	u8 op_mod[0x10];
5338
5339	u8 reserved_at_40[0xc0];
5340
5341	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5342
5343	u8 reserved_at_300[0x100];
5344	};
5345
5346	enum {
5347	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5348	SCHEDULING_HIERARCHY_NIC = 0x3,
5349	};
5350
5351	struct mlx5_ifc_query_scheduling_element_in_bits {
5352	u8 opcode[0x10];
5353	u8 reserved_at_10[0x10];
5354
5355	u8 reserved_at_20[0x10];
5356	u8 op_mod[0x10];
5357
5358	u8 scheduling_hierarchy[0x8];
5359	u8 reserved_at_48[0x18];
5360
5361	u8 scheduling_element_id[0x20];
5362
5363	u8 reserved_at_80[0x180];
5364	};
5365
5366	struct mlx5_ifc_query_rqt_out_bits {
5367	u8 status[0x8];
5368	u8 reserved_at_8[0x18];
5369
5370	u8 syndrome[0x20];
5371
5372	u8 reserved_at_40[0xc0];
5373
5374	struct mlx5_ifc_rqtc_bits rqt_context;
5375	};
5376
5377	struct mlx5_ifc_query_rqt_in_bits {
5378	u8 opcode[0x10];
5379	u8 reserved_at_10[0x10];
5380
5381	u8 reserved_at_20[0x10];
5382	u8 op_mod[0x10];
5383
5384	u8 reserved_at_40[0x8];
5385	u8 rqtn[0x18];
5386
5387	u8 reserved_at_60[0x20];
5388	};
5389
5390	struct mlx5_ifc_query_rq_out_bits {
5391	u8 status[0x8];
5392	u8 reserved_at_8[0x18];
5393
5394	u8 syndrome[0x20];
5395
5396	u8 reserved_at_40[0xc0];
5397
5398	struct mlx5_ifc_rqc_bits rq_context;
5399	};
5400
5401	struct mlx5_ifc_query_rq_in_bits {
5402	u8 opcode[0x10];
5403	u8 reserved_at_10[0x10];
5404
5405	u8 reserved_at_20[0x10];
5406	u8 op_mod[0x10];
5407
5408	u8 reserved_at_40[0x8];
5409	u8 rqn[0x18];
5410
5411	u8 reserved_at_60[0x20];
5412	};
5413
5414	struct mlx5_ifc_query_roce_address_out_bits {
5415	u8 status[0x8];
5416	u8 reserved_at_8[0x18];
5417
5418	u8 syndrome[0x20];
5419
5420	u8 reserved_at_40[0x40];
5421
5422	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5423	};
5424
5425	struct mlx5_ifc_query_roce_address_in_bits {
5426	u8 opcode[0x10];
5427	u8 reserved_at_10[0x10];
5428
5429	u8 reserved_at_20[0x10];
5430	u8 op_mod[0x10];
5431
5432	u8 roce_address_index[0x10];
5433	u8 reserved_at_50[0xc];
5434	u8 vhca_port_num[0x4];
5435
5436	u8 reserved_at_60[0x20];
5437	};
5438
5439	struct mlx5_ifc_query_rmp_out_bits {
5440	u8 status[0x8];
5441	u8 reserved_at_8[0x18];
5442
5443	u8 syndrome[0x20];
5444
5445	u8 reserved_at_40[0xc0];
5446
5447	struct mlx5_ifc_rmpc_bits rmp_context;
5448	};
5449
5450	struct mlx5_ifc_query_rmp_in_bits {
5451	u8 opcode[0x10];
5452	u8 reserved_at_10[0x10];
5453
5454	u8 reserved_at_20[0x10];
5455	u8 op_mod[0x10];
5456
5457	u8 reserved_at_40[0x8];
5458	u8 rmpn[0x18];
5459
5460	u8 reserved_at_60[0x20];
5461	};
5462
5463	struct mlx5_ifc_cqe_error_syndrome_bits {
5464	u8 hw_error_syndrome[0x8];
5465	u8 hw_syndrome_type[0x4];
5466	u8 reserved_at_c[0x4];
5467	u8 vendor_error_syndrome[0x8];
5468	u8 syndrome[0x8];
5469	};
5470
5471	struct mlx5_ifc_qp_context_extension_bits {
5472	u8 reserved_at_0[0x60];
5473
5474	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5475
5476	u8 reserved_at_80[0x580];
5477	};
5478
5479	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5480	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5481
5482	u8 pas[0][0x40];
5483	};
5484
5485	struct mlx5_ifc_qp_pas_list_in_bits {
5486	struct mlx5_ifc_cmd_pas_bits pas[0];
5487	};
5488
5489	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5490	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5491	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5492	};
5493
5494	struct mlx5_ifc_query_qp_out_bits {
5495	u8 status[0x8];
5496	u8 reserved_at_8[0x18];
5497
5498	u8 syndrome[0x20];
5499
5500	u8 reserved_at_40[0x40];
5501
5502	u8 opt_param_mask[0x20];
5503
5504	u8 ece[0x20];
5505
5506	struct mlx5_ifc_qpc_bits qpc;
5507
5508	u8 reserved_at_800[0x80];
5509
5510	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5511	};
5512
5513	struct mlx5_ifc_query_qp_in_bits {
5514	u8 opcode[0x10];
5515	u8 reserved_at_10[0x10];
5516
5517	u8 reserved_at_20[0x10];
5518	u8 op_mod[0x10];
5519
5520	u8 qpc_ext[0x1];
5521	u8 reserved_at_41[0x7];
5522	u8 qpn[0x18];
5523
5524	u8 reserved_at_60[0x20];
5525	};
5526
5527	struct mlx5_ifc_query_q_counter_out_bits {
5528	u8 status[0x8];
5529	u8 reserved_at_8[0x18];
5530
5531	u8 syndrome[0x20];
5532
5533	u8 reserved_at_40[0x40];
5534
5535	u8 rx_write_requests[0x20];
5536
5537	u8 reserved_at_a0[0x20];
5538
5539	u8 rx_read_requests[0x20];
5540
5541	u8 reserved_at_e0[0x20];
5542
5543	u8 rx_atomic_requests[0x20];
5544
5545	u8 reserved_at_120[0x20];
5546
5547	u8 rx_dct_connect[0x20];
5548
5549	u8 reserved_at_160[0x20];
5550
5551	u8 out_of_buffer[0x20];
5552
5553	u8 reserved_at_1a0[0x20];
5554
5555	u8 out_of_sequence[0x20];
5556
5557	u8 reserved_at_1e0[0x20];
5558
5559	u8 duplicate_request[0x20];
5560
5561	u8 reserved_at_220[0x20];
5562
5563	u8 rnr_nak_retry_err[0x20];
5564
5565	u8 reserved_at_260[0x20];
5566
5567	u8 packet_seq_err[0x20];
5568
5569	u8 reserved_at_2a0[0x20];
5570
5571	u8 implied_nak_seq_err[0x20];
5572
5573	u8 reserved_at_2e0[0x20];
5574
5575	u8 local_ack_timeout_err[0x20];
5576
5577	u8 reserved_at_320[0xa0];
5578
5579	u8 resp_local_length_error[0x20];
5580
5581	u8 req_local_length_error[0x20];
5582
5583	u8 resp_local_qp_error[0x20];
5584
5585	u8 local_operation_error[0x20];
5586
5587	u8 resp_local_protection[0x20];
5588
5589	u8 req_local_protection[0x20];
5590
5591	u8 resp_cqe_error[0x20];
5592
5593	u8 req_cqe_error[0x20];
5594
5595	u8 req_mw_binding[0x20];
5596
5597	u8 req_bad_response[0x20];
5598
5599	u8 req_remote_invalid_request[0x20];
5600
5601	u8 resp_remote_invalid_request[0x20];
5602
5603	u8 req_remote_access_errors[0x20];
5604
5605	u8 resp_remote_access_errors[0x20];
5606
5607	u8 req_remote_operation_errors[0x20];
5608
5609	u8 req_transport_retries_exceeded[0x20];
5610
5611	u8 cq_overflow[0x20];
5612
5613	u8 resp_cqe_flush_error[0x20];
5614
5615	u8 req_cqe_flush_error[0x20];
5616
5617	u8 reserved_at_620[0x20];
5618
5619	u8 roce_adp_retrans[0x20];
5620
5621	u8 roce_adp_retrans_to[0x20];
5622
5623	u8 roce_slow_restart[0x20];
5624
5625	u8 roce_slow_restart_cnps[0x20];
5626
5627	u8 roce_slow_restart_trans[0x20];
5628
5629	u8 reserved_at_6e0[0x120];
5630	};
5631
5632	struct mlx5_ifc_query_q_counter_in_bits {
5633	u8 opcode[0x10];
5634	u8 reserved_at_10[0x10];
5635
5636	u8 reserved_at_20[0x10];
5637	u8 op_mod[0x10];
5638
5639	u8 other_vport[0x1];
5640	u8 reserved_at_41[0xf];
5641	u8 vport_number[0x10];
5642
5643	u8 reserved_at_60[0x60];
5644
5645	u8 clear[0x1];
5646	u8 aggregate[0x1];
5647	u8 reserved_at_c2[0x1e];
5648
5649	u8 reserved_at_e0[0x18];
5650	u8 counter_set_id[0x8];
5651	};
5652
5653	struct mlx5_ifc_query_pages_out_bits {
5654	u8 status[0x8];
5655	u8 reserved_at_8[0x18];
5656
5657	u8 syndrome[0x20];
5658
5659	u8 embedded_cpu_function[0x1];
5660	u8 reserved_at_41[0xf];
5661	u8 function_id[0x10];
5662
5663	u8 num_pages[0x20];
5664	};
5665
5666	enum {
5667	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5668	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5669	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5670	};
5671
5672	struct mlx5_ifc_query_pages_in_bits {
5673	u8 opcode[0x10];
5674	u8 reserved_at_10[0x10];
5675
5676	u8 reserved_at_20[0x10];
5677	u8 op_mod[0x10];
5678
5679	u8 embedded_cpu_function[0x1];
5680	u8 reserved_at_41[0xf];
5681	u8 function_id[0x10];
5682
5683	u8 reserved_at_60[0x20];
5684	};
5685
5686	struct mlx5_ifc_query_nic_vport_context_out_bits {
5687	u8 status[0x8];
5688	u8 reserved_at_8[0x18];
5689
5690	u8 syndrome[0x20];
5691
5692	u8 reserved_at_40[0x40];
5693
5694	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5695	};
5696
5697	struct mlx5_ifc_query_nic_vport_context_in_bits {
5698	u8 opcode[0x10];
5699	u8 reserved_at_10[0x10];
5700
5701	u8 reserved_at_20[0x10];
5702	u8 op_mod[0x10];
5703
5704	u8 other_vport[0x1];
5705	u8 reserved_at_41[0xf];
5706	u8 vport_number[0x10];
5707
5708	u8 reserved_at_60[0x5];
5709	u8 allowed_list_type[0x3];
5710	u8 reserved_at_68[0x18];
5711	};
5712
5713	struct mlx5_ifc_query_mkey_out_bits {
5714	u8 status[0x8];
5715	u8 reserved_at_8[0x18];
5716
5717	u8 syndrome[0x20];
5718
5719	u8 reserved_at_40[0x40];
5720
5721	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5722
5723	u8 reserved_at_280[0x600];
5724
5725	u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5726
5727	u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5728	};
5729
5730	struct mlx5_ifc_query_mkey_in_bits {
5731	u8 opcode[0x10];
5732	u8 reserved_at_10[0x10];
5733
5734	u8 reserved_at_20[0x10];
5735	u8 op_mod[0x10];
5736
5737	u8 reserved_at_40[0x8];
5738	u8 mkey_index[0x18];
5739
5740	u8 pg_access[0x1];
5741	u8 reserved_at_61[0x1f];
5742	};
5743
5744	struct mlx5_ifc_query_mad_demux_out_bits {
5745	u8 status[0x8];
5746	u8 reserved_at_8[0x18];
5747
5748	u8 syndrome[0x20];
5749
5750	u8 reserved_at_40[0x40];
5751
5752	u8 mad_dumux_parameters_block[0x20];
5753	};
5754
5755	struct mlx5_ifc_query_mad_demux_in_bits {
5756	u8 opcode[0x10];
5757	u8 reserved_at_10[0x10];
5758
5759	u8 reserved_at_20[0x10];
5760	u8 op_mod[0x10];
5761
5762	u8 reserved_at_40[0x40];
5763	};
5764
5765	struct mlx5_ifc_query_l2_table_entry_out_bits {
5766	u8 status[0x8];
5767	u8 reserved_at_8[0x18];
5768
5769	u8 syndrome[0x20];
5770
5771	u8 reserved_at_40[0xa0];
5772
5773	u8 reserved_at_e0[0x13];
5774	u8 vlan_valid[0x1];
5775	u8 vlan[0xc];
5776
5777	struct mlx5_ifc_mac_address_layout_bits mac_address;
5778
5779	u8 reserved_at_140[0xc0];
5780	};
5781
5782	struct mlx5_ifc_query_l2_table_entry_in_bits {
5783	u8 opcode[0x10];
5784	u8 reserved_at_10[0x10];
5785
5786	u8 reserved_at_20[0x10];
5787	u8 op_mod[0x10];
5788
5789	u8 reserved_at_40[0x60];
5790
5791	u8 reserved_at_a0[0x8];
5792	u8 table_index[0x18];
5793
5794	u8 reserved_at_c0[0x140];
5795	};
5796
5797	struct mlx5_ifc_query_issi_out_bits {
5798	u8 status[0x8];
5799	u8 reserved_at_8[0x18];
5800
5801	u8 syndrome[0x20];
5802
5803	u8 reserved_at_40[0x10];
5804	u8 current_issi[0x10];
5805
5806	u8 reserved_at_60[0xa0];
5807
5808	u8 reserved_at_100[76][0x8];
5809	u8 supported_issi_dw0[0x20];
5810	};
5811
5812	struct mlx5_ifc_query_issi_in_bits {
5813	u8 opcode[0x10];
5814	u8 reserved_at_10[0x10];
5815
5816	u8 reserved_at_20[0x10];
5817	u8 op_mod[0x10];
5818
5819	u8 reserved_at_40[0x40];
5820	};
5821
5822	struct mlx5_ifc_set_driver_version_out_bits {
5823	u8 status[0x8];
5824	u8 reserved_0[0x18];
5825
5826	u8 syndrome[0x20];
5827	u8 reserved_1[0x40];
5828	};
5829
5830	struct mlx5_ifc_set_driver_version_in_bits {
5831	u8 opcode[0x10];
5832	u8 reserved_0[0x10];
5833
5834	u8 reserved_1[0x10];
5835	u8 op_mod[0x10];
5836
5837	u8 reserved_2[0x40];
5838	u8 driver_version[64][0x8];
5839	};
5840
5841	struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5842	u8 status[0x8];
5843	u8 reserved_at_8[0x18];
5844
5845	u8 syndrome[0x20];
5846
5847	u8 reserved_at_40[0x40];
5848
5849	struct mlx5_ifc_pkey_bits pkey[];
5850	};
5851
5852	struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5853	u8 opcode[0x10];
5854	u8 reserved_at_10[0x10];
5855
5856	u8 reserved_at_20[0x10];
5857	u8 op_mod[0x10];
5858
5859	u8 other_vport[0x1];
5860	u8 reserved_at_41[0xb];
5861	u8 port_num[0x4];
5862	u8 vport_number[0x10];
5863
5864	u8 reserved_at_60[0x10];
5865	u8 pkey_index[0x10];
5866	};
5867
5868	enum {
5869	MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5870	MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5871	MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5872	};
5873
5874	struct mlx5_ifc_query_hca_vport_gid_out_bits {
5875	u8 status[0x8];
5876	u8 reserved_at_8[0x18];
5877
5878	u8 syndrome[0x20];
5879
5880	u8 reserved_at_40[0x20];
5881
5882	u8 gids_num[0x10];
5883	u8 reserved_at_70[0x10];
5884
5885	struct mlx5_ifc_array128_auto_bits gid[];
5886	};
5887
5888	struct mlx5_ifc_query_hca_vport_gid_in_bits {
5889	u8 opcode[0x10];
5890	u8 reserved_at_10[0x10];
5891
5892	u8 reserved_at_20[0x10];
5893	u8 op_mod[0x10];
5894
5895	u8 other_vport[0x1];
5896	u8 reserved_at_41[0xb];
5897	u8 port_num[0x4];
5898	u8 vport_number[0x10];
5899
5900	u8 reserved_at_60[0x10];
5901	u8 gid_index[0x10];
5902	};
5903
5904	struct mlx5_ifc_query_hca_vport_context_out_bits {
5905	u8 status[0x8];
5906	u8 reserved_at_8[0x18];
5907
5908	u8 syndrome[0x20];
5909
5910	u8 reserved_at_40[0x40];
5911
5912	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5913	};
5914
5915	struct mlx5_ifc_query_hca_vport_context_in_bits {
5916	u8 opcode[0x10];
5917	u8 reserved_at_10[0x10];
5918
5919	u8 reserved_at_20[0x10];
5920	u8 op_mod[0x10];
5921
5922	u8 other_vport[0x1];
5923	u8 reserved_at_41[0xb];
5924	u8 port_num[0x4];
5925	u8 vport_number[0x10];
5926
5927	u8 reserved_at_60[0x20];
5928	};
5929
5930	struct mlx5_ifc_query_hca_cap_out_bits {
5931	u8 status[0x8];
5932	u8 reserved_at_8[0x18];
5933
5934	u8 syndrome[0x20];
5935
5936	u8 reserved_at_40[0x40];
5937
5938	union mlx5_ifc_hca_cap_union_bits capability;
5939	};
5940
5941	struct mlx5_ifc_query_hca_cap_in_bits {
5942	u8 opcode[0x10];
5943	u8 reserved_at_10[0x10];
5944
5945	u8 reserved_at_20[0x10];
5946	u8 op_mod[0x10];
5947
5948	u8 other_function[0x1];
5949	u8 ec_vf_function[0x1];
5950	u8 reserved_at_42[0xe];
5951	u8 function_id[0x10];
5952
5953	u8 reserved_at_60[0x20];
5954	};
5955
5956	struct mlx5_ifc_other_hca_cap_bits {
5957	u8 roce[0x1];
5958	u8 reserved_at_1[0x27f];
5959	};
5960
5961	struct mlx5_ifc_query_other_hca_cap_out_bits {
5962	u8 status[0x8];
5963	u8 reserved_at_8[0x18];
5964
5965	u8 syndrome[0x20];
5966
5967	u8 reserved_at_40[0x40];
5968
5969	struct mlx5_ifc_other_hca_cap_bits other_capability;
5970	};
5971
5972	struct mlx5_ifc_query_other_hca_cap_in_bits {
5973	u8 opcode[0x10];
5974	u8 reserved_at_10[0x10];
5975
5976	u8 reserved_at_20[0x10];
5977	u8 op_mod[0x10];
5978
5979	u8 reserved_at_40[0x10];
5980	u8 function_id[0x10];
5981
5982	u8 reserved_at_60[0x20];
5983	};
5984
5985	struct mlx5_ifc_modify_other_hca_cap_out_bits {
5986	u8 status[0x8];
5987	u8 reserved_at_8[0x18];
5988
5989	u8 syndrome[0x20];
5990
5991	u8 reserved_at_40[0x40];
5992	};
5993
5994	struct mlx5_ifc_modify_other_hca_cap_in_bits {
5995	u8 opcode[0x10];
5996	u8 reserved_at_10[0x10];
5997
5998	u8 reserved_at_20[0x10];
5999	u8 op_mod[0x10];
6000
6001	u8 reserved_at_40[0x10];
6002	u8 function_id[0x10];
6003	u8 field_select[0x20];
6004
6005	struct mlx5_ifc_other_hca_cap_bits other_capability;
6006	};
6007
6008	struct mlx5_ifc_flow_table_context_bits {
6009	u8 reformat_en[0x1];
6010	u8 decap_en[0x1];
6011	u8 sw_owner[0x1];
6012	u8 termination_table[0x1];
6013	u8 table_miss_action[0x4];
6014	u8 level[0x8];
6015	u8 reserved_at_10[0x8];
6016	u8 log_size[0x8];
6017
6018	u8 reserved_at_20[0x8];
6019	u8 table_miss_id[0x18];
6020
6021	u8 reserved_at_40[0x8];
6022	u8 lag_master_next_table_id[0x18];
6023
6024	u8 reserved_at_60[0x60];
6025
6026	u8 sw_owner_icm_root_1[0x40];
6027
6028	u8 sw_owner_icm_root_0[0x40];
6029
6030	};
6031
6032	struct mlx5_ifc_query_flow_table_out_bits {
6033	u8 status[0x8];
6034	u8 reserved_at_8[0x18];
6035
6036	u8 syndrome[0x20];
6037
6038	u8 reserved_at_40[0x80];
6039
6040	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6041	};
6042
6043	struct mlx5_ifc_query_flow_table_in_bits {
6044	u8 opcode[0x10];
6045	u8 reserved_at_10[0x10];
6046
6047	u8 reserved_at_20[0x10];
6048	u8 op_mod[0x10];
6049
6050	u8 reserved_at_40[0x40];
6051
6052	u8 table_type[0x8];
6053	u8 reserved_at_88[0x18];
6054
6055	u8 reserved_at_a0[0x8];
6056	u8 table_id[0x18];
6057
6058	u8 reserved_at_c0[0x140];
6059	};
6060
6061	struct mlx5_ifc_query_fte_out_bits {
6062	u8 status[0x8];
6063	u8 reserved_at_8[0x18];
6064
6065	u8 syndrome[0x20];
6066
6067	u8 reserved_at_40[0x1c0];
6068
6069	struct mlx5_ifc_flow_context_bits flow_context;
6070	};
6071
6072	struct mlx5_ifc_query_fte_in_bits {
6073	u8 opcode[0x10];
6074	u8 reserved_at_10[0x10];
6075
6076	u8 reserved_at_20[0x10];
6077	u8 op_mod[0x10];
6078
6079	u8 reserved_at_40[0x40];
6080
6081	u8 table_type[0x8];
6082	u8 reserved_at_88[0x18];
6083
6084	u8 reserved_at_a0[0x8];
6085	u8 table_id[0x18];
6086
6087	u8 reserved_at_c0[0x40];
6088
6089	u8 flow_index[0x20];
6090
6091	u8 reserved_at_120[0xe0];
6092	};
6093
6094	struct mlx5_ifc_match_definer_format_0_bits {
6095	u8 reserved_at_0[0x100];
6096
6097	u8 metadata_reg_c_0[0x20];
6098
6099	u8 metadata_reg_c_1[0x20];
6100
6101	u8 outer_dmac_47_16[0x20];
6102
6103	u8 outer_dmac_15_0[0x10];
6104	u8 outer_ethertype[0x10];
6105
6106	u8 reserved_at_180[0x1];
6107	u8 sx_sniffer[0x1];
6108	u8 functional_lb[0x1];
6109	u8 outer_ip_frag[0x1];
6110	u8 outer_qp_type[0x2];
6111	u8 outer_encap_type[0x2];
6112	u8 port_number[0x2];
6113	u8 outer_l3_type[0x2];
6114	u8 outer_l4_type[0x2];
6115	u8 outer_first_vlan_type[0x2];
6116	u8 outer_first_vlan_prio[0x3];
6117	u8 outer_first_vlan_cfi[0x1];
6118	u8 outer_first_vlan_vid[0xc];
6119
6120	u8 outer_l4_type_ext[0x4];
6121	u8 reserved_at_1a4[0x2];
6122	u8 outer_ipsec_layer[0x2];
6123	u8 outer_l2_type[0x2];
6124	u8 force_lb[0x1];
6125	u8 outer_l2_ok[0x1];
6126	u8 outer_l3_ok[0x1];
6127	u8 outer_l4_ok[0x1];
6128	u8 outer_second_vlan_type[0x2];
6129	u8 outer_second_vlan_prio[0x3];
6130	u8 outer_second_vlan_cfi[0x1];
6131	u8 outer_second_vlan_vid[0xc];
6132
6133	u8 outer_smac_47_16[0x20];
6134
6135	u8 outer_smac_15_0[0x10];
6136	u8 inner_ipv4_checksum_ok[0x1];
6137	u8 inner_l4_checksum_ok[0x1];
6138	u8 outer_ipv4_checksum_ok[0x1];
6139	u8 outer_l4_checksum_ok[0x1];
6140	u8 inner_l3_ok[0x1];
6141	u8 inner_l4_ok[0x1];
6142	u8 outer_l3_ok_duplicate[0x1];
6143	u8 outer_l4_ok_duplicate[0x1];
6144	u8 outer_tcp_cwr[0x1];
6145	u8 outer_tcp_ece[0x1];
6146	u8 outer_tcp_urg[0x1];
6147	u8 outer_tcp_ack[0x1];
6148	u8 outer_tcp_psh[0x1];
6149	u8 outer_tcp_rst[0x1];
6150	u8 outer_tcp_syn[0x1];
6151	u8 outer_tcp_fin[0x1];
6152	};
6153
6154	struct mlx5_ifc_match_definer_format_22_bits {
6155	u8 reserved_at_0[0x100];
6156
6157	u8 outer_ip_src_addr[0x20];
6158
6159	u8 outer_ip_dest_addr[0x20];
6160
6161	u8 outer_l4_sport[0x10];
6162	u8 outer_l4_dport[0x10];
6163
6164	u8 reserved_at_160[0x1];
6165	u8 sx_sniffer[0x1];
6166	u8 functional_lb[0x1];
6167	u8 outer_ip_frag[0x1];
6168	u8 outer_qp_type[0x2];
6169	u8 outer_encap_type[0x2];
6170	u8 port_number[0x2];
6171	u8 outer_l3_type[0x2];
6172	u8 outer_l4_type[0x2];
6173	u8 outer_first_vlan_type[0x2];
6174	u8 outer_first_vlan_prio[0x3];
6175	u8 outer_first_vlan_cfi[0x1];
6176	u8 outer_first_vlan_vid[0xc];
6177
6178	u8 metadata_reg_c_0[0x20];
6179
6180	u8 outer_dmac_47_16[0x20];
6181
6182	u8 outer_smac_47_16[0x20];
6183
6184	u8 outer_smac_15_0[0x10];
6185	u8 outer_dmac_15_0[0x10];
6186	};
6187
6188	struct mlx5_ifc_match_definer_format_23_bits {
6189	u8 reserved_at_0[0x100];
6190
6191	u8 inner_ip_src_addr[0x20];
6192
6193	u8 inner_ip_dest_addr[0x20];
6194
6195	u8 inner_l4_sport[0x10];
6196	u8 inner_l4_dport[0x10];
6197
6198	u8 reserved_at_160[0x1];
6199	u8 sx_sniffer[0x1];
6200	u8 functional_lb[0x1];
6201	u8 inner_ip_frag[0x1];
6202	u8 inner_qp_type[0x2];
6203	u8 inner_encap_type[0x2];
6204	u8 port_number[0x2];
6205	u8 inner_l3_type[0x2];
6206	u8 inner_l4_type[0x2];
6207	u8 inner_first_vlan_type[0x2];
6208	u8 inner_first_vlan_prio[0x3];
6209	u8 inner_first_vlan_cfi[0x1];
6210	u8 inner_first_vlan_vid[0xc];
6211
6212	u8 tunnel_header_0[0x20];
6213
6214	u8 inner_dmac_47_16[0x20];
6215
6216	u8 inner_smac_47_16[0x20];
6217
6218	u8 inner_smac_15_0[0x10];
6219	u8 inner_dmac_15_0[0x10];
6220	};
6221
6222	struct mlx5_ifc_match_definer_format_29_bits {
6223	u8 reserved_at_0[0xc0];
6224
6225	u8 outer_ip_dest_addr[0x80];
6226
6227	u8 outer_ip_src_addr[0x80];
6228
6229	u8 outer_l4_sport[0x10];
6230	u8 outer_l4_dport[0x10];
6231
6232	u8 reserved_at_1e0[0x20];
6233	};
6234
6235	struct mlx5_ifc_match_definer_format_30_bits {
6236	u8 reserved_at_0[0xa0];
6237
6238	u8 outer_ip_dest_addr[0x80];
6239
6240	u8 outer_ip_src_addr[0x80];
6241
6242	u8 outer_dmac_47_16[0x20];
6243
6244	u8 outer_smac_47_16[0x20];
6245
6246	u8 outer_smac_15_0[0x10];
6247	u8 outer_dmac_15_0[0x10];
6248	};
6249
6250	struct mlx5_ifc_match_definer_format_31_bits {
6251	u8 reserved_at_0[0xc0];
6252
6253	u8 inner_ip_dest_addr[0x80];
6254
6255	u8 inner_ip_src_addr[0x80];
6256
6257	u8 inner_l4_sport[0x10];
6258	u8 inner_l4_dport[0x10];
6259
6260	u8 reserved_at_1e0[0x20];
6261	};
6262
6263	struct mlx5_ifc_match_definer_format_32_bits {
6264	u8 reserved_at_0[0xa0];
6265
6266	u8 inner_ip_dest_addr[0x80];
6267
6268	u8 inner_ip_src_addr[0x80];
6269
6270	u8 inner_dmac_47_16[0x20];
6271
6272	u8 inner_smac_47_16[0x20];
6273
6274	u8 inner_smac_15_0[0x10];
6275	u8 inner_dmac_15_0[0x10];
6276	};
6277
6278	enum {
6279	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6280	};
6281
6282	#define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6283	#define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6284	#define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6285	#define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6286
6287	struct mlx5_ifc_match_definer_match_mask_bits {
6288	u8 reserved_at_1c0[5][0x20];
6289	u8 match_dw_8[0x20];
6290	u8 match_dw_7[0x20];
6291	u8 match_dw_6[0x20];
6292	u8 match_dw_5[0x20];
6293	u8 match_dw_4[0x20];
6294	u8 match_dw_3[0x20];
6295	u8 match_dw_2[0x20];
6296	u8 match_dw_1[0x20];
6297	u8 match_dw_0[0x20];
6298
6299	u8 match_byte_7[0x8];
6300	u8 match_byte_6[0x8];
6301	u8 match_byte_5[0x8];
6302	u8 match_byte_4[0x8];
6303
6304	u8 match_byte_3[0x8];
6305	u8 match_byte_2[0x8];
6306	u8 match_byte_1[0x8];
6307	u8 match_byte_0[0x8];
6308	};
6309
6310	struct mlx5_ifc_match_definer_bits {
6311	u8 modify_field_select[0x40];
6312
6313	u8 reserved_at_40[0x40];
6314
6315	u8 reserved_at_80[0x10];
6316	u8 format_id[0x10];
6317
6318	u8 reserved_at_a0[0x60];
6319
6320	u8 format_select_dw3[0x8];
6321	u8 format_select_dw2[0x8];
6322	u8 format_select_dw1[0x8];
6323	u8 format_select_dw0[0x8];
6324
6325	u8 format_select_dw7[0x8];
6326	u8 format_select_dw6[0x8];
6327	u8 format_select_dw5[0x8];
6328	u8 format_select_dw4[0x8];
6329
6330	u8 reserved_at_100[0x18];
6331	u8 format_select_dw8[0x8];
6332
6333	u8 reserved_at_120[0x20];
6334
6335	u8 format_select_byte3[0x8];
6336	u8 format_select_byte2[0x8];
6337	u8 format_select_byte1[0x8];
6338	u8 format_select_byte0[0x8];
6339
6340	u8 format_select_byte7[0x8];
6341	u8 format_select_byte6[0x8];
6342	u8 format_select_byte5[0x8];
6343	u8 format_select_byte4[0x8];
6344
6345	u8 reserved_at_180[0x40];
6346
6347	union {
6348	struct {
6349	u8 match_mask[16][0x20];
6350	};
6351	struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6352	};
6353	};
6354
6355	struct mlx5_ifc_general_obj_create_param_bits {
6356	u8 alias_object[0x1];
6357	u8 reserved_at_1[0x2];
6358	u8 log_obj_range[0x5];
6359	u8 reserved_at_8[0x18];
6360	};
6361
6362	struct mlx5_ifc_general_obj_query_param_bits {
6363	u8 alias_object[0x1];
6364	u8 obj_offset[0x1f];
6365	};
6366
6367	struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6368	u8 opcode[0x10];
6369	u8 uid[0x10];
6370
6371	u8 vhca_tunnel_id[0x10];
6372	u8 obj_type[0x10];
6373
6374	u8 obj_id[0x20];
6375
6376	union {
6377	struct mlx5_ifc_general_obj_create_param_bits create;
6378	struct mlx5_ifc_general_obj_query_param_bits query;
6379	} op_param;
6380	};
6381
6382	struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6383	u8 status[0x8];
6384	u8 reserved_at_8[0x18];
6385
6386	u8 syndrome[0x20];
6387
6388	u8 obj_id[0x20];
6389
6390	u8 reserved_at_60[0x20];
6391	};
6392
6393	struct mlx5_ifc_allow_other_vhca_access_in_bits {
6394	u8 opcode[0x10];
6395	u8 uid[0x10];
6396	u8 reserved_at_20[0x10];
6397	u8 op_mod[0x10];
6398	u8 reserved_at_40[0x50];
6399	u8 object_type_to_be_accessed[0x10];
6400	u8 object_id_to_be_accessed[0x20];
6401	u8 reserved_at_c0[0x40];
6402	union {
6403	u8 access_key_raw[0x100];
6404	u8 access_key[8][0x20];
6405	};
6406	};
6407
6408	struct mlx5_ifc_allow_other_vhca_access_out_bits {
6409	u8 status[0x8];
6410	u8 reserved_at_8[0x18];
6411	u8 syndrome[0x20];
6412	u8 reserved_at_40[0x40];
6413	};
6414
6415	struct mlx5_ifc_modify_header_arg_bits {
6416	u8 reserved_at_0[0x80];
6417
6418	u8 reserved_at_80[0x8];
6419	u8 access_pd[0x18];
6420	};
6421
6422	struct mlx5_ifc_create_modify_header_arg_in_bits {
6423	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6424	struct mlx5_ifc_modify_header_arg_bits arg;
6425	};
6426
6427	struct mlx5_ifc_create_match_definer_in_bits {
6428	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6429
6430	struct mlx5_ifc_match_definer_bits obj_context;
6431	};
6432
6433	struct mlx5_ifc_create_match_definer_out_bits {
6434	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6435	};
6436
6437	struct mlx5_ifc_alias_context_bits {
6438	u8 vhca_id_to_be_accessed[0x10];
6439	u8 reserved_at_10[0xd];
6440	u8 status[0x3];
6441	u8 object_id_to_be_accessed[0x20];
6442	u8 reserved_at_40[0x40];
6443	union {
6444	u8 access_key_raw[0x100];
6445	u8 access_key[8][0x20];
6446	};
6447	u8 metadata[0x80];
6448	};
6449
6450	struct mlx5_ifc_create_alias_obj_in_bits {
6451	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6452	struct mlx5_ifc_alias_context_bits alias_ctx;
6453	};
6454
6455	enum {
6456	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6457	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6458	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6459	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6460	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6461	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6462	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6463	};
6464
6465	struct mlx5_ifc_query_flow_group_out_bits {
6466	u8 status[0x8];
6467	u8 reserved_at_8[0x18];
6468
6469	u8 syndrome[0x20];
6470
6471	u8 reserved_at_40[0xa0];
6472
6473	u8 start_flow_index[0x20];
6474
6475	u8 reserved_at_100[0x20];
6476
6477	u8 end_flow_index[0x20];
6478
6479	u8 reserved_at_140[0xa0];
6480
6481	u8 reserved_at_1e0[0x18];
6482	u8 match_criteria_enable[0x8];
6483
6484	struct mlx5_ifc_fte_match_param_bits match_criteria;
6485
6486	u8 reserved_at_1200[0xe00];
6487	};
6488
6489	struct mlx5_ifc_query_flow_group_in_bits {
6490	u8 opcode[0x10];
6491	u8 reserved_at_10[0x10];
6492
6493	u8 reserved_at_20[0x10];
6494	u8 op_mod[0x10];
6495
6496	u8 reserved_at_40[0x40];
6497
6498	u8 table_type[0x8];
6499	u8 reserved_at_88[0x18];
6500
6501	u8 reserved_at_a0[0x8];
6502	u8 table_id[0x18];
6503
6504	u8 group_id[0x20];
6505
6506	u8 reserved_at_e0[0x120];
6507	};
6508
6509	struct mlx5_ifc_query_flow_counter_out_bits {
6510	u8 status[0x8];
6511	u8 reserved_at_8[0x18];
6512
6513	u8 syndrome[0x20];
6514
6515	u8 reserved_at_40[0x40];
6516
6517	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6518	};
6519
6520	struct mlx5_ifc_query_flow_counter_in_bits {
6521	u8 opcode[0x10];
6522	u8 reserved_at_10[0x10];
6523
6524	u8 reserved_at_20[0x10];
6525	u8 op_mod[0x10];
6526
6527	u8 reserved_at_40[0x80];
6528
6529	u8 clear[0x1];
6530	u8 reserved_at_c1[0xf];
6531	u8 num_of_counters[0x10];
6532
6533	u8 flow_counter_id[0x20];
6534	};
6535
6536	struct mlx5_ifc_query_esw_vport_context_out_bits {
6537	u8 status[0x8];
6538	u8 reserved_at_8[0x18];
6539
6540	u8 syndrome[0x20];
6541
6542	u8 reserved_at_40[0x40];
6543
6544	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6545	};
6546
6547	struct mlx5_ifc_query_esw_vport_context_in_bits {
6548	u8 opcode[0x10];
6549	u8 reserved_at_10[0x10];
6550
6551	u8 reserved_at_20[0x10];
6552	u8 op_mod[0x10];
6553
6554	u8 other_vport[0x1];
6555	u8 reserved_at_41[0xf];
6556	u8 vport_number[0x10];
6557
6558	u8 reserved_at_60[0x20];
6559	};
6560
6561	struct mlx5_ifc_modify_esw_vport_context_out_bits {
6562	u8 status[0x8];
6563	u8 reserved_at_8[0x18];
6564
6565	u8 syndrome[0x20];
6566
6567	u8 reserved_at_40[0x40];
6568	};
6569
6570	struct mlx5_ifc_esw_vport_context_fields_select_bits {
6571	u8 reserved_at_0[0x1b];
6572	u8 fdb_to_vport_reg_c_id[0x1];
6573	u8 vport_cvlan_insert[0x1];
6574	u8 vport_svlan_insert[0x1];
6575	u8 vport_cvlan_strip[0x1];
6576	u8 vport_svlan_strip[0x1];
6577	};
6578
6579	struct mlx5_ifc_modify_esw_vport_context_in_bits {
6580	u8 opcode[0x10];
6581	u8 reserved_at_10[0x10];
6582
6583	u8 reserved_at_20[0x10];
6584	u8 op_mod[0x10];
6585
6586	u8 other_vport[0x1];
6587	u8 reserved_at_41[0xf];
6588	u8 vport_number[0x10];
6589
6590	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6591
6592	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6593	};
6594
6595	struct mlx5_ifc_query_eq_out_bits {
6596	u8 status[0x8];
6597	u8 reserved_at_8[0x18];
6598
6599	u8 syndrome[0x20];
6600
6601	u8 reserved_at_40[0x40];
6602
6603	struct mlx5_ifc_eqc_bits eq_context_entry;
6604
6605	u8 reserved_at_280[0x40];
6606
6607	u8 event_bitmask[0x40];
6608
6609	u8 reserved_at_300[0x580];
6610
6611	u8 pas[][0x40];
6612	};
6613
6614	struct mlx5_ifc_query_eq_in_bits {
6615	u8 opcode[0x10];
6616	u8 reserved_at_10[0x10];
6617
6618	u8 reserved_at_20[0x10];
6619	u8 op_mod[0x10];
6620
6621	u8 reserved_at_40[0x18];
6622	u8 eq_number[0x8];
6623
6624	u8 reserved_at_60[0x20];
6625	};
6626
6627	struct mlx5_ifc_packet_reformat_context_in_bits {
6628	u8 reformat_type[0x8];
6629	u8 reserved_at_8[0x4];
6630	u8 reformat_param_0[0x4];
6631	u8 reserved_at_10[0x6];
6632	u8 reformat_data_size[0xa];
6633
6634	u8 reformat_param_1[0x8];
6635	u8 reserved_at_28[0x8];
6636	u8 reformat_data[2][0x8];
6637
6638	u8 more_reformat_data[][0x8];
6639	};
6640
6641	struct mlx5_ifc_query_packet_reformat_context_out_bits {
6642	u8 status[0x8];
6643	u8 reserved_at_8[0x18];
6644
6645	u8 syndrome[0x20];
6646
6647	u8 reserved_at_40[0xa0];
6648
6649	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6650	};
6651
6652	struct mlx5_ifc_query_packet_reformat_context_in_bits {
6653	u8 opcode[0x10];
6654	u8 reserved_at_10[0x10];
6655
6656	u8 reserved_at_20[0x10];
6657	u8 op_mod[0x10];
6658
6659	u8 packet_reformat_id[0x20];
6660
6661	u8 reserved_at_60[0xa0];
6662	};
6663
6664	struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6665	u8 status[0x8];
6666	u8 reserved_at_8[0x18];
6667
6668	u8 syndrome[0x20];
6669
6670	u8 packet_reformat_id[0x20];
6671
6672	u8 reserved_at_60[0x20];
6673	};
6674
6675	enum {
6676	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6677	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6678	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6679	};
6680
6681	enum mlx5_reformat_ctx_type {
6682	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6683	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6684	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6685	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6686	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6687	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6688	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6689	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6690	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6691	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6692	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6693	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6694	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6695	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6696	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6697	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6698	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6699	};
6700
6701	struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6702	u8 opcode[0x10];
6703	u8 reserved_at_10[0x10];
6704
6705	u8 reserved_at_20[0x10];
6706	u8 op_mod[0x10];
6707
6708	u8 reserved_at_40[0xa0];
6709
6710	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6711	};
6712
6713	struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6714	u8 status[0x8];
6715	u8 reserved_at_8[0x18];
6716
6717	u8 syndrome[0x20];
6718
6719	u8 reserved_at_40[0x40];
6720	};
6721
6722	struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6723	u8 opcode[0x10];
6724	u8 reserved_at_10[0x10];
6725
6726	u8 reserved_20[0x10];
6727	u8 op_mod[0x10];
6728
6729	u8 packet_reformat_id[0x20];
6730
6731	u8 reserved_60[0x20];
6732	};
6733
6734	struct mlx5_ifc_set_action_in_bits {
6735	u8 action_type[0x4];
6736	u8 field[0xc];
6737	u8 reserved_at_10[0x3];
6738	u8 offset[0x5];
6739	u8 reserved_at_18[0x3];
6740	u8 length[0x5];
6741
6742	u8 data[0x20];
6743	};
6744
6745	struct mlx5_ifc_add_action_in_bits {
6746	u8 action_type[0x4];
6747	u8 field[0xc];
6748	u8 reserved_at_10[0x10];
6749
6750	u8 data[0x20];
6751	};
6752
6753	struct mlx5_ifc_copy_action_in_bits {
6754	u8 action_type[0x4];
6755	u8 src_field[0xc];
6756	u8 reserved_at_10[0x3];
6757	u8 src_offset[0x5];
6758	u8 reserved_at_18[0x3];
6759	u8 length[0x5];
6760
6761	u8 reserved_at_20[0x4];
6762	u8 dst_field[0xc];
6763	u8 reserved_at_30[0x3];
6764	u8 dst_offset[0x5];
6765	u8 reserved_at_38[0x8];
6766	};
6767
6768	union mlx5_ifc_set_add_copy_action_in_auto_bits {
6769	struct mlx5_ifc_set_action_in_bits set_action_in;
6770	struct mlx5_ifc_add_action_in_bits add_action_in;
6771	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6772	u8 reserved_at_0[0x40];
6773	};
6774
6775	enum {
6776	MLX5_ACTION_TYPE_SET = 0x1,
6777	MLX5_ACTION_TYPE_ADD = 0x2,
6778	MLX5_ACTION_TYPE_COPY = 0x3,
6779	};
6780
6781	enum {
6782	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6783	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6784	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6785	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6786	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6787	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6788	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6789	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6790	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6791	MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6792	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6793	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6794	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6795	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6796	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6797	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6798	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6799	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6800	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6801	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6802	MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6803	MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
6804	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
6805	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6806	MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6807	MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
6808	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
6809	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6810	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6811	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6812	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6813	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
6814	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6815	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
6816	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6817	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
6818	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
6819	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6820	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
6821	};
6822
6823	struct mlx5_ifc_alloc_modify_header_context_out_bits {
6824	u8 status[0x8];
6825	u8 reserved_at_8[0x18];
6826
6827	u8 syndrome[0x20];
6828
6829	u8 modify_header_id[0x20];
6830
6831	u8 reserved_at_60[0x20];
6832	};
6833
6834	struct mlx5_ifc_alloc_modify_header_context_in_bits {
6835	u8 opcode[0x10];
6836	u8 reserved_at_10[0x10];
6837
6838	u8 reserved_at_20[0x10];
6839	u8 op_mod[0x10];
6840
6841	u8 reserved_at_40[0x20];
6842
6843	u8 table_type[0x8];
6844	u8 reserved_at_68[0x10];
6845	u8 num_of_actions[0x8];
6846
6847	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6848	};
6849
6850	struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6851	u8 status[0x8];
6852	u8 reserved_at_8[0x18];
6853
6854	u8 syndrome[0x20];
6855
6856	u8 reserved_at_40[0x40];
6857	};
6858
6859	struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6860	u8 opcode[0x10];
6861	u8 reserved_at_10[0x10];
6862
6863	u8 reserved_at_20[0x10];
6864	u8 op_mod[0x10];
6865
6866	u8 modify_header_id[0x20];
6867
6868	u8 reserved_at_60[0x20];
6869	};
6870
6871	struct mlx5_ifc_query_modify_header_context_in_bits {
6872	u8 opcode[0x10];
6873	u8 uid[0x10];
6874
6875	u8 reserved_at_20[0x10];
6876	u8 op_mod[0x10];
6877
6878	u8 modify_header_id[0x20];
6879
6880	u8 reserved_at_60[0xa0];
6881	};
6882
6883	struct mlx5_ifc_query_dct_out_bits {
6884	u8 status[0x8];
6885	u8 reserved_at_8[0x18];
6886
6887	u8 syndrome[0x20];
6888
6889	u8 reserved_at_40[0x40];
6890
6891	struct mlx5_ifc_dctc_bits dct_context_entry;
6892
6893	u8 reserved_at_280[0x180];
6894	};
6895
6896	struct mlx5_ifc_query_dct_in_bits {
6897	u8 opcode[0x10];
6898	u8 reserved_at_10[0x10];
6899
6900	u8 reserved_at_20[0x10];
6901	u8 op_mod[0x10];
6902
6903	u8 reserved_at_40[0x8];
6904	u8 dctn[0x18];
6905
6906	u8 reserved_at_60[0x20];
6907	};
6908
6909	struct mlx5_ifc_query_cq_out_bits {
6910	u8 status[0x8];
6911	u8 reserved_at_8[0x18];
6912
6913	u8 syndrome[0x20];
6914
6915	u8 reserved_at_40[0x40];
6916
6917	struct mlx5_ifc_cqc_bits cq_context;
6918
6919	u8 reserved_at_280[0x600];
6920
6921	u8 pas[][0x40];
6922	};
6923
6924	struct mlx5_ifc_query_cq_in_bits {
6925	u8 opcode[0x10];
6926	u8 reserved_at_10[0x10];
6927
6928	u8 reserved_at_20[0x10];
6929	u8 op_mod[0x10];
6930
6931	u8 reserved_at_40[0x8];
6932	u8 cqn[0x18];
6933
6934	u8 reserved_at_60[0x20];
6935	};
6936
6937	struct mlx5_ifc_query_cong_status_out_bits {
6938	u8 status[0x8];
6939	u8 reserved_at_8[0x18];
6940
6941	u8 syndrome[0x20];
6942
6943	u8 reserved_at_40[0x20];
6944
6945	u8 enable[0x1];
6946	u8 tag_enable[0x1];
6947	u8 reserved_at_62[0x1e];
6948	};
6949
6950	struct mlx5_ifc_query_cong_status_in_bits {
6951	u8 opcode[0x10];
6952	u8 reserved_at_10[0x10];
6953
6954	u8 reserved_at_20[0x10];
6955	u8 op_mod[0x10];
6956
6957	u8 reserved_at_40[0x18];
6958	u8 priority[0x4];
6959	u8 cong_protocol[0x4];
6960
6961	u8 reserved_at_60[0x20];
6962	};
6963
6964	struct mlx5_ifc_query_cong_statistics_out_bits {
6965	u8 status[0x8];
6966	u8 reserved_at_8[0x18];
6967
6968	u8 syndrome[0x20];
6969
6970	u8 reserved_at_40[0x40];
6971
6972	u8 rp_cur_flows[0x20];
6973
6974	u8 sum_flows[0x20];
6975
6976	u8 rp_cnp_ignored_high[0x20];
6977
6978	u8 rp_cnp_ignored_low[0x20];
6979
6980	u8 rp_cnp_handled_high[0x20];
6981
6982	u8 rp_cnp_handled_low[0x20];
6983
6984	u8 reserved_at_140[0x100];
6985
6986	u8 time_stamp_high[0x20];
6987
6988	u8 time_stamp_low[0x20];
6989
6990	u8 accumulators_period[0x20];
6991
6992	u8 np_ecn_marked_roce_packets_high[0x20];
6993
6994	u8 np_ecn_marked_roce_packets_low[0x20];
6995
6996	u8 np_cnp_sent_high[0x20];
6997
6998	u8 np_cnp_sent_low[0x20];
6999
7000	u8 reserved_at_320[0x560];
7001	};
7002
7003	struct mlx5_ifc_query_cong_statistics_in_bits {
7004	u8 opcode[0x10];
7005	u8 reserved_at_10[0x10];
7006
7007	u8 reserved_at_20[0x10];
7008	u8 op_mod[0x10];
7009
7010	u8 clear[0x1];
7011	u8 reserved_at_41[0x1f];
7012
7013	u8 reserved_at_60[0x20];
7014	};
7015
7016	struct mlx5_ifc_query_cong_params_out_bits {
7017	u8 status[0x8];
7018	u8 reserved_at_8[0x18];
7019
7020	u8 syndrome[0x20];
7021
7022	u8 reserved_at_40[0x40];
7023
7024	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7025	};
7026
7027	struct mlx5_ifc_query_cong_params_in_bits {
7028	u8 opcode[0x10];
7029	u8 reserved_at_10[0x10];
7030
7031	u8 reserved_at_20[0x10];
7032	u8 op_mod[0x10];
7033
7034	u8 reserved_at_40[0x1c];
7035	u8 cong_protocol[0x4];
7036
7037	u8 reserved_at_60[0x20];
7038	};
7039
7040	struct mlx5_ifc_query_adapter_out_bits {
7041	u8 status[0x8];
7042	u8 reserved_at_8[0x18];
7043
7044	u8 syndrome[0x20];
7045
7046	u8 reserved_at_40[0x40];
7047
7048	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7049	};
7050
7051	struct mlx5_ifc_query_adapter_in_bits {
7052	u8 opcode[0x10];
7053	u8 reserved_at_10[0x10];
7054
7055	u8 reserved_at_20[0x10];
7056	u8 op_mod[0x10];
7057
7058	u8 reserved_at_40[0x40];
7059	};
7060
7061	struct mlx5_ifc_qp_2rst_out_bits {
7062	u8 status[0x8];
7063	u8 reserved_at_8[0x18];
7064
7065	u8 syndrome[0x20];
7066
7067	u8 reserved_at_40[0x40];
7068	};
7069
7070	struct mlx5_ifc_qp_2rst_in_bits {
7071	u8 opcode[0x10];
7072	u8 uid[0x10];
7073
7074	u8 reserved_at_20[0x10];
7075	u8 op_mod[0x10];
7076
7077	u8 reserved_at_40[0x8];
7078	u8 qpn[0x18];
7079
7080	u8 reserved_at_60[0x20];
7081	};
7082
7083	struct mlx5_ifc_qp_2err_out_bits {
7084	u8 status[0x8];
7085	u8 reserved_at_8[0x18];
7086
7087	u8 syndrome[0x20];
7088
7089	u8 reserved_at_40[0x40];
7090	};
7091
7092	struct mlx5_ifc_qp_2err_in_bits {
7093	u8 opcode[0x10];
7094	u8 uid[0x10];
7095
7096	u8 reserved_at_20[0x10];
7097	u8 op_mod[0x10];
7098
7099	u8 reserved_at_40[0x8];
7100	u8 qpn[0x18];
7101
7102	u8 reserved_at_60[0x20];
7103	};
7104
7105	struct mlx5_ifc_page_fault_resume_out_bits {
7106	u8 status[0x8];
7107	u8 reserved_at_8[0x18];
7108
7109	u8 syndrome[0x20];
7110
7111	u8 reserved_at_40[0x40];
7112	};
7113
7114	struct mlx5_ifc_page_fault_resume_in_bits {
7115	u8 opcode[0x10];
7116	u8 reserved_at_10[0x10];
7117
7118	u8 reserved_at_20[0x10];
7119	u8 op_mod[0x10];
7120
7121	u8 error[0x1];
7122	u8 reserved_at_41[0x4];
7123	u8 page_fault_type[0x3];
7124	u8 wq_number[0x18];
7125
7126	u8 reserved_at_60[0x8];
7127	u8 token[0x18];
7128	};
7129
7130	struct mlx5_ifc_nop_out_bits {
7131	u8 status[0x8];
7132	u8 reserved_at_8[0x18];
7133
7134	u8 syndrome[0x20];
7135
7136	u8 reserved_at_40[0x40];
7137	};
7138
7139	struct mlx5_ifc_nop_in_bits {
7140	u8 opcode[0x10];
7141	u8 reserved_at_10[0x10];
7142
7143	u8 reserved_at_20[0x10];
7144	u8 op_mod[0x10];
7145
7146	u8 reserved_at_40[0x40];
7147	};
7148
7149	struct mlx5_ifc_modify_vport_state_out_bits {
7150	u8 status[0x8];
7151	u8 reserved_at_8[0x18];
7152
7153	u8 syndrome[0x20];
7154
7155	u8 reserved_at_40[0x40];
7156	};
7157
7158	struct mlx5_ifc_modify_vport_state_in_bits {
7159	u8 opcode[0x10];
7160	u8 reserved_at_10[0x10];
7161
7162	u8 reserved_at_20[0x10];
7163	u8 op_mod[0x10];
7164
7165	u8 other_vport[0x1];
7166	u8 reserved_at_41[0xf];
7167	u8 vport_number[0x10];
7168
7169	u8 reserved_at_60[0x18];
7170	u8 admin_state[0x4];
7171	u8 reserved_at_7c[0x4];
7172	};
7173
7174	struct mlx5_ifc_modify_tis_out_bits {
7175	u8 status[0x8];
7176	u8 reserved_at_8[0x18];
7177
7178	u8 syndrome[0x20];
7179
7180	u8 reserved_at_40[0x40];
7181	};
7182
7183	struct mlx5_ifc_modify_tis_bitmask_bits {
7184	u8 reserved_at_0[0x20];
7185
7186	u8 reserved_at_20[0x1d];
7187	u8 lag_tx_port_affinity[0x1];
7188	u8 strict_lag_tx_port_affinity[0x1];
7189	u8 prio[0x1];
7190	};
7191
7192	struct mlx5_ifc_modify_tis_in_bits {
7193	u8 opcode[0x10];
7194	u8 uid[0x10];
7195
7196	u8 reserved_at_20[0x10];
7197	u8 op_mod[0x10];
7198
7199	u8 reserved_at_40[0x8];
7200	u8 tisn[0x18];
7201
7202	u8 reserved_at_60[0x20];
7203
7204	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7205
7206	u8 reserved_at_c0[0x40];
7207
7208	struct mlx5_ifc_tisc_bits ctx;
7209	};
7210
7211	struct mlx5_ifc_modify_tir_bitmask_bits {
7212	u8 reserved_at_0[0x20];
7213
7214	u8 reserved_at_20[0x1b];
7215	u8 self_lb_en[0x1];
7216	u8 reserved_at_3c[0x1];
7217	u8 hash[0x1];
7218	u8 reserved_at_3e[0x1];
7219	u8 packet_merge[0x1];
7220	};
7221
7222	struct mlx5_ifc_modify_tir_out_bits {
7223	u8 status[0x8];
7224	u8 reserved_at_8[0x18];
7225
7226	u8 syndrome[0x20];
7227
7228	u8 reserved_at_40[0x40];
7229	};
7230
7231	struct mlx5_ifc_modify_tir_in_bits {
7232	u8 opcode[0x10];
7233	u8 uid[0x10];
7234
7235	u8 reserved_at_20[0x10];
7236	u8 op_mod[0x10];
7237
7238	u8 reserved_at_40[0x8];
7239	u8 tirn[0x18];
7240
7241	u8 reserved_at_60[0x20];
7242
7243	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7244
7245	u8 reserved_at_c0[0x40];
7246
7247	struct mlx5_ifc_tirc_bits ctx;
7248	};
7249
7250	struct mlx5_ifc_modify_sq_out_bits {
7251	u8 status[0x8];
7252	u8 reserved_at_8[0x18];
7253
7254	u8 syndrome[0x20];
7255
7256	u8 reserved_at_40[0x40];
7257	};
7258
7259	struct mlx5_ifc_modify_sq_in_bits {
7260	u8 opcode[0x10];
7261	u8 uid[0x10];
7262
7263	u8 reserved_at_20[0x10];
7264	u8 op_mod[0x10];
7265
7266	u8 sq_state[0x4];
7267	u8 reserved_at_44[0x4];
7268	u8 sqn[0x18];
7269
7270	u8 reserved_at_60[0x20];
7271
7272	u8 modify_bitmask[0x40];
7273
7274	u8 reserved_at_c0[0x40];
7275
7276	struct mlx5_ifc_sqc_bits ctx;
7277	};
7278
7279	struct mlx5_ifc_modify_scheduling_element_out_bits {
7280	u8 status[0x8];
7281	u8 reserved_at_8[0x18];
7282
7283	u8 syndrome[0x20];
7284
7285	u8 reserved_at_40[0x1c0];
7286	};
7287
7288	enum {
7289	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7290	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7291	};
7292
7293	struct mlx5_ifc_modify_scheduling_element_in_bits {
7294	u8 opcode[0x10];
7295	u8 reserved_at_10[0x10];
7296
7297	u8 reserved_at_20[0x10];
7298	u8 op_mod[0x10];
7299
7300	u8 scheduling_hierarchy[0x8];
7301	u8 reserved_at_48[0x18];
7302
7303	u8 scheduling_element_id[0x20];
7304
7305	u8 reserved_at_80[0x20];
7306
7307	u8 modify_bitmask[0x20];
7308
7309	u8 reserved_at_c0[0x40];
7310
7311	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7312
7313	u8 reserved_at_300[0x100];
7314	};
7315
7316	struct mlx5_ifc_modify_rqt_out_bits {
7317	u8 status[0x8];
7318	u8 reserved_at_8[0x18];
7319
7320	u8 syndrome[0x20];
7321
7322	u8 reserved_at_40[0x40];
7323	};
7324
7325	struct mlx5_ifc_rqt_bitmask_bits {
7326	u8 reserved_at_0[0x20];
7327
7328	u8 reserved_at_20[0x1f];
7329	u8 rqn_list[0x1];
7330	};
7331
7332	struct mlx5_ifc_modify_rqt_in_bits {
7333	u8 opcode[0x10];
7334	u8 uid[0x10];
7335
7336	u8 reserved_at_20[0x10];
7337	u8 op_mod[0x10];
7338
7339	u8 reserved_at_40[0x8];
7340	u8 rqtn[0x18];
7341
7342	u8 reserved_at_60[0x20];
7343
7344	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7345
7346	u8 reserved_at_c0[0x40];
7347
7348	struct mlx5_ifc_rqtc_bits ctx;
7349	};
7350
7351	struct mlx5_ifc_modify_rq_out_bits {
7352	u8 status[0x8];
7353	u8 reserved_at_8[0x18];
7354
7355	u8 syndrome[0x20];
7356
7357	u8 reserved_at_40[0x40];
7358	};
7359
7360	enum {
7361	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7362	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7363	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7364	};
7365
7366	struct mlx5_ifc_modify_rq_in_bits {
7367	u8 opcode[0x10];
7368	u8 uid[0x10];
7369
7370	u8 reserved_at_20[0x10];
7371	u8 op_mod[0x10];
7372
7373	u8 rq_state[0x4];
7374	u8 reserved_at_44[0x4];
7375	u8 rqn[0x18];
7376
7377	u8 reserved_at_60[0x20];
7378
7379	u8 modify_bitmask[0x40];
7380
7381	u8 reserved_at_c0[0x40];
7382
7383	struct mlx5_ifc_rqc_bits ctx;
7384	};
7385
7386	struct mlx5_ifc_modify_rmp_out_bits {
7387	u8 status[0x8];
7388	u8 reserved_at_8[0x18];
7389
7390	u8 syndrome[0x20];
7391
7392	u8 reserved_at_40[0x40];
7393	};
7394
7395	struct mlx5_ifc_rmp_bitmask_bits {
7396	u8 reserved_at_0[0x20];
7397
7398	u8 reserved_at_20[0x1f];
7399	u8 lwm[0x1];
7400	};
7401
7402	struct mlx5_ifc_modify_rmp_in_bits {
7403	u8 opcode[0x10];
7404	u8 uid[0x10];
7405
7406	u8 reserved_at_20[0x10];
7407	u8 op_mod[0x10];
7408
7409	u8 rmp_state[0x4];
7410	u8 reserved_at_44[0x4];
7411	u8 rmpn[0x18];
7412
7413	u8 reserved_at_60[0x20];
7414
7415	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7416
7417	u8 reserved_at_c0[0x40];
7418
7419	struct mlx5_ifc_rmpc_bits ctx;
7420	};
7421
7422	struct mlx5_ifc_modify_nic_vport_context_out_bits {
7423	u8 status[0x8];
7424	u8 reserved_at_8[0x18];
7425
7426	u8 syndrome[0x20];
7427
7428	u8 reserved_at_40[0x40];
7429	};
7430
7431	struct mlx5_ifc_modify_nic_vport_field_select_bits {
7432	u8 reserved_at_0[0x12];
7433	u8 affiliation[0x1];
7434	u8 reserved_at_13[0x1];
7435	u8 disable_uc_local_lb[0x1];
7436	u8 disable_mc_local_lb[0x1];
7437	u8 node_guid[0x1];
7438	u8 port_guid[0x1];
7439	u8 min_inline[0x1];
7440	u8 mtu[0x1];
7441	u8 change_event[0x1];
7442	u8 promisc[0x1];
7443	u8 permanent_address[0x1];
7444	u8 addresses_list[0x1];
7445	u8 roce_en[0x1];
7446	u8 reserved_at_1f[0x1];
7447	};
7448
7449	struct mlx5_ifc_modify_nic_vport_context_in_bits {
7450	u8 opcode[0x10];
7451	u8 reserved_at_10[0x10];
7452
7453	u8 reserved_at_20[0x10];
7454	u8 op_mod[0x10];
7455
7456	u8 other_vport[0x1];
7457	u8 reserved_at_41[0xf];
7458	u8 vport_number[0x10];
7459
7460	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7461
7462	u8 reserved_at_80[0x780];
7463
7464	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7465	};
7466
7467	struct mlx5_ifc_modify_hca_vport_context_out_bits {
7468	u8 status[0x8];
7469	u8 reserved_at_8[0x18];
7470
7471	u8 syndrome[0x20];
7472
7473	u8 reserved_at_40[0x40];
7474	};
7475
7476	struct mlx5_ifc_modify_hca_vport_context_in_bits {
7477	u8 opcode[0x10];
7478	u8 reserved_at_10[0x10];
7479
7480	u8 reserved_at_20[0x10];
7481	u8 op_mod[0x10];
7482
7483	u8 other_vport[0x1];
7484	u8 reserved_at_41[0xb];
7485	u8 port_num[0x4];
7486	u8 vport_number[0x10];
7487
7488	u8 reserved_at_60[0x20];
7489
7490	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7491	};
7492
7493	struct mlx5_ifc_modify_cq_out_bits {
7494	u8 status[0x8];
7495	u8 reserved_at_8[0x18];
7496
7497	u8 syndrome[0x20];
7498
7499	u8 reserved_at_40[0x40];
7500	};
7501
7502	enum {
7503	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7504	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7505	};
7506
7507	struct mlx5_ifc_modify_cq_in_bits {
7508	u8 opcode[0x10];
7509	u8 uid[0x10];
7510
7511	u8 reserved_at_20[0x10];
7512	u8 op_mod[0x10];
7513
7514	u8 reserved_at_40[0x8];
7515	u8 cqn[0x18];
7516
7517	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7518
7519	struct mlx5_ifc_cqc_bits cq_context;
7520
7521	u8 reserved_at_280[0x60];
7522
7523	u8 cq_umem_valid[0x1];
7524	u8 reserved_at_2e1[0x1f];
7525
7526	u8 reserved_at_300[0x580];
7527
7528	u8 pas[][0x40];
7529	};
7530
7531	struct mlx5_ifc_modify_cong_status_out_bits {
7532	u8 status[0x8];
7533	u8 reserved_at_8[0x18];
7534
7535	u8 syndrome[0x20];
7536
7537	u8 reserved_at_40[0x40];
7538	};
7539
7540	struct mlx5_ifc_modify_cong_status_in_bits {
7541	u8 opcode[0x10];
7542	u8 reserved_at_10[0x10];
7543
7544	u8 reserved_at_20[0x10];
7545	u8 op_mod[0x10];
7546
7547	u8 reserved_at_40[0x18];
7548	u8 priority[0x4];
7549	u8 cong_protocol[0x4];
7550
7551	u8 enable[0x1];
7552	u8 tag_enable[0x1];
7553	u8 reserved_at_62[0x1e];
7554	};
7555
7556	struct mlx5_ifc_modify_cong_params_out_bits {
7557	u8 status[0x8];
7558	u8 reserved_at_8[0x18];
7559
7560	u8 syndrome[0x20];
7561
7562	u8 reserved_at_40[0x40];
7563	};
7564
7565	struct mlx5_ifc_modify_cong_params_in_bits {
7566	u8 opcode[0x10];
7567	u8 reserved_at_10[0x10];
7568
7569	u8 reserved_at_20[0x10];
7570	u8 op_mod[0x10];
7571
7572	u8 reserved_at_40[0x1c];
7573	u8 cong_protocol[0x4];
7574
7575	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7576
7577	u8 reserved_at_80[0x80];
7578
7579	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7580	};
7581
7582	struct mlx5_ifc_manage_pages_out_bits {
7583	u8 status[0x8];
7584	u8 reserved_at_8[0x18];
7585
7586	u8 syndrome[0x20];
7587
7588	u8 output_num_entries[0x20];
7589
7590	u8 reserved_at_60[0x20];
7591
7592	u8 pas[][0x40];
7593	};
7594
7595	enum {
7596	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7597	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7598	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7599	};
7600
7601	struct mlx5_ifc_manage_pages_in_bits {
7602	u8 opcode[0x10];
7603	u8 reserved_at_10[0x10];
7604
7605	u8 reserved_at_20[0x10];
7606	u8 op_mod[0x10];
7607
7608	u8 embedded_cpu_function[0x1];
7609	u8 reserved_at_41[0xf];
7610	u8 function_id[0x10];
7611
7612	u8 input_num_entries[0x20];
7613
7614	u8 pas[][0x40];
7615	};
7616
7617	struct mlx5_ifc_mad_ifc_out_bits {
7618	u8 status[0x8];
7619	u8 reserved_at_8[0x18];
7620
7621	u8 syndrome[0x20];
7622
7623	u8 reserved_at_40[0x40];
7624
7625	u8 response_mad_packet[256][0x8];
7626	};
7627
7628	struct mlx5_ifc_mad_ifc_in_bits {
7629	u8 opcode[0x10];
7630	u8 reserved_at_10[0x10];
7631
7632	u8 reserved_at_20[0x10];
7633	u8 op_mod[0x10];
7634
7635	u8 remote_lid[0x10];
7636	u8 reserved_at_50[0x8];
7637	u8 port[0x8];
7638
7639	u8 reserved_at_60[0x20];
7640
7641	u8 mad[256][0x8];
7642	};
7643
7644	struct mlx5_ifc_init_hca_out_bits {
7645	u8 status[0x8];
7646	u8 reserved_at_8[0x18];
7647
7648	u8 syndrome[0x20];
7649
7650	u8 reserved_at_40[0x40];
7651	};
7652
7653	struct mlx5_ifc_init_hca_in_bits {
7654	u8 opcode[0x10];
7655	u8 reserved_at_10[0x10];
7656
7657	u8 reserved_at_20[0x10];
7658	u8 op_mod[0x10];
7659
7660	u8 reserved_at_40[0x20];
7661
7662	u8 reserved_at_60[0x2];
7663	u8 sw_vhca_id[0xe];
7664	u8 reserved_at_70[0x10];
7665
7666	u8 sw_owner_id[4][0x20];
7667	};
7668
7669	struct mlx5_ifc_init2rtr_qp_out_bits {
7670	u8 status[0x8];
7671	u8 reserved_at_8[0x18];
7672
7673	u8 syndrome[0x20];
7674
7675	u8 reserved_at_40[0x20];
7676	u8 ece[0x20];
7677	};
7678
7679	struct mlx5_ifc_init2rtr_qp_in_bits {
7680	u8 opcode[0x10];
7681	u8 uid[0x10];
7682
7683	u8 reserved_at_20[0x10];
7684	u8 op_mod[0x10];
7685
7686	u8 reserved_at_40[0x8];
7687	u8 qpn[0x18];
7688
7689	u8 reserved_at_60[0x20];
7690
7691	u8 opt_param_mask[0x20];
7692
7693	u8 ece[0x20];
7694
7695	struct mlx5_ifc_qpc_bits qpc;
7696
7697	u8 reserved_at_800[0x80];
7698	};
7699
7700	struct mlx5_ifc_init2init_qp_out_bits {
7701	u8 status[0x8];
7702	u8 reserved_at_8[0x18];
7703
7704	u8 syndrome[0x20];
7705
7706	u8 reserved_at_40[0x20];
7707	u8 ece[0x20];
7708	};
7709
7710	struct mlx5_ifc_init2init_qp_in_bits {
7711	u8 opcode[0x10];
7712	u8 uid[0x10];
7713
7714	u8 reserved_at_20[0x10];
7715	u8 op_mod[0x10];
7716
7717	u8 reserved_at_40[0x8];
7718	u8 qpn[0x18];
7719
7720	u8 reserved_at_60[0x20];
7721
7722	u8 opt_param_mask[0x20];
7723
7724	u8 ece[0x20];
7725
7726	struct mlx5_ifc_qpc_bits qpc;
7727
7728	u8 reserved_at_800[0x80];
7729	};
7730
7731	struct mlx5_ifc_get_dropped_packet_log_out_bits {
7732	u8 status[0x8];
7733	u8 reserved_at_8[0x18];
7734
7735	u8 syndrome[0x20];
7736
7737	u8 reserved_at_40[0x40];
7738
7739	u8 packet_headers_log[128][0x8];
7740
7741	u8 packet_syndrome[64][0x8];
7742	};
7743
7744	struct mlx5_ifc_get_dropped_packet_log_in_bits {
7745	u8 opcode[0x10];
7746	u8 reserved_at_10[0x10];
7747
7748	u8 reserved_at_20[0x10];
7749	u8 op_mod[0x10];
7750
7751	u8 reserved_at_40[0x40];
7752	};
7753
7754	struct mlx5_ifc_gen_eqe_in_bits {
7755	u8 opcode[0x10];
7756	u8 reserved_at_10[0x10];
7757
7758	u8 reserved_at_20[0x10];
7759	u8 op_mod[0x10];
7760
7761	u8 reserved_at_40[0x18];
7762	u8 eq_number[0x8];
7763
7764	u8 reserved_at_60[0x20];
7765
7766	u8 eqe[64][0x8];
7767	};
7768
7769	struct mlx5_ifc_gen_eq_out_bits {
7770	u8 status[0x8];
7771	u8 reserved_at_8[0x18];
7772
7773	u8 syndrome[0x20];
7774
7775	u8 reserved_at_40[0x40];
7776	};
7777
7778	struct mlx5_ifc_enable_hca_out_bits {
7779	u8 status[0x8];
7780	u8 reserved_at_8[0x18];
7781
7782	u8 syndrome[0x20];
7783
7784	u8 reserved_at_40[0x20];
7785	};
7786
7787	struct mlx5_ifc_enable_hca_in_bits {
7788	u8 opcode[0x10];
7789	u8 reserved_at_10[0x10];
7790
7791	u8 reserved_at_20[0x10];
7792	u8 op_mod[0x10];
7793
7794	u8 embedded_cpu_function[0x1];
7795	u8 reserved_at_41[0xf];
7796	u8 function_id[0x10];
7797
7798	u8 reserved_at_60[0x20];
7799	};
7800
7801	struct mlx5_ifc_drain_dct_out_bits {
7802	u8 status[0x8];
7803	u8 reserved_at_8[0x18];
7804
7805	u8 syndrome[0x20];
7806
7807	u8 reserved_at_40[0x40];
7808	};
7809
7810	struct mlx5_ifc_drain_dct_in_bits {
7811	u8 opcode[0x10];
7812	u8 uid[0x10];
7813
7814	u8 reserved_at_20[0x10];
7815	u8 op_mod[0x10];
7816
7817	u8 reserved_at_40[0x8];
7818	u8 dctn[0x18];
7819
7820	u8 reserved_at_60[0x20];
7821	};
7822
7823	struct mlx5_ifc_disable_hca_out_bits {
7824	u8 status[0x8];
7825	u8 reserved_at_8[0x18];
7826
7827	u8 syndrome[0x20];
7828
7829	u8 reserved_at_40[0x20];
7830	};
7831
7832	struct mlx5_ifc_disable_hca_in_bits {
7833	u8 opcode[0x10];
7834	u8 reserved_at_10[0x10];
7835
7836	u8 reserved_at_20[0x10];
7837	u8 op_mod[0x10];
7838
7839	u8 embedded_cpu_function[0x1];
7840	u8 reserved_at_41[0xf];
7841	u8 function_id[0x10];
7842
7843	u8 reserved_at_60[0x20];
7844	};
7845
7846	struct mlx5_ifc_detach_from_mcg_out_bits {
7847	u8 status[0x8];
7848	u8 reserved_at_8[0x18];
7849
7850	u8 syndrome[0x20];
7851
7852	u8 reserved_at_40[0x40];
7853	};
7854
7855	struct mlx5_ifc_detach_from_mcg_in_bits {
7856	u8 opcode[0x10];
7857	u8 uid[0x10];
7858
7859	u8 reserved_at_20[0x10];
7860	u8 op_mod[0x10];
7861
7862	u8 reserved_at_40[0x8];
7863	u8 qpn[0x18];
7864
7865	u8 reserved_at_60[0x20];
7866
7867	u8 multicast_gid[16][0x8];
7868	};
7869
7870	struct mlx5_ifc_destroy_xrq_out_bits {
7871	u8 status[0x8];
7872	u8 reserved_at_8[0x18];
7873
7874	u8 syndrome[0x20];
7875
7876	u8 reserved_at_40[0x40];
7877	};
7878
7879	struct mlx5_ifc_destroy_xrq_in_bits {
7880	u8 opcode[0x10];
7881	u8 uid[0x10];
7882
7883	u8 reserved_at_20[0x10];
7884	u8 op_mod[0x10];
7885
7886	u8 reserved_at_40[0x8];
7887	u8 xrqn[0x18];
7888
7889	u8 reserved_at_60[0x20];
7890	};
7891
7892	struct mlx5_ifc_destroy_xrc_srq_out_bits {
7893	u8 status[0x8];
7894	u8 reserved_at_8[0x18];
7895
7896	u8 syndrome[0x20];
7897
7898	u8 reserved_at_40[0x40];
7899	};
7900
7901	struct mlx5_ifc_destroy_xrc_srq_in_bits {
7902	u8 opcode[0x10];
7903	u8 uid[0x10];
7904
7905	u8 reserved_at_20[0x10];
7906	u8 op_mod[0x10];
7907
7908	u8 reserved_at_40[0x8];
7909	u8 xrc_srqn[0x18];
7910
7911	u8 reserved_at_60[0x20];
7912	};
7913
7914	struct mlx5_ifc_destroy_tis_out_bits {
7915	u8 status[0x8];
7916	u8 reserved_at_8[0x18];
7917
7918	u8 syndrome[0x20];
7919
7920	u8 reserved_at_40[0x40];
7921	};
7922
7923	struct mlx5_ifc_destroy_tis_in_bits {
7924	u8 opcode[0x10];
7925	u8 uid[0x10];
7926
7927	u8 reserved_at_20[0x10];
7928	u8 op_mod[0x10];
7929
7930	u8 reserved_at_40[0x8];
7931	u8 tisn[0x18];
7932
7933	u8 reserved_at_60[0x20];
7934	};
7935
7936	struct mlx5_ifc_destroy_tir_out_bits {
7937	u8 status[0x8];
7938	u8 reserved_at_8[0x18];
7939
7940	u8 syndrome[0x20];
7941
7942	u8 reserved_at_40[0x40];
7943	};
7944
7945	struct mlx5_ifc_destroy_tir_in_bits {
7946	u8 opcode[0x10];
7947	u8 uid[0x10];
7948
7949	u8 reserved_at_20[0x10];
7950	u8 op_mod[0x10];
7951
7952	u8 reserved_at_40[0x8];
7953	u8 tirn[0x18];
7954
7955	u8 reserved_at_60[0x20];
7956	};
7957
7958	struct mlx5_ifc_destroy_srq_out_bits {
7959	u8 status[0x8];
7960	u8 reserved_at_8[0x18];
7961
7962	u8 syndrome[0x20];
7963
7964	u8 reserved_at_40[0x40];
7965	};
7966
7967	struct mlx5_ifc_destroy_srq_in_bits {
7968	u8 opcode[0x10];
7969	u8 uid[0x10];
7970
7971	u8 reserved_at_20[0x10];
7972	u8 op_mod[0x10];
7973
7974	u8 reserved_at_40[0x8];
7975	u8 srqn[0x18];
7976
7977	u8 reserved_at_60[0x20];
7978	};
7979
7980	struct mlx5_ifc_destroy_sq_out_bits {
7981	u8 status[0x8];
7982	u8 reserved_at_8[0x18];
7983
7984	u8 syndrome[0x20];
7985
7986	u8 reserved_at_40[0x40];
7987	};
7988
7989	struct mlx5_ifc_destroy_sq_in_bits {
7990	u8 opcode[0x10];
7991	u8 uid[0x10];
7992
7993	u8 reserved_at_20[0x10];
7994	u8 op_mod[0x10];
7995
7996	u8 reserved_at_40[0x8];
7997	u8 sqn[0x18];
7998
7999	u8 reserved_at_60[0x20];
8000	};
8001
8002	struct mlx5_ifc_destroy_scheduling_element_out_bits {
8003	u8 status[0x8];
8004	u8 reserved_at_8[0x18];
8005
8006	u8 syndrome[0x20];
8007
8008	u8 reserved_at_40[0x1c0];
8009	};
8010
8011	struct mlx5_ifc_destroy_scheduling_element_in_bits {
8012	u8 opcode[0x10];
8013	u8 reserved_at_10[0x10];
8014
8015	u8 reserved_at_20[0x10];
8016	u8 op_mod[0x10];
8017
8018	u8 scheduling_hierarchy[0x8];
8019	u8 reserved_at_48[0x18];
8020
8021	u8 scheduling_element_id[0x20];
8022
8023	u8 reserved_at_80[0x180];
8024	};
8025
8026	struct mlx5_ifc_destroy_rqt_out_bits {
8027	u8 status[0x8];
8028	u8 reserved_at_8[0x18];
8029
8030	u8 syndrome[0x20];
8031
8032	u8 reserved_at_40[0x40];
8033	};
8034
8035	struct mlx5_ifc_destroy_rqt_in_bits {
8036	u8 opcode[0x10];
8037	u8 uid[0x10];
8038
8039	u8 reserved_at_20[0x10];
8040	u8 op_mod[0x10];
8041
8042	u8 reserved_at_40[0x8];
8043	u8 rqtn[0x18];
8044
8045	u8 reserved_at_60[0x20];
8046	};
8047
8048	struct mlx5_ifc_destroy_rq_out_bits {
8049	u8 status[0x8];
8050	u8 reserved_at_8[0x18];
8051
8052	u8 syndrome[0x20];
8053
8054	u8 reserved_at_40[0x40];
8055	};
8056
8057	struct mlx5_ifc_destroy_rq_in_bits {
8058	u8 opcode[0x10];
8059	u8 uid[0x10];
8060
8061	u8 reserved_at_20[0x10];
8062	u8 op_mod[0x10];
8063
8064	u8 reserved_at_40[0x8];
8065	u8 rqn[0x18];
8066
8067	u8 reserved_at_60[0x20];
8068	};
8069
8070	struct mlx5_ifc_set_delay_drop_params_in_bits {
8071	u8 opcode[0x10];
8072	u8 reserved_at_10[0x10];
8073
8074	u8 reserved_at_20[0x10];
8075	u8 op_mod[0x10];
8076
8077	u8 reserved_at_40[0x20];
8078
8079	u8 reserved_at_60[0x10];
8080	u8 delay_drop_timeout[0x10];
8081	};
8082
8083	struct mlx5_ifc_set_delay_drop_params_out_bits {
8084	u8 status[0x8];
8085	u8 reserved_at_8[0x18];
8086
8087	u8 syndrome[0x20];
8088
8089	u8 reserved_at_40[0x40];
8090	};
8091
8092	struct mlx5_ifc_destroy_rmp_out_bits {
8093	u8 status[0x8];
8094	u8 reserved_at_8[0x18];
8095
8096	u8 syndrome[0x20];
8097
8098	u8 reserved_at_40[0x40];
8099	};
8100
8101	struct mlx5_ifc_destroy_rmp_in_bits {
8102	u8 opcode[0x10];
8103	u8 uid[0x10];
8104
8105	u8 reserved_at_20[0x10];
8106	u8 op_mod[0x10];
8107
8108	u8 reserved_at_40[0x8];
8109	u8 rmpn[0x18];
8110
8111	u8 reserved_at_60[0x20];
8112	};
8113
8114	struct mlx5_ifc_destroy_qp_out_bits {
8115	u8 status[0x8];
8116	u8 reserved_at_8[0x18];
8117
8118	u8 syndrome[0x20];
8119
8120	u8 reserved_at_40[0x40];
8121	};
8122
8123	struct mlx5_ifc_destroy_qp_in_bits {
8124	u8 opcode[0x10];
8125	u8 uid[0x10];
8126
8127	u8 reserved_at_20[0x10];
8128	u8 op_mod[0x10];
8129
8130	u8 reserved_at_40[0x8];
8131	u8 qpn[0x18];
8132
8133	u8 reserved_at_60[0x20];
8134	};
8135
8136	struct mlx5_ifc_destroy_psv_out_bits {
8137	u8 status[0x8];
8138	u8 reserved_at_8[0x18];
8139
8140	u8 syndrome[0x20];
8141
8142	u8 reserved_at_40[0x40];
8143	};
8144
8145	struct mlx5_ifc_destroy_psv_in_bits {
8146	u8 opcode[0x10];
8147	u8 reserved_at_10[0x10];
8148
8149	u8 reserved_at_20[0x10];
8150	u8 op_mod[0x10];
8151
8152	u8 reserved_at_40[0x8];
8153	u8 psvn[0x18];
8154
8155	u8 reserved_at_60[0x20];
8156	};
8157
8158	struct mlx5_ifc_destroy_mkey_out_bits {
8159	u8 status[0x8];
8160	u8 reserved_at_8[0x18];
8161
8162	u8 syndrome[0x20];
8163
8164	u8 reserved_at_40[0x40];
8165	};
8166
8167	struct mlx5_ifc_destroy_mkey_in_bits {
8168	u8 opcode[0x10];
8169	u8 uid[0x10];
8170
8171	u8 reserved_at_20[0x10];
8172	u8 op_mod[0x10];
8173
8174	u8 reserved_at_40[0x8];
8175	u8 mkey_index[0x18];
8176
8177	u8 reserved_at_60[0x20];
8178	};
8179
8180	struct mlx5_ifc_destroy_flow_table_out_bits {
8181	u8 status[0x8];
8182	u8 reserved_at_8[0x18];
8183
8184	u8 syndrome[0x20];
8185
8186	u8 reserved_at_40[0x40];
8187	};
8188
8189	struct mlx5_ifc_destroy_flow_table_in_bits {
8190	u8 opcode[0x10];
8191	u8 reserved_at_10[0x10];
8192
8193	u8 reserved_at_20[0x10];
8194	u8 op_mod[0x10];
8195
8196	u8 other_vport[0x1];
8197	u8 reserved_at_41[0xf];
8198	u8 vport_number[0x10];
8199
8200	u8 reserved_at_60[0x20];
8201
8202	u8 table_type[0x8];
8203	u8 reserved_at_88[0x18];
8204
8205	u8 reserved_at_a0[0x8];
8206	u8 table_id[0x18];
8207
8208	u8 reserved_at_c0[0x140];
8209	};
8210
8211	struct mlx5_ifc_destroy_flow_group_out_bits {
8212	u8 status[0x8];
8213	u8 reserved_at_8[0x18];
8214
8215	u8 syndrome[0x20];
8216
8217	u8 reserved_at_40[0x40];
8218	};
8219
8220	struct mlx5_ifc_destroy_flow_group_in_bits {
8221	u8 opcode[0x10];
8222	u8 reserved_at_10[0x10];
8223
8224	u8 reserved_at_20[0x10];
8225	u8 op_mod[0x10];
8226
8227	u8 other_vport[0x1];
8228	u8 reserved_at_41[0xf];
8229	u8 vport_number[0x10];
8230
8231	u8 reserved_at_60[0x20];
8232
8233	u8 table_type[0x8];
8234	u8 reserved_at_88[0x18];
8235
8236	u8 reserved_at_a0[0x8];
8237	u8 table_id[0x18];
8238
8239	u8 group_id[0x20];
8240
8241	u8 reserved_at_e0[0x120];
8242	};
8243
8244	struct mlx5_ifc_destroy_eq_out_bits {
8245	u8 status[0x8];
8246	u8 reserved_at_8[0x18];
8247
8248	u8 syndrome[0x20];
8249
8250	u8 reserved_at_40[0x40];
8251	};
8252
8253	struct mlx5_ifc_destroy_eq_in_bits {
8254	u8 opcode[0x10];
8255	u8 reserved_at_10[0x10];
8256
8257	u8 reserved_at_20[0x10];
8258	u8 op_mod[0x10];
8259
8260	u8 reserved_at_40[0x18];
8261	u8 eq_number[0x8];
8262
8263	u8 reserved_at_60[0x20];
8264	};
8265
8266	struct mlx5_ifc_destroy_dct_out_bits {
8267	u8 status[0x8];
8268	u8 reserved_at_8[0x18];
8269
8270	u8 syndrome[0x20];
8271
8272	u8 reserved_at_40[0x40];
8273	};
8274
8275	struct mlx5_ifc_destroy_dct_in_bits {
8276	u8 opcode[0x10];
8277	u8 uid[0x10];
8278
8279	u8 reserved_at_20[0x10];
8280	u8 op_mod[0x10];
8281
8282	u8 reserved_at_40[0x8];
8283	u8 dctn[0x18];
8284
8285	u8 reserved_at_60[0x20];
8286	};
8287
8288	struct mlx5_ifc_destroy_cq_out_bits {
8289	u8 status[0x8];
8290	u8 reserved_at_8[0x18];
8291
8292	u8 syndrome[0x20];
8293
8294	u8 reserved_at_40[0x40];
8295	};
8296
8297	struct mlx5_ifc_destroy_cq_in_bits {
8298	u8 opcode[0x10];
8299	u8 uid[0x10];
8300
8301	u8 reserved_at_20[0x10];
8302	u8 op_mod[0x10];
8303
8304	u8 reserved_at_40[0x8];
8305	u8 cqn[0x18];
8306
8307	u8 reserved_at_60[0x20];
8308	};
8309
8310	struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8311	u8 status[0x8];
8312	u8 reserved_at_8[0x18];
8313
8314	u8 syndrome[0x20];
8315
8316	u8 reserved_at_40[0x40];
8317	};
8318
8319	struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8320	u8 opcode[0x10];
8321	u8 reserved_at_10[0x10];
8322
8323	u8 reserved_at_20[0x10];
8324	u8 op_mod[0x10];
8325
8326	u8 reserved_at_40[0x20];
8327
8328	u8 reserved_at_60[0x10];
8329	u8 vxlan_udp_port[0x10];
8330	};
8331
8332	struct mlx5_ifc_delete_l2_table_entry_out_bits {
8333	u8 status[0x8];
8334	u8 reserved_at_8[0x18];
8335
8336	u8 syndrome[0x20];
8337
8338	u8 reserved_at_40[0x40];
8339	};
8340
8341	struct mlx5_ifc_delete_l2_table_entry_in_bits {
8342	u8 opcode[0x10];
8343	u8 reserved_at_10[0x10];
8344
8345	u8 reserved_at_20[0x10];
8346	u8 op_mod[0x10];
8347
8348	u8 reserved_at_40[0x60];
8349
8350	u8 reserved_at_a0[0x8];
8351	u8 table_index[0x18];
8352
8353	u8 reserved_at_c0[0x140];
8354	};
8355
8356	struct mlx5_ifc_delete_fte_out_bits {
8357	u8 status[0x8];
8358	u8 reserved_at_8[0x18];
8359
8360	u8 syndrome[0x20];
8361
8362	u8 reserved_at_40[0x40];
8363	};
8364
8365	struct mlx5_ifc_delete_fte_in_bits {
8366	u8 opcode[0x10];
8367	u8 reserved_at_10[0x10];
8368
8369	u8 reserved_at_20[0x10];
8370	u8 op_mod[0x10];
8371
8372	u8 other_vport[0x1];
8373	u8 reserved_at_41[0xf];
8374	u8 vport_number[0x10];
8375
8376	u8 reserved_at_60[0x20];
8377
8378	u8 table_type[0x8];
8379	u8 reserved_at_88[0x18];
8380
8381	u8 reserved_at_a0[0x8];
8382	u8 table_id[0x18];
8383
8384	u8 reserved_at_c0[0x40];
8385
8386	u8 flow_index[0x20];
8387
8388	u8 reserved_at_120[0xe0];
8389	};
8390
8391	struct mlx5_ifc_dealloc_xrcd_out_bits {
8392	u8 status[0x8];
8393	u8 reserved_at_8[0x18];
8394
8395	u8 syndrome[0x20];
8396
8397	u8 reserved_at_40[0x40];
8398	};
8399
8400	struct mlx5_ifc_dealloc_xrcd_in_bits {
8401	u8 opcode[0x10];
8402	u8 uid[0x10];
8403
8404	u8 reserved_at_20[0x10];
8405	u8 op_mod[0x10];
8406
8407	u8 reserved_at_40[0x8];
8408	u8 xrcd[0x18];
8409
8410	u8 reserved_at_60[0x20];
8411	};
8412
8413	struct mlx5_ifc_dealloc_uar_out_bits {
8414	u8 status[0x8];
8415	u8 reserved_at_8[0x18];
8416
8417	u8 syndrome[0x20];
8418
8419	u8 reserved_at_40[0x40];
8420	};
8421
8422	struct mlx5_ifc_dealloc_uar_in_bits {
8423	u8 opcode[0x10];
8424	u8 uid[0x10];
8425
8426	u8 reserved_at_20[0x10];
8427	u8 op_mod[0x10];
8428
8429	u8 reserved_at_40[0x8];
8430	u8 uar[0x18];
8431
8432	u8 reserved_at_60[0x20];
8433	};
8434
8435	struct mlx5_ifc_dealloc_transport_domain_out_bits {
8436	u8 status[0x8];
8437	u8 reserved_at_8[0x18];
8438
8439	u8 syndrome[0x20];
8440
8441	u8 reserved_at_40[0x40];
8442	};
8443
8444	struct mlx5_ifc_dealloc_transport_domain_in_bits {
8445	u8 opcode[0x10];
8446	u8 uid[0x10];
8447
8448	u8 reserved_at_20[0x10];
8449	u8 op_mod[0x10];
8450
8451	u8 reserved_at_40[0x8];
8452	u8 transport_domain[0x18];
8453
8454	u8 reserved_at_60[0x20];
8455	};
8456
8457	struct mlx5_ifc_dealloc_q_counter_out_bits {
8458	u8 status[0x8];
8459	u8 reserved_at_8[0x18];
8460
8461	u8 syndrome[0x20];
8462
8463	u8 reserved_at_40[0x40];
8464	};
8465
8466	struct mlx5_ifc_dealloc_q_counter_in_bits {
8467	u8 opcode[0x10];
8468	u8 reserved_at_10[0x10];
8469
8470	u8 reserved_at_20[0x10];
8471	u8 op_mod[0x10];
8472
8473	u8 reserved_at_40[0x18];
8474	u8 counter_set_id[0x8];
8475
8476	u8 reserved_at_60[0x20];
8477	};
8478
8479	struct mlx5_ifc_dealloc_pd_out_bits {
8480	u8 status[0x8];
8481	u8 reserved_at_8[0x18];
8482
8483	u8 syndrome[0x20];
8484
8485	u8 reserved_at_40[0x40];
8486	};
8487
8488	struct mlx5_ifc_dealloc_pd_in_bits {
8489	u8 opcode[0x10];
8490	u8 uid[0x10];
8491
8492	u8 reserved_at_20[0x10];
8493	u8 op_mod[0x10];
8494
8495	u8 reserved_at_40[0x8];
8496	u8 pd[0x18];
8497
8498	u8 reserved_at_60[0x20];
8499	};
8500
8501	struct mlx5_ifc_dealloc_flow_counter_out_bits {
8502	u8 status[0x8];
8503	u8 reserved_at_8[0x18];
8504
8505	u8 syndrome[0x20];
8506
8507	u8 reserved_at_40[0x40];
8508	};
8509
8510	struct mlx5_ifc_dealloc_flow_counter_in_bits {
8511	u8 opcode[0x10];
8512	u8 reserved_at_10[0x10];
8513
8514	u8 reserved_at_20[0x10];
8515	u8 op_mod[0x10];
8516
8517	u8 flow_counter_id[0x20];
8518
8519	u8 reserved_at_60[0x20];
8520	};
8521
8522	struct mlx5_ifc_create_xrq_out_bits {
8523	u8 status[0x8];
8524	u8 reserved_at_8[0x18];
8525
8526	u8 syndrome[0x20];
8527
8528	u8 reserved_at_40[0x8];
8529	u8 xrqn[0x18];
8530
8531	u8 reserved_at_60[0x20];
8532	};
8533
8534	struct mlx5_ifc_create_xrq_in_bits {
8535	u8 opcode[0x10];
8536	u8 uid[0x10];
8537
8538	u8 reserved_at_20[0x10];
8539	u8 op_mod[0x10];
8540
8541	u8 reserved_at_40[0x40];
8542
8543	struct mlx5_ifc_xrqc_bits xrq_context;
8544	};
8545
8546	struct mlx5_ifc_create_xrc_srq_out_bits {
8547	u8 status[0x8];
8548	u8 reserved_at_8[0x18];
8549
8550	u8 syndrome[0x20];
8551
8552	u8 reserved_at_40[0x8];
8553	u8 xrc_srqn[0x18];
8554
8555	u8 reserved_at_60[0x20];
8556	};
8557
8558	struct mlx5_ifc_create_xrc_srq_in_bits {
8559	u8 opcode[0x10];
8560	u8 uid[0x10];
8561
8562	u8 reserved_at_20[0x10];
8563	u8 op_mod[0x10];
8564
8565	u8 reserved_at_40[0x40];
8566
8567	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8568
8569	u8 reserved_at_280[0x60];
8570
8571	u8 xrc_srq_umem_valid[0x1];
8572	u8 reserved_at_2e1[0x1f];
8573
8574	u8 reserved_at_300[0x580];
8575
8576	u8 pas[][0x40];
8577	};
8578
8579	struct mlx5_ifc_create_tis_out_bits {
8580	u8 status[0x8];
8581	u8 reserved_at_8[0x18];
8582
8583	u8 syndrome[0x20];
8584
8585	u8 reserved_at_40[0x8];
8586	u8 tisn[0x18];
8587
8588	u8 reserved_at_60[0x20];
8589	};
8590
8591	struct mlx5_ifc_create_tis_in_bits {
8592	u8 opcode[0x10];
8593	u8 uid[0x10];
8594
8595	u8 reserved_at_20[0x10];
8596	u8 op_mod[0x10];
8597
8598	u8 reserved_at_40[0xc0];
8599
8600	struct mlx5_ifc_tisc_bits ctx;
8601	};
8602
8603	struct mlx5_ifc_create_tir_out_bits {
8604	u8 status[0x8];
8605	u8 icm_address_63_40[0x18];
8606
8607	u8 syndrome[0x20];
8608
8609	u8 icm_address_39_32[0x8];
8610	u8 tirn[0x18];
8611
8612	u8 icm_address_31_0[0x20];
8613	};
8614
8615	struct mlx5_ifc_create_tir_in_bits {
8616	u8 opcode[0x10];
8617	u8 uid[0x10];
8618
8619	u8 reserved_at_20[0x10];
8620	u8 op_mod[0x10];
8621
8622	u8 reserved_at_40[0xc0];
8623
8624	struct mlx5_ifc_tirc_bits ctx;
8625	};
8626
8627	struct mlx5_ifc_create_srq_out_bits {
8628	u8 status[0x8];
8629	u8 reserved_at_8[0x18];
8630
8631	u8 syndrome[0x20];
8632
8633	u8 reserved_at_40[0x8];
8634	u8 srqn[0x18];
8635
8636	u8 reserved_at_60[0x20];
8637	};
8638
8639	struct mlx5_ifc_create_srq_in_bits {
8640	u8 opcode[0x10];
8641	u8 uid[0x10];
8642
8643	u8 reserved_at_20[0x10];
8644	u8 op_mod[0x10];
8645
8646	u8 reserved_at_40[0x40];
8647
8648	struct mlx5_ifc_srqc_bits srq_context_entry;
8649
8650	u8 reserved_at_280[0x600];
8651
8652	u8 pas[][0x40];
8653	};
8654
8655	struct mlx5_ifc_create_sq_out_bits {
8656	u8 status[0x8];
8657	u8 reserved_at_8[0x18];
8658
8659	u8 syndrome[0x20];
8660
8661	u8 reserved_at_40[0x8];
8662	u8 sqn[0x18];
8663
8664	u8 reserved_at_60[0x20];
8665	};
8666
8667	struct mlx5_ifc_create_sq_in_bits {
8668	u8 opcode[0x10];
8669	u8 uid[0x10];
8670
8671	u8 reserved_at_20[0x10];
8672	u8 op_mod[0x10];
8673
8674	u8 reserved_at_40[0xc0];
8675
8676	struct mlx5_ifc_sqc_bits ctx;
8677	};
8678
8679	struct mlx5_ifc_create_scheduling_element_out_bits {
8680	u8 status[0x8];
8681	u8 reserved_at_8[0x18];
8682
8683	u8 syndrome[0x20];
8684
8685	u8 reserved_at_40[0x40];
8686
8687	u8 scheduling_element_id[0x20];
8688
8689	u8 reserved_at_a0[0x160];
8690	};
8691
8692	struct mlx5_ifc_create_scheduling_element_in_bits {
8693	u8 opcode[0x10];
8694	u8 reserved_at_10[0x10];
8695
8696	u8 reserved_at_20[0x10];
8697	u8 op_mod[0x10];
8698
8699	u8 scheduling_hierarchy[0x8];
8700	u8 reserved_at_48[0x18];
8701
8702	u8 reserved_at_60[0xa0];
8703
8704	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8705
8706	u8 reserved_at_300[0x100];
8707	};
8708
8709	struct mlx5_ifc_create_rqt_out_bits {
8710	u8 status[0x8];
8711	u8 reserved_at_8[0x18];
8712
8713	u8 syndrome[0x20];
8714
8715	u8 reserved_at_40[0x8];
8716	u8 rqtn[0x18];
8717
8718	u8 reserved_at_60[0x20];
8719	};
8720
8721	struct mlx5_ifc_create_rqt_in_bits {
8722	u8 opcode[0x10];
8723	u8 uid[0x10];
8724
8725	u8 reserved_at_20[0x10];
8726	u8 op_mod[0x10];
8727
8728	u8 reserved_at_40[0xc0];
8729
8730	struct mlx5_ifc_rqtc_bits rqt_context;
8731	};
8732
8733	struct mlx5_ifc_create_rq_out_bits {
8734	u8 status[0x8];
8735	u8 reserved_at_8[0x18];
8736
8737	u8 syndrome[0x20];
8738
8739	u8 reserved_at_40[0x8];
8740	u8 rqn[0x18];
8741
8742	u8 reserved_at_60[0x20];
8743	};
8744
8745	struct mlx5_ifc_create_rq_in_bits {
8746	u8 opcode[0x10];
8747	u8 uid[0x10];
8748
8749	u8 reserved_at_20[0x10];
8750	u8 op_mod[0x10];
8751
8752	u8 reserved_at_40[0xc0];
8753
8754	struct mlx5_ifc_rqc_bits ctx;
8755	};
8756
8757	struct mlx5_ifc_create_rmp_out_bits {
8758	u8 status[0x8];
8759	u8 reserved_at_8[0x18];
8760
8761	u8 syndrome[0x20];
8762
8763	u8 reserved_at_40[0x8];
8764	u8 rmpn[0x18];
8765
8766	u8 reserved_at_60[0x20];
8767	};
8768
8769	struct mlx5_ifc_create_rmp_in_bits {
8770	u8 opcode[0x10];
8771	u8 uid[0x10];
8772
8773	u8 reserved_at_20[0x10];
8774	u8 op_mod[0x10];
8775
8776	u8 reserved_at_40[0xc0];
8777
8778	struct mlx5_ifc_rmpc_bits ctx;
8779	};
8780
8781	struct mlx5_ifc_create_qp_out_bits {
8782	u8 status[0x8];
8783	u8 reserved_at_8[0x18];
8784
8785	u8 syndrome[0x20];
8786
8787	u8 reserved_at_40[0x8];
8788	u8 qpn[0x18];
8789
8790	u8 ece[0x20];
8791	};
8792
8793	struct mlx5_ifc_create_qp_in_bits {
8794	u8 opcode[0x10];
8795	u8 uid[0x10];
8796
8797	u8 reserved_at_20[0x10];
8798	u8 op_mod[0x10];
8799
8800	u8 qpc_ext[0x1];
8801	u8 reserved_at_41[0x7];
8802	u8 input_qpn[0x18];
8803
8804	u8 reserved_at_60[0x20];
8805	u8 opt_param_mask[0x20];
8806
8807	u8 ece[0x20];
8808
8809	struct mlx5_ifc_qpc_bits qpc;
8810
8811	u8 reserved_at_800[0x60];
8812
8813	u8 wq_umem_valid[0x1];
8814	u8 reserved_at_861[0x1f];
8815
8816	u8 pas[][0x40];
8817	};
8818
8819	struct mlx5_ifc_create_psv_out_bits {
8820	u8 status[0x8];
8821	u8 reserved_at_8[0x18];
8822
8823	u8 syndrome[0x20];
8824
8825	u8 reserved_at_40[0x40];
8826
8827	u8 reserved_at_80[0x8];
8828	u8 psv0_index[0x18];
8829
8830	u8 reserved_at_a0[0x8];
8831	u8 psv1_index[0x18];
8832
8833	u8 reserved_at_c0[0x8];
8834	u8 psv2_index[0x18];
8835
8836	u8 reserved_at_e0[0x8];
8837	u8 psv3_index[0x18];
8838	};
8839
8840	struct mlx5_ifc_create_psv_in_bits {
8841	u8 opcode[0x10];
8842	u8 reserved_at_10[0x10];
8843
8844	u8 reserved_at_20[0x10];
8845	u8 op_mod[0x10];
8846
8847	u8 num_psv[0x4];
8848	u8 reserved_at_44[0x4];
8849	u8 pd[0x18];
8850
8851	u8 reserved_at_60[0x20];
8852	};
8853
8854	struct mlx5_ifc_create_mkey_out_bits {
8855	u8 status[0x8];
8856	u8 reserved_at_8[0x18];
8857
8858	u8 syndrome[0x20];
8859
8860	u8 reserved_at_40[0x8];
8861	u8 mkey_index[0x18];
8862
8863	u8 reserved_at_60[0x20];
8864	};
8865
8866	struct mlx5_ifc_create_mkey_in_bits {
8867	u8 opcode[0x10];
8868	u8 uid[0x10];
8869
8870	u8 reserved_at_20[0x10];
8871	u8 op_mod[0x10];
8872
8873	u8 reserved_at_40[0x20];
8874
8875	u8 pg_access[0x1];
8876	u8 mkey_umem_valid[0x1];
8877	u8 reserved_at_62[0x1e];
8878
8879	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8880
8881	u8 reserved_at_280[0x80];
8882
8883	u8 translations_octword_actual_size[0x20];
8884
8885	u8 reserved_at_320[0x560];
8886
8887	u8 klm_pas_mtt[][0x20];
8888	};
8889
8890	enum {
8891	MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8892	MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8893	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8894	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8895	MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8896	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8897	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8898	};
8899
8900	struct mlx5_ifc_create_flow_table_out_bits {
8901	u8 status[0x8];
8902	u8 icm_address_63_40[0x18];
8903
8904	u8 syndrome[0x20];
8905
8906	u8 icm_address_39_32[0x8];
8907	u8 table_id[0x18];
8908
8909	u8 icm_address_31_0[0x20];
8910	};
8911
8912	struct mlx5_ifc_create_flow_table_in_bits {
8913	u8 opcode[0x10];
8914	u8 uid[0x10];
8915
8916	u8 reserved_at_20[0x10];
8917	u8 op_mod[0x10];
8918
8919	u8 other_vport[0x1];
8920	u8 reserved_at_41[0xf];
8921	u8 vport_number[0x10];
8922
8923	u8 reserved_at_60[0x20];
8924
8925	u8 table_type[0x8];
8926	u8 reserved_at_88[0x18];
8927
8928	u8 reserved_at_a0[0x20];
8929
8930	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8931	};
8932
8933	struct mlx5_ifc_create_flow_group_out_bits {
8934	u8 status[0x8];
8935	u8 reserved_at_8[0x18];
8936
8937	u8 syndrome[0x20];
8938
8939	u8 reserved_at_40[0x8];
8940	u8 group_id[0x18];
8941
8942	u8 reserved_at_60[0x20];
8943	};
8944
8945	enum {
8946	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8947	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8948	};
8949
8950	enum {
8951	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8952	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8953	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8954	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8955	};
8956
8957	struct mlx5_ifc_create_flow_group_in_bits {
8958	u8 opcode[0x10];
8959	u8 reserved_at_10[0x10];
8960
8961	u8 reserved_at_20[0x10];
8962	u8 op_mod[0x10];
8963
8964	u8 other_vport[0x1];
8965	u8 reserved_at_41[0xf];
8966	u8 vport_number[0x10];
8967
8968	u8 reserved_at_60[0x20];
8969
8970	u8 table_type[0x8];
8971	u8 reserved_at_88[0x4];
8972	u8 group_type[0x4];
8973	u8 reserved_at_90[0x10];
8974
8975	u8 reserved_at_a0[0x8];
8976	u8 table_id[0x18];
8977
8978	u8 source_eswitch_owner_vhca_id_valid[0x1];
8979
8980	u8 reserved_at_c1[0x1f];
8981
8982	u8 start_flow_index[0x20];
8983
8984	u8 reserved_at_100[0x20];
8985
8986	u8 end_flow_index[0x20];
8987
8988	u8 reserved_at_140[0x10];
8989	u8 match_definer_id[0x10];
8990
8991	u8 reserved_at_160[0x80];
8992
8993	u8 reserved_at_1e0[0x18];
8994	u8 match_criteria_enable[0x8];
8995
8996	struct mlx5_ifc_fte_match_param_bits match_criteria;
8997
8998	u8 reserved_at_1200[0xe00];
8999	};
9000
9001	struct mlx5_ifc_create_eq_out_bits {
9002	u8 status[0x8];
9003	u8 reserved_at_8[0x18];
9004
9005	u8 syndrome[0x20];
9006
9007	u8 reserved_at_40[0x18];
9008	u8 eq_number[0x8];
9009
9010	u8 reserved_at_60[0x20];
9011	};
9012
9013	struct mlx5_ifc_create_eq_in_bits {
9014	u8 opcode[0x10];
9015	u8 uid[0x10];
9016
9017	u8 reserved_at_20[0x10];
9018	u8 op_mod[0x10];
9019
9020	u8 reserved_at_40[0x40];
9021
9022	struct mlx5_ifc_eqc_bits eq_context_entry;
9023
9024	u8 reserved_at_280[0x40];
9025
9026	u8 event_bitmask[4][0x40];
9027
9028	u8 reserved_at_3c0[0x4c0];
9029
9030	u8 pas[][0x40];
9031	};
9032
9033	struct mlx5_ifc_create_dct_out_bits {
9034	u8 status[0x8];
9035	u8 reserved_at_8[0x18];
9036
9037	u8 syndrome[0x20];
9038
9039	u8 reserved_at_40[0x8];
9040	u8 dctn[0x18];
9041
9042	u8 ece[0x20];
9043	};
9044
9045	struct mlx5_ifc_create_dct_in_bits {
9046	u8 opcode[0x10];
9047	u8 uid[0x10];
9048
9049	u8 reserved_at_20[0x10];
9050	u8 op_mod[0x10];
9051
9052	u8 reserved_at_40[0x40];
9053
9054	struct mlx5_ifc_dctc_bits dct_context_entry;
9055
9056	u8 reserved_at_280[0x180];
9057	};
9058
9059	struct mlx5_ifc_create_cq_out_bits {
9060	u8 status[0x8];
9061	u8 reserved_at_8[0x18];
9062
9063	u8 syndrome[0x20];
9064
9065	u8 reserved_at_40[0x8];
9066	u8 cqn[0x18];
9067
9068	u8 reserved_at_60[0x20];
9069	};
9070
9071	struct mlx5_ifc_create_cq_in_bits {
9072	u8 opcode[0x10];
9073	u8 uid[0x10];
9074
9075	u8 reserved_at_20[0x10];
9076	u8 op_mod[0x10];
9077
9078	u8 reserved_at_40[0x40];
9079
9080	struct mlx5_ifc_cqc_bits cq_context;
9081
9082	u8 reserved_at_280[0x60];
9083
9084	u8 cq_umem_valid[0x1];
9085	u8 reserved_at_2e1[0x59f];
9086
9087	u8 pas[][0x40];
9088	};
9089
9090	struct mlx5_ifc_config_int_moderation_out_bits {
9091	u8 status[0x8];
9092	u8 reserved_at_8[0x18];
9093
9094	u8 syndrome[0x20];
9095
9096	u8 reserved_at_40[0x4];
9097	u8 min_delay[0xc];
9098	u8 int_vector[0x10];
9099
9100	u8 reserved_at_60[0x20];
9101	};
9102
9103	enum {
9104	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
9105	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
9106	};
9107
9108	struct mlx5_ifc_config_int_moderation_in_bits {
9109	u8 opcode[0x10];
9110	u8 reserved_at_10[0x10];
9111
9112	u8 reserved_at_20[0x10];
9113	u8 op_mod[0x10];
9114
9115	u8 reserved_at_40[0x4];
9116	u8 min_delay[0xc];
9117	u8 int_vector[0x10];
9118
9119	u8 reserved_at_60[0x20];
9120	};
9121
9122	struct mlx5_ifc_attach_to_mcg_out_bits {
9123	u8 status[0x8];
9124	u8 reserved_at_8[0x18];
9125
9126	u8 syndrome[0x20];
9127
9128	u8 reserved_at_40[0x40];
9129	};
9130
9131	struct mlx5_ifc_attach_to_mcg_in_bits {
9132	u8 opcode[0x10];
9133	u8 uid[0x10];
9134
9135	u8 reserved_at_20[0x10];
9136	u8 op_mod[0x10];
9137
9138	u8 reserved_at_40[0x8];
9139	u8 qpn[0x18];
9140
9141	u8 reserved_at_60[0x20];
9142
9143	u8 multicast_gid[16][0x8];
9144	};
9145
9146	struct mlx5_ifc_arm_xrq_out_bits {
9147	u8 status[0x8];
9148	u8 reserved_at_8[0x18];
9149
9150	u8 syndrome[0x20];
9151
9152	u8 reserved_at_40[0x40];
9153	};
9154
9155	struct mlx5_ifc_arm_xrq_in_bits {
9156	u8 opcode[0x10];
9157	u8 reserved_at_10[0x10];
9158
9159	u8 reserved_at_20[0x10];
9160	u8 op_mod[0x10];
9161
9162	u8 reserved_at_40[0x8];
9163	u8 xrqn[0x18];
9164
9165	u8 reserved_at_60[0x10];
9166	u8 lwm[0x10];
9167	};
9168
9169	struct mlx5_ifc_arm_xrc_srq_out_bits {
9170	u8 status[0x8];
9171	u8 reserved_at_8[0x18];
9172
9173	u8 syndrome[0x20];
9174
9175	u8 reserved_at_40[0x40];
9176	};
9177
9178	enum {
9179	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
9180	};
9181
9182	struct mlx5_ifc_arm_xrc_srq_in_bits {
9183	u8 opcode[0x10];
9184	u8 uid[0x10];
9185
9186	u8 reserved_at_20[0x10];
9187	u8 op_mod[0x10];
9188
9189	u8 reserved_at_40[0x8];
9190	u8 xrc_srqn[0x18];
9191
9192	u8 reserved_at_60[0x10];
9193	u8 lwm[0x10];
9194	};
9195
9196	struct mlx5_ifc_arm_rq_out_bits {
9197	u8 status[0x8];
9198	u8 reserved_at_8[0x18];
9199
9200	u8 syndrome[0x20];
9201
9202	u8 reserved_at_40[0x40];
9203	};
9204
9205	enum {
9206	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9207	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9208	};
9209
9210	struct mlx5_ifc_arm_rq_in_bits {
9211	u8 opcode[0x10];
9212	u8 uid[0x10];
9213
9214	u8 reserved_at_20[0x10];
9215	u8 op_mod[0x10];
9216
9217	u8 reserved_at_40[0x8];
9218	u8 srq_number[0x18];
9219
9220	u8 reserved_at_60[0x10];
9221	u8 lwm[0x10];
9222	};
9223
9224	struct mlx5_ifc_arm_dct_out_bits {
9225	u8 status[0x8];
9226	u8 reserved_at_8[0x18];
9227
9228	u8 syndrome[0x20];
9229
9230	u8 reserved_at_40[0x40];
9231	};
9232
9233	struct mlx5_ifc_arm_dct_in_bits {
9234	u8 opcode[0x10];
9235	u8 reserved_at_10[0x10];
9236
9237	u8 reserved_at_20[0x10];
9238	u8 op_mod[0x10];
9239
9240	u8 reserved_at_40[0x8];
9241	u8 dct_number[0x18];
9242
9243	u8 reserved_at_60[0x20];
9244	};
9245
9246	struct mlx5_ifc_alloc_xrcd_out_bits {
9247	u8 status[0x8];
9248	u8 reserved_at_8[0x18];
9249
9250	u8 syndrome[0x20];
9251
9252	u8 reserved_at_40[0x8];
9253	u8 xrcd[0x18];
9254
9255	u8 reserved_at_60[0x20];
9256	};
9257
9258	struct mlx5_ifc_alloc_xrcd_in_bits {
9259	u8 opcode[0x10];
9260	u8 uid[0x10];
9261
9262	u8 reserved_at_20[0x10];
9263	u8 op_mod[0x10];
9264
9265	u8 reserved_at_40[0x40];
9266	};
9267
9268	struct mlx5_ifc_alloc_uar_out_bits {
9269	u8 status[0x8];
9270	u8 reserved_at_8[0x18];
9271
9272	u8 syndrome[0x20];
9273
9274	u8 reserved_at_40[0x8];
9275	u8 uar[0x18];
9276
9277	u8 reserved_at_60[0x20];
9278	};
9279
9280	struct mlx5_ifc_alloc_uar_in_bits {
9281	u8 opcode[0x10];
9282	u8 uid[0x10];
9283
9284	u8 reserved_at_20[0x10];
9285	u8 op_mod[0x10];
9286
9287	u8 reserved_at_40[0x40];
9288	};
9289
9290	struct mlx5_ifc_alloc_transport_domain_out_bits {
9291	u8 status[0x8];
9292	u8 reserved_at_8[0x18];
9293
9294	u8 syndrome[0x20];
9295
9296	u8 reserved_at_40[0x8];
9297	u8 transport_domain[0x18];
9298
9299	u8 reserved_at_60[0x20];
9300	};
9301
9302	struct mlx5_ifc_alloc_transport_domain_in_bits {
9303	u8 opcode[0x10];
9304	u8 uid[0x10];
9305
9306	u8 reserved_at_20[0x10];
9307	u8 op_mod[0x10];
9308
9309	u8 reserved_at_40[0x40];
9310	};
9311
9312	struct mlx5_ifc_alloc_q_counter_out_bits {
9313	u8 status[0x8];
9314	u8 reserved_at_8[0x18];
9315
9316	u8 syndrome[0x20];
9317
9318	u8 reserved_at_40[0x18];
9319	u8 counter_set_id[0x8];
9320
9321	u8 reserved_at_60[0x20];
9322	};
9323
9324	struct mlx5_ifc_alloc_q_counter_in_bits {
9325	u8 opcode[0x10];
9326	u8 uid[0x10];
9327
9328	u8 reserved_at_20[0x10];
9329	u8 op_mod[0x10];
9330
9331	u8 reserved_at_40[0x40];
9332	};
9333
9334	struct mlx5_ifc_alloc_pd_out_bits {
9335	u8 status[0x8];
9336	u8 reserved_at_8[0x18];
9337
9338	u8 syndrome[0x20];
9339
9340	u8 reserved_at_40[0x8];
9341	u8 pd[0x18];
9342
9343	u8 reserved_at_60[0x20];
9344	};
9345
9346	struct mlx5_ifc_alloc_pd_in_bits {
9347	u8 opcode[0x10];
9348	u8 uid[0x10];
9349
9350	u8 reserved_at_20[0x10];
9351	u8 op_mod[0x10];
9352
9353	u8 reserved_at_40[0x40];
9354	};
9355
9356	struct mlx5_ifc_alloc_flow_counter_out_bits {
9357	u8 status[0x8];
9358	u8 reserved_at_8[0x18];
9359
9360	u8 syndrome[0x20];
9361
9362	u8 flow_counter_id[0x20];
9363
9364	u8 reserved_at_60[0x20];
9365	};
9366
9367	struct mlx5_ifc_alloc_flow_counter_in_bits {
9368	u8 opcode[0x10];
9369	u8 reserved_at_10[0x10];
9370
9371	u8 reserved_at_20[0x10];
9372	u8 op_mod[0x10];
9373
9374	u8 reserved_at_40[0x33];
9375	u8 flow_counter_bulk_log_size[0x5];
9376	u8 flow_counter_bulk[0x8];
9377	};
9378
9379	struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9380	u8 status[0x8];
9381	u8 reserved_at_8[0x18];
9382
9383	u8 syndrome[0x20];
9384
9385	u8 reserved_at_40[0x40];
9386	};
9387
9388	struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9389	u8 opcode[0x10];
9390	u8 reserved_at_10[0x10];
9391
9392	u8 reserved_at_20[0x10];
9393	u8 op_mod[0x10];
9394
9395	u8 reserved_at_40[0x20];
9396
9397	u8 reserved_at_60[0x10];
9398	u8 vxlan_udp_port[0x10];
9399	};
9400
9401	struct mlx5_ifc_set_pp_rate_limit_out_bits {
9402	u8 status[0x8];
9403	u8 reserved_at_8[0x18];
9404
9405	u8 syndrome[0x20];
9406
9407	u8 reserved_at_40[0x40];
9408	};
9409
9410	struct mlx5_ifc_set_pp_rate_limit_context_bits {
9411	u8 rate_limit[0x20];
9412
9413	u8 burst_upper_bound[0x20];
9414
9415	u8 reserved_at_40[0x10];
9416	u8 typical_packet_size[0x10];
9417
9418	u8 reserved_at_60[0x120];
9419	};
9420
9421	struct mlx5_ifc_set_pp_rate_limit_in_bits {
9422	u8 opcode[0x10];
9423	u8 uid[0x10];
9424
9425	u8 reserved_at_20[0x10];
9426	u8 op_mod[0x10];
9427
9428	u8 reserved_at_40[0x10];
9429	u8 rate_limit_index[0x10];
9430
9431	u8 reserved_at_60[0x20];
9432
9433	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9434	};
9435
9436	struct mlx5_ifc_access_register_out_bits {
9437	u8 status[0x8];
9438	u8 reserved_at_8[0x18];
9439
9440	u8 syndrome[0x20];
9441
9442	u8 reserved_at_40[0x40];
9443
9444	u8 register_data[][0x20];
9445	};
9446
9447	enum {
9448	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9449	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9450	};
9451
9452	struct mlx5_ifc_access_register_in_bits {
9453	u8 opcode[0x10];
9454	u8 reserved_at_10[0x10];
9455
9456	u8 reserved_at_20[0x10];
9457	u8 op_mod[0x10];
9458
9459	u8 reserved_at_40[0x10];
9460	u8 register_id[0x10];
9461
9462	u8 argument[0x20];
9463
9464	u8 register_data[][0x20];
9465	};
9466
9467	struct mlx5_ifc_sltp_reg_bits {
9468	u8 status[0x4];
9469	u8 version[0x4];
9470	u8 local_port[0x8];
9471	u8 pnat[0x2];
9472	u8 reserved_at_12[0x2];
9473	u8 lane[0x4];
9474	u8 reserved_at_18[0x8];
9475
9476	u8 reserved_at_20[0x20];
9477
9478	u8 reserved_at_40[0x7];
9479	u8 polarity[0x1];
9480	u8 ob_tap0[0x8];
9481	u8 ob_tap1[0x8];
9482	u8 ob_tap2[0x8];
9483
9484	u8 reserved_at_60[0xc];
9485	u8 ob_preemp_mode[0x4];
9486	u8 ob_reg[0x8];
9487	u8 ob_bias[0x8];
9488
9489	u8 reserved_at_80[0x20];
9490	};
9491
9492	struct mlx5_ifc_slrg_reg_bits {
9493	u8 status[0x4];
9494	u8 version[0x4];
9495	u8 local_port[0x8];
9496	u8 pnat[0x2];
9497	u8 reserved_at_12[0x2];
9498	u8 lane[0x4];
9499	u8 reserved_at_18[0x8];
9500
9501	u8 time_to_link_up[0x10];
9502	u8 reserved_at_30[0xc];
9503	u8 grade_lane_speed[0x4];
9504
9505	u8 grade_version[0x8];
9506	u8 grade[0x18];
9507
9508	u8 reserved_at_60[0x4];
9509	u8 height_grade_type[0x4];
9510	u8 height_grade[0x18];
9511
9512	u8 height_dz[0x10];
9513	u8 height_dv[0x10];
9514
9515	u8 reserved_at_a0[0x10];
9516	u8 height_sigma[0x10];
9517
9518	u8 reserved_at_c0[0x20];
9519
9520	u8 reserved_at_e0[0x4];
9521	u8 phase_grade_type[0x4];
9522	u8 phase_grade[0x18];
9523
9524	u8 reserved_at_100[0x8];
9525	u8 phase_eo_pos[0x8];
9526	u8 reserved_at_110[0x8];
9527	u8 phase_eo_neg[0x8];
9528
9529	u8 ffe_set_tested[0x10];
9530	u8 test_errors_per_lane[0x10];
9531	};
9532
9533	struct mlx5_ifc_pvlc_reg_bits {
9534	u8 reserved_at_0[0x8];
9535	u8 local_port[0x8];
9536	u8 reserved_at_10[0x10];
9537
9538	u8 reserved_at_20[0x1c];
9539	u8 vl_hw_cap[0x4];
9540
9541	u8 reserved_at_40[0x1c];
9542	u8 vl_admin[0x4];
9543
9544	u8 reserved_at_60[0x1c];
9545	u8 vl_operational[0x4];
9546	};
9547
9548	struct mlx5_ifc_pude_reg_bits {
9549	u8 swid[0x8];
9550	u8 local_port[0x8];
9551	u8 reserved_at_10[0x4];
9552	u8 admin_status[0x4];
9553	u8 reserved_at_18[0x4];
9554	u8 oper_status[0x4];
9555
9556	u8 reserved_at_20[0x60];
9557	};
9558
9559	struct mlx5_ifc_ptys_reg_bits {
9560	u8 reserved_at_0[0x1];
9561	u8 an_disable_admin[0x1];
9562	u8 an_disable_cap[0x1];
9563	u8 reserved_at_3[0x5];
9564	u8 local_port[0x8];
9565	u8 reserved_at_10[0xd];
9566	u8 proto_mask[0x3];
9567
9568	u8 an_status[0x4];
9569	u8 reserved_at_24[0xc];
9570	u8 data_rate_oper[0x10];
9571
9572	u8 ext_eth_proto_capability[0x20];
9573
9574	u8 eth_proto_capability[0x20];
9575
9576	u8 ib_link_width_capability[0x10];
9577	u8 ib_proto_capability[0x10];
9578
9579	u8 ext_eth_proto_admin[0x20];
9580
9581	u8 eth_proto_admin[0x20];
9582
9583	u8 ib_link_width_admin[0x10];
9584	u8 ib_proto_admin[0x10];
9585
9586	u8 ext_eth_proto_oper[0x20];
9587
9588	u8 eth_proto_oper[0x20];
9589
9590	u8 ib_link_width_oper[0x10];
9591	u8 ib_proto_oper[0x10];
9592
9593	u8 reserved_at_160[0x1c];
9594	u8 connector_type[0x4];
9595
9596	u8 eth_proto_lp_advertise[0x20];
9597
9598	u8 reserved_at_1a0[0x60];
9599	};
9600
9601	struct mlx5_ifc_mlcr_reg_bits {
9602	u8 reserved_at_0[0x8];
9603	u8 local_port[0x8];
9604	u8 reserved_at_10[0x20];
9605
9606	u8 beacon_duration[0x10];
9607	u8 reserved_at_40[0x10];
9608
9609	u8 beacon_remain[0x10];
9610	};
9611
9612	struct mlx5_ifc_ptas_reg_bits {
9613	u8 reserved_at_0[0x20];
9614
9615	u8 algorithm_options[0x10];
9616	u8 reserved_at_30[0x4];
9617	u8 repetitions_mode[0x4];
9618	u8 num_of_repetitions[0x8];
9619
9620	u8 grade_version[0x8];
9621	u8 height_grade_type[0x4];
9622	u8 phase_grade_type[0x4];
9623	u8 height_grade_weight[0x8];
9624	u8 phase_grade_weight[0x8];
9625
9626	u8 gisim_measure_bits[0x10];
9627	u8 adaptive_tap_measure_bits[0x10];
9628
9629	u8 ber_bath_high_error_threshold[0x10];
9630	u8 ber_bath_mid_error_threshold[0x10];
9631
9632	u8 ber_bath_low_error_threshold[0x10];
9633	u8 one_ratio_high_threshold[0x10];
9634
9635	u8 one_ratio_high_mid_threshold[0x10];
9636	u8 one_ratio_low_mid_threshold[0x10];
9637
9638	u8 one_ratio_low_threshold[0x10];
9639	u8 ndeo_error_threshold[0x10];
9640
9641	u8 mixer_offset_step_size[0x10];
9642	u8 reserved_at_110[0x8];
9643	u8 mix90_phase_for_voltage_bath[0x8];
9644
9645	u8 mixer_offset_start[0x10];
9646	u8 mixer_offset_end[0x10];
9647
9648	u8 reserved_at_140[0x15];
9649	u8 ber_test_time[0xb];
9650	};
9651
9652	struct mlx5_ifc_pspa_reg_bits {
9653	u8 swid[0x8];
9654	u8 local_port[0x8];
9655	u8 sub_port[0x8];
9656	u8 reserved_at_18[0x8];
9657
9658	u8 reserved_at_20[0x20];
9659	};
9660
9661	struct mlx5_ifc_pqdr_reg_bits {
9662	u8 reserved_at_0[0x8];
9663	u8 local_port[0x8];
9664	u8 reserved_at_10[0x5];
9665	u8 prio[0x3];
9666	u8 reserved_at_18[0x6];
9667	u8 mode[0x2];
9668
9669	u8 reserved_at_20[0x20];
9670
9671	u8 reserved_at_40[0x10];
9672	u8 min_threshold[0x10];
9673
9674	u8 reserved_at_60[0x10];
9675	u8 max_threshold[0x10];
9676
9677	u8 reserved_at_80[0x10];
9678	u8 mark_probability_denominator[0x10];
9679
9680	u8 reserved_at_a0[0x60];
9681	};
9682
9683	struct mlx5_ifc_ppsc_reg_bits {
9684	u8 reserved_at_0[0x8];
9685	u8 local_port[0x8];
9686	u8 reserved_at_10[0x10];
9687
9688	u8 reserved_at_20[0x60];
9689
9690	u8 reserved_at_80[0x1c];
9691	u8 wrps_admin[0x4];
9692
9693	u8 reserved_at_a0[0x1c];
9694	u8 wrps_status[0x4];
9695
9696	u8 reserved_at_c0[0x8];
9697	u8 up_threshold[0x8];
9698	u8 reserved_at_d0[0x8];
9699	u8 down_threshold[0x8];
9700
9701	u8 reserved_at_e0[0x20];
9702
9703	u8 reserved_at_100[0x1c];
9704	u8 srps_admin[0x4];
9705
9706	u8 reserved_at_120[0x1c];
9707	u8 srps_status[0x4];
9708
9709	u8 reserved_at_140[0x40];
9710	};
9711
9712	struct mlx5_ifc_pplr_reg_bits {
9713	u8 reserved_at_0[0x8];
9714	u8 local_port[0x8];
9715	u8 reserved_at_10[0x10];
9716
9717	u8 reserved_at_20[0x8];
9718	u8 lb_cap[0x8];
9719	u8 reserved_at_30[0x8];
9720	u8 lb_en[0x8];
9721	};
9722
9723	struct mlx5_ifc_pplm_reg_bits {
9724	u8 reserved_at_0[0x8];
9725	u8 local_port[0x8];
9726	u8 reserved_at_10[0x10];
9727
9728	u8 reserved_at_20[0x20];
9729
9730	u8 port_profile_mode[0x8];
9731	u8 static_port_profile[0x8];
9732	u8 active_port_profile[0x8];
9733	u8 reserved_at_58[0x8];
9734
9735	u8 retransmission_active[0x8];
9736	u8 fec_mode_active[0x18];
9737
9738	u8 rs_fec_correction_bypass_cap[0x4];
9739	u8 reserved_at_84[0x8];
9740	u8 fec_override_cap_56g[0x4];
9741	u8 fec_override_cap_100g[0x4];
9742	u8 fec_override_cap_50g[0x4];
9743	u8 fec_override_cap_25g[0x4];
9744	u8 fec_override_cap_10g_40g[0x4];
9745
9746	u8 rs_fec_correction_bypass_admin[0x4];
9747	u8 reserved_at_a4[0x8];
9748	u8 fec_override_admin_56g[0x4];
9749	u8 fec_override_admin_100g[0x4];
9750	u8 fec_override_admin_50g[0x4];
9751	u8 fec_override_admin_25g[0x4];
9752	u8 fec_override_admin_10g_40g[0x4];
9753
9754	u8 fec_override_cap_400g_8x[0x10];
9755	u8 fec_override_cap_200g_4x[0x10];
9756
9757	u8 fec_override_cap_100g_2x[0x10];
9758	u8 fec_override_cap_50g_1x[0x10];
9759
9760	u8 fec_override_admin_400g_8x[0x10];
9761	u8 fec_override_admin_200g_4x[0x10];
9762
9763	u8 fec_override_admin_100g_2x[0x10];
9764	u8 fec_override_admin_50g_1x[0x10];
9765
9766	u8 reserved_at_140[0x140];
9767	};
9768
9769	struct mlx5_ifc_ppcnt_reg_bits {
9770	u8 swid[0x8];
9771	u8 local_port[0x8];
9772	u8 pnat[0x2];
9773	u8 reserved_at_12[0x8];
9774	u8 grp[0x6];
9775
9776	u8 clr[0x1];
9777	u8 reserved_at_21[0x1c];
9778	u8 prio_tc[0x3];
9779
9780	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9781	};
9782
9783	struct mlx5_ifc_mpein_reg_bits {
9784	u8 reserved_at_0[0x2];
9785	u8 depth[0x6];
9786	u8 pcie_index[0x8];
9787	u8 node[0x8];
9788	u8 reserved_at_18[0x8];
9789
9790	u8 capability_mask[0x20];
9791
9792	u8 reserved_at_40[0x8];
9793	u8 link_width_enabled[0x8];
9794	u8 link_speed_enabled[0x10];
9795
9796	u8 lane0_physical_position[0x8];
9797	u8 link_width_active[0x8];
9798	u8 link_speed_active[0x10];
9799
9800	u8 num_of_pfs[0x10];
9801	u8 num_of_vfs[0x10];
9802
9803	u8 bdf0[0x10];
9804	u8 reserved_at_b0[0x10];
9805
9806	u8 max_read_request_size[0x4];
9807	u8 max_payload_size[0x4];
9808	u8 reserved_at_c8[0x5];
9809	u8 pwr_status[0x3];
9810	u8 port_type[0x4];
9811	u8 reserved_at_d4[0xb];
9812	u8 lane_reversal[0x1];
9813
9814	u8 reserved_at_e0[0x14];
9815	u8 pci_power[0xc];
9816
9817	u8 reserved_at_100[0x20];
9818
9819	u8 device_status[0x10];
9820	u8 port_state[0x8];
9821	u8 reserved_at_138[0x8];
9822
9823	u8 reserved_at_140[0x10];
9824	u8 receiver_detect_result[0x10];
9825
9826	u8 reserved_at_160[0x20];
9827	};
9828
9829	struct mlx5_ifc_mpcnt_reg_bits {
9830	u8 reserved_at_0[0x8];
9831	u8 pcie_index[0x8];
9832	u8 reserved_at_10[0xa];
9833	u8 grp[0x6];
9834
9835	u8 clr[0x1];
9836	u8 reserved_at_21[0x1f];
9837
9838	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9839	};
9840
9841	struct mlx5_ifc_ppad_reg_bits {
9842	u8 reserved_at_0[0x3];
9843	u8 single_mac[0x1];
9844	u8 reserved_at_4[0x4];
9845	u8 local_port[0x8];
9846	u8 mac_47_32[0x10];
9847
9848	u8 mac_31_0[0x20];
9849
9850	u8 reserved_at_40[0x40];
9851	};
9852
9853	struct mlx5_ifc_pmtu_reg_bits {
9854	u8 reserved_at_0[0x8];
9855	u8 local_port[0x8];
9856	u8 reserved_at_10[0x10];
9857
9858	u8 max_mtu[0x10];
9859	u8 reserved_at_30[0x10];
9860
9861	u8 admin_mtu[0x10];
9862	u8 reserved_at_50[0x10];
9863
9864	u8 oper_mtu[0x10];
9865	u8 reserved_at_70[0x10];
9866	};
9867
9868	struct mlx5_ifc_pmpr_reg_bits {
9869	u8 reserved_at_0[0x8];
9870	u8 module[0x8];
9871	u8 reserved_at_10[0x10];
9872
9873	u8 reserved_at_20[0x18];
9874	u8 attenuation_5g[0x8];
9875
9876	u8 reserved_at_40[0x18];
9877	u8 attenuation_7g[0x8];
9878
9879	u8 reserved_at_60[0x18];
9880	u8 attenuation_12g[0x8];
9881	};
9882
9883	struct mlx5_ifc_pmpe_reg_bits {
9884	u8 reserved_at_0[0x8];
9885	u8 module[0x8];
9886	u8 reserved_at_10[0xc];
9887	u8 module_status[0x4];
9888
9889	u8 reserved_at_20[0x60];
9890	};
9891
9892	struct mlx5_ifc_pmpc_reg_bits {
9893	u8 module_state_updated[32][0x8];
9894	};
9895
9896	struct mlx5_ifc_pmlpn_reg_bits {
9897	u8 reserved_at_0[0x4];
9898	u8 mlpn_status[0x4];
9899	u8 local_port[0x8];
9900	u8 reserved_at_10[0x10];
9901
9902	u8 e[0x1];
9903	u8 reserved_at_21[0x1f];
9904	};
9905
9906	struct mlx5_ifc_pmlp_reg_bits {
9907	u8 rxtx[0x1];
9908	u8 reserved_at_1[0x7];
9909	u8 local_port[0x8];
9910	u8 reserved_at_10[0x8];
9911	u8 width[0x8];
9912
9913	u8 lane0_module_mapping[0x20];
9914
9915	u8 lane1_module_mapping[0x20];
9916
9917	u8 lane2_module_mapping[0x20];
9918
9919	u8 lane3_module_mapping[0x20];
9920
9921	u8 reserved_at_a0[0x160];
9922	};
9923
9924	struct mlx5_ifc_pmaos_reg_bits {
9925	u8 reserved_at_0[0x8];
9926	u8 module[0x8];
9927	u8 reserved_at_10[0x4];
9928	u8 admin_status[0x4];
9929	u8 reserved_at_18[0x4];
9930	u8 oper_status[0x4];
9931
9932	u8 ase[0x1];
9933	u8 ee[0x1];
9934	u8 reserved_at_22[0x1c];
9935	u8 e[0x2];
9936
9937	u8 reserved_at_40[0x40];
9938	};
9939
9940	struct mlx5_ifc_plpc_reg_bits {
9941	u8 reserved_at_0[0x4];
9942	u8 profile_id[0xc];
9943	u8 reserved_at_10[0x4];
9944	u8 proto_mask[0x4];
9945	u8 reserved_at_18[0x8];
9946
9947	u8 reserved_at_20[0x10];
9948	u8 lane_speed[0x10];
9949
9950	u8 reserved_at_40[0x17];
9951	u8 lpbf[0x1];
9952	u8 fec_mode_policy[0x8];
9953
9954	u8 retransmission_capability[0x8];
9955	u8 fec_mode_capability[0x18];
9956
9957	u8 retransmission_support_admin[0x8];
9958	u8 fec_mode_support_admin[0x18];
9959
9960	u8 retransmission_request_admin[0x8];
9961	u8 fec_mode_request_admin[0x18];
9962
9963	u8 reserved_at_c0[0x80];
9964	};
9965
9966	struct mlx5_ifc_plib_reg_bits {
9967	u8 reserved_at_0[0x8];
9968	u8 local_port[0x8];
9969	u8 reserved_at_10[0x8];
9970	u8 ib_port[0x8];
9971
9972	u8 reserved_at_20[0x60];
9973	};
9974
9975	struct mlx5_ifc_plbf_reg_bits {
9976	u8 reserved_at_0[0x8];
9977	u8 local_port[0x8];
9978	u8 reserved_at_10[0xd];
9979	u8 lbf_mode[0x3];
9980
9981	u8 reserved_at_20[0x20];
9982	};
9983
9984	struct mlx5_ifc_pipg_reg_bits {
9985	u8 reserved_at_0[0x8];
9986	u8 local_port[0x8];
9987	u8 reserved_at_10[0x10];
9988
9989	u8 dic[0x1];
9990	u8 reserved_at_21[0x19];
9991	u8 ipg[0x4];
9992	u8 reserved_at_3e[0x2];
9993	};
9994
9995	struct mlx5_ifc_pifr_reg_bits {
9996	u8 reserved_at_0[0x8];
9997	u8 local_port[0x8];
9998	u8 reserved_at_10[0x10];
9999
10000	u8 reserved_at_20[0xe0];
10001
10002	u8 port_filter[8][0x20];
10003
10004	u8 port_filter_update_en[8][0x20];
10005	};
10006
10007	struct mlx5_ifc_pfcc_reg_bits {
10008	u8 reserved_at_0[0x8];
10009	u8 local_port[0x8];
10010	u8 reserved_at_10[0xb];
10011	u8 ppan_mask_n[0x1];
10012	u8 minor_stall_mask[0x1];
10013	u8 critical_stall_mask[0x1];
10014	u8 reserved_at_1e[0x2];
10015
10016	u8 ppan[0x4];
10017	u8 reserved_at_24[0x4];
10018	u8 prio_mask_tx[0x8];
10019	u8 reserved_at_30[0x8];
10020	u8 prio_mask_rx[0x8];
10021
10022	u8 pptx[0x1];
10023	u8 aptx[0x1];
10024	u8 pptx_mask_n[0x1];
10025	u8 reserved_at_43[0x5];
10026	u8 pfctx[0x8];
10027	u8 reserved_at_50[0x10];
10028
10029	u8 pprx[0x1];
10030	u8 aprx[0x1];
10031	u8 pprx_mask_n[0x1];
10032	u8 reserved_at_63[0x5];
10033	u8 pfcrx[0x8];
10034	u8 reserved_at_70[0x10];
10035
10036	u8 device_stall_minor_watermark[0x10];
10037	u8 device_stall_critical_watermark[0x10];
10038
10039	u8 reserved_at_a0[0x60];
10040	};
10041
10042	struct mlx5_ifc_pelc_reg_bits {
10043	u8 op[0x4];
10044	u8 reserved_at_4[0x4];
10045	u8 local_port[0x8];
10046	u8 reserved_at_10[0x10];
10047
10048	u8 op_admin[0x8];
10049	u8 op_capability[0x8];
10050	u8 op_request[0x8];
10051	u8 op_active[0x8];
10052
10053	u8 admin[0x40];
10054
10055	u8 capability[0x40];
10056
10057	u8 request[0x40];
10058
10059	u8 active[0x40];
10060
10061	u8 reserved_at_140[0x80];
10062	};
10063
10064	struct mlx5_ifc_peir_reg_bits {
10065	u8 reserved_at_0[0x8];
10066	u8 local_port[0x8];
10067	u8 reserved_at_10[0x10];
10068
10069	u8 reserved_at_20[0xc];
10070	u8 error_count[0x4];
10071	u8 reserved_at_30[0x10];
10072
10073	u8 reserved_at_40[0xc];
10074	u8 lane[0x4];
10075	u8 reserved_at_50[0x8];
10076	u8 error_type[0x8];
10077	};
10078
10079	struct mlx5_ifc_mpegc_reg_bits {
10080	u8 reserved_at_0[0x30];
10081	u8 field_select[0x10];
10082
10083	u8 tx_overflow_sense[0x1];
10084	u8 mark_cqe[0x1];
10085	u8 mark_cnp[0x1];
10086	u8 reserved_at_43[0x1b];
10087	u8 tx_lossy_overflow_oper[0x2];
10088
10089	u8 reserved_at_60[0x100];
10090	};
10091
10092	enum {
10093	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0,
10094	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1,
10095	};
10096
10097	enum {
10098	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
10099	MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
10100	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
10101	};
10102
10103	struct mlx5_ifc_mtutc_reg_bits {
10104	u8 reserved_at_0[0x5];
10105	u8 freq_adj_units[0x3];
10106	u8 reserved_at_8[0x14];
10107	u8 operation[0x4];
10108
10109	u8 freq_adjustment[0x20];
10110
10111	u8 reserved_at_40[0x40];
10112
10113	u8 utc_sec[0x20];
10114
10115	u8 reserved_at_a0[0x2];
10116	u8 utc_nsec[0x1e];
10117
10118	u8 time_adjustment[0x20];
10119	};
10120
10121	struct mlx5_ifc_pcam_enhanced_features_bits {
10122	u8 reserved_at_0[0x68];
10123	u8 fec_50G_per_lane_in_pplm[0x1];
10124	u8 reserved_at_69[0x4];
10125	u8 rx_icrc_encapsulated_counter[0x1];
10126	u8 reserved_at_6e[0x4];
10127	u8 ptys_extended_ethernet[0x1];
10128	u8 reserved_at_73[0x3];
10129	u8 pfcc_mask[0x1];
10130	u8 reserved_at_77[0x3];
10131	u8 per_lane_error_counters[0x1];
10132	u8 rx_buffer_fullness_counters[0x1];
10133	u8 ptys_connector_type[0x1];
10134	u8 reserved_at_7d[0x1];
10135	u8 ppcnt_discard_group[0x1];
10136	u8 ppcnt_statistical_group[0x1];
10137	};
10138
10139	struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10140	u8 port_access_reg_cap_mask_127_to_96[0x20];
10141	u8 port_access_reg_cap_mask_95_to_64[0x20];
10142
10143	u8 port_access_reg_cap_mask_63_to_36[0x1c];
10144	u8 pplm[0x1];
10145	u8 port_access_reg_cap_mask_34_to_32[0x3];
10146
10147	u8 port_access_reg_cap_mask_31_to_13[0x13];
10148	u8 pbmc[0x1];
10149	u8 pptb[0x1];
10150	u8 port_access_reg_cap_mask_10_to_09[0x2];
10151	u8 ppcnt[0x1];
10152	u8 port_access_reg_cap_mask_07_to_00[0x8];
10153	};
10154
10155	struct mlx5_ifc_pcam_reg_bits {
10156	u8 reserved_at_0[0x8];
10157	u8 feature_group[0x8];
10158	u8 reserved_at_10[0x8];
10159	u8 access_reg_group[0x8];
10160
10161	u8 reserved_at_20[0x20];
10162
10163	union {
10164	struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10165	u8 reserved_at_0[0x80];
10166	} port_access_reg_cap_mask;
10167
10168	u8 reserved_at_c0[0x80];
10169
10170	union {
10171	struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10172	u8 reserved_at_0[0x80];
10173	} feature_cap_mask;
10174
10175	u8 reserved_at_1c0[0xc0];
10176	};
10177
10178	struct mlx5_ifc_mcam_enhanced_features_bits {
10179	u8 reserved_at_0[0x50];
10180	u8 mtutc_freq_adj_units[0x1];
10181	u8 mtutc_time_adjustment_extended_range[0x1];
10182	u8 reserved_at_52[0xb];
10183	u8 mcia_32dwords[0x1];
10184	u8 out_pulse_duration_ns[0x1];
10185	u8 npps_period[0x1];
10186	u8 reserved_at_60[0xa];
10187	u8 reset_state[0x1];
10188	u8 ptpcyc2realtime_modify[0x1];
10189	u8 reserved_at_6c[0x2];
10190	u8 pci_status_and_power[0x1];
10191	u8 reserved_at_6f[0x5];
10192	u8 mark_tx_action_cnp[0x1];
10193	u8 mark_tx_action_cqe[0x1];
10194	u8 dynamic_tx_overflow[0x1];
10195	u8 reserved_at_77[0x4];
10196	u8 pcie_outbound_stalled[0x1];
10197	u8 tx_overflow_buffer_pkt[0x1];
10198	u8 mtpps_enh_out_per_adj[0x1];
10199	u8 mtpps_fs[0x1];
10200	u8 pcie_performance_group[0x1];
10201	};
10202
10203	struct mlx5_ifc_mcam_access_reg_bits {
10204	u8 reserved_at_0[0x1c];
10205	u8 mcda[0x1];
10206	u8 mcc[0x1];
10207	u8 mcqi[0x1];
10208	u8 mcqs[0x1];
10209
10210	u8 regs_95_to_87[0x9];
10211	u8 mpegc[0x1];
10212	u8 mtutc[0x1];
10213	u8 regs_84_to_68[0x11];
10214	u8 tracer_registers[0x4];
10215
10216	u8 regs_63_to_46[0x12];
10217	u8 mrtc[0x1];
10218	u8 regs_44_to_32[0xd];
10219
10220	u8 regs_31_to_10[0x16];
10221	u8 mtmp[0x1];
10222	u8 regs_8_to_0[0x9];
10223	};
10224
10225	struct mlx5_ifc_mcam_access_reg_bits1 {
10226	u8 regs_127_to_96[0x20];
10227
10228	u8 regs_95_to_64[0x20];
10229
10230	u8 regs_63_to_32[0x20];
10231
10232	u8 regs_31_to_0[0x20];
10233	};
10234
10235	struct mlx5_ifc_mcam_access_reg_bits2 {
10236	u8 regs_127_to_99[0x1d];
10237	u8 mirc[0x1];
10238	u8 regs_97_to_96[0x2];
10239
10240	u8 regs_95_to_87[0x09];
10241	u8 synce_registers[0x2];
10242	u8 regs_84_to_64[0x15];
10243
10244	u8 regs_63_to_32[0x20];
10245
10246	u8 regs_31_to_0[0x20];
10247	};
10248
10249	struct mlx5_ifc_mcam_reg_bits {
10250	u8 reserved_at_0[0x8];
10251	u8 feature_group[0x8];
10252	u8 reserved_at_10[0x8];
10253	u8 access_reg_group[0x8];
10254
10255	u8 reserved_at_20[0x20];
10256
10257	union {
10258	struct mlx5_ifc_mcam_access_reg_bits access_regs;
10259	struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10260	struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10261	u8 reserved_at_0[0x80];
10262	} mng_access_reg_cap_mask;
10263
10264	u8 reserved_at_c0[0x80];
10265
10266	union {
10267	struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10268	u8 reserved_at_0[0x80];
10269	} mng_feature_cap_mask;
10270
10271	u8 reserved_at_1c0[0x80];
10272	};
10273
10274	struct mlx5_ifc_qcam_access_reg_cap_mask {
10275	u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
10276	u8 qpdpm[0x1];
10277	u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
10278	u8 qdpm[0x1];
10279	u8 qpts[0x1];
10280	u8 qcap[0x1];
10281	u8 qcam_access_reg_cap_mask_0[0x1];
10282	};
10283
10284	struct mlx5_ifc_qcam_qos_feature_cap_mask {
10285	u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
10286	u8 qpts_trust_both[0x1];
10287	};
10288
10289	struct mlx5_ifc_qcam_reg_bits {
10290	u8 reserved_at_0[0x8];
10291	u8 feature_group[0x8];
10292	u8 reserved_at_10[0x8];
10293	u8 access_reg_group[0x8];
10294	u8 reserved_at_20[0x20];
10295
10296	union {
10297	struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10298	u8 reserved_at_0[0x80];
10299	} qos_access_reg_cap_mask;
10300
10301	u8 reserved_at_c0[0x80];
10302
10303	union {
10304	struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10305	u8 reserved_at_0[0x80];
10306	} qos_feature_cap_mask;
10307
10308	u8 reserved_at_1c0[0x80];
10309	};
10310
10311	struct mlx5_ifc_core_dump_reg_bits {
10312	u8 reserved_at_0[0x18];
10313	u8 core_dump_type[0x8];
10314
10315	u8 reserved_at_20[0x30];
10316	u8 vhca_id[0x10];
10317
10318	u8 reserved_at_60[0x8];
10319	u8 qpn[0x18];
10320	u8 reserved_at_80[0x180];
10321	};
10322
10323	struct mlx5_ifc_pcap_reg_bits {
10324	u8 reserved_at_0[0x8];
10325	u8 local_port[0x8];
10326	u8 reserved_at_10[0x10];
10327
10328	u8 port_capability_mask[4][0x20];
10329	};
10330
10331	struct mlx5_ifc_paos_reg_bits {
10332	u8 swid[0x8];
10333	u8 local_port[0x8];
10334	u8 reserved_at_10[0x4];
10335	u8 admin_status[0x4];
10336	u8 reserved_at_18[0x4];
10337	u8 oper_status[0x4];
10338
10339	u8 ase[0x1];
10340	u8 ee[0x1];
10341	u8 reserved_at_22[0x1c];
10342	u8 e[0x2];
10343
10344	u8 reserved_at_40[0x40];
10345	};
10346
10347	struct mlx5_ifc_pamp_reg_bits {
10348	u8 reserved_at_0[0x8];
10349	u8 opamp_group[0x8];
10350	u8 reserved_at_10[0xc];
10351	u8 opamp_group_type[0x4];
10352
10353	u8 start_index[0x10];
10354	u8 reserved_at_30[0x4];
10355	u8 num_of_indices[0xc];
10356
10357	u8 index_data[18][0x10];
10358	};
10359
10360	struct mlx5_ifc_pcmr_reg_bits {
10361	u8 reserved_at_0[0x8];
10362	u8 local_port[0x8];
10363	u8 reserved_at_10[0x10];
10364
10365	u8 entropy_force_cap[0x1];
10366	u8 entropy_calc_cap[0x1];
10367	u8 entropy_gre_calc_cap[0x1];
10368	u8 reserved_at_23[0xf];
10369	u8 rx_ts_over_crc_cap[0x1];
10370	u8 reserved_at_33[0xb];
10371	u8 fcs_cap[0x1];
10372	u8 reserved_at_3f[0x1];
10373
10374	u8 entropy_force[0x1];
10375	u8 entropy_calc[0x1];
10376	u8 entropy_gre_calc[0x1];
10377	u8 reserved_at_43[0xf];
10378	u8 rx_ts_over_crc[0x1];
10379	u8 reserved_at_53[0xb];
10380	u8 fcs_chk[0x1];
10381	u8 reserved_at_5f[0x1];
10382	};
10383
10384	struct mlx5_ifc_lane_2_module_mapping_bits {
10385	u8 reserved_at_0[0x4];
10386	u8 rx_lane[0x4];
10387	u8 reserved_at_8[0x4];
10388	u8 tx_lane[0x4];
10389	u8 reserved_at_10[0x8];
10390	u8 module[0x8];
10391	};
10392
10393	struct mlx5_ifc_bufferx_reg_bits {
10394	u8 reserved_at_0[0x6];
10395	u8 lossy[0x1];
10396	u8 epsb[0x1];
10397	u8 reserved_at_8[0x8];
10398	u8 size[0x10];
10399
10400	u8 xoff_threshold[0x10];
10401	u8 xon_threshold[0x10];
10402	};
10403
10404	struct mlx5_ifc_set_node_in_bits {
10405	u8 node_description[64][0x8];
10406	};
10407
10408	struct mlx5_ifc_register_power_settings_bits {
10409	u8 reserved_at_0[0x18];
10410	u8 power_settings_level[0x8];
10411
10412	u8 reserved_at_20[0x60];
10413	};
10414
10415	struct mlx5_ifc_register_host_endianness_bits {
10416	u8 he[0x1];
10417	u8 reserved_at_1[0x1f];
10418
10419	u8 reserved_at_20[0x60];
10420	};
10421
10422	struct mlx5_ifc_umr_pointer_desc_argument_bits {
10423	u8 reserved_at_0[0x20];
10424
10425	u8 mkey[0x20];
10426
10427	u8 addressh_63_32[0x20];
10428
10429	u8 addressl_31_0[0x20];
10430	};
10431
10432	struct mlx5_ifc_ud_adrs_vector_bits {
10433	u8 dc_key[0x40];
10434
10435	u8 ext[0x1];
10436	u8 reserved_at_41[0x7];
10437	u8 destination_qp_dct[0x18];
10438
10439	u8 static_rate[0x4];
10440	u8 sl_eth_prio[0x4];
10441	u8 fl[0x1];
10442	u8 mlid[0x7];
10443	u8 rlid_udp_sport[0x10];
10444
10445	u8 reserved_at_80[0x20];
10446
10447	u8 rmac_47_16[0x20];
10448
10449	u8 rmac_15_0[0x10];
10450	u8 tclass[0x8];
10451	u8 hop_limit[0x8];
10452
10453	u8 reserved_at_e0[0x1];
10454	u8 grh[0x1];
10455	u8 reserved_at_e2[0x2];
10456	u8 src_addr_index[0x8];
10457	u8 flow_label[0x14];
10458
10459	u8 rgid_rip[16][0x8];
10460	};
10461
10462	struct mlx5_ifc_pages_req_event_bits {
10463	u8 reserved_at_0[0x10];
10464	u8 function_id[0x10];
10465
10466	u8 num_pages[0x20];
10467
10468	u8 reserved_at_40[0xa0];
10469	};
10470
10471	struct mlx5_ifc_eqe_bits {
10472	u8 reserved_at_0[0x8];
10473	u8 event_type[0x8];
10474	u8 reserved_at_10[0x8];
10475	u8 event_sub_type[0x8];
10476
10477	u8 reserved_at_20[0xe0];
10478
10479	union mlx5_ifc_event_auto_bits event_data;
10480
10481	u8 reserved_at_1e0[0x10];
10482	u8 signature[0x8];
10483	u8 reserved_at_1f8[0x7];
10484	u8 owner[0x1];
10485	};
10486
10487	enum {
10488	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10489	};
10490
10491	struct mlx5_ifc_cmd_queue_entry_bits {
10492	u8 type[0x8];
10493	u8 reserved_at_8[0x18];
10494
10495	u8 input_length[0x20];
10496
10497	u8 input_mailbox_pointer_63_32[0x20];
10498
10499	u8 input_mailbox_pointer_31_9[0x17];
10500	u8 reserved_at_77[0x9];
10501
10502	u8 command_input_inline_data[16][0x8];
10503
10504	u8 command_output_inline_data[16][0x8];
10505
10506	u8 output_mailbox_pointer_63_32[0x20];
10507
10508	u8 output_mailbox_pointer_31_9[0x17];
10509	u8 reserved_at_1b7[0x9];
10510
10511	u8 output_length[0x20];
10512
10513	u8 token[0x8];
10514	u8 signature[0x8];
10515	u8 reserved_at_1f0[0x8];
10516	u8 status[0x7];
10517	u8 ownership[0x1];
10518	};
10519
10520	struct mlx5_ifc_cmd_out_bits {
10521	u8 status[0x8];
10522	u8 reserved_at_8[0x18];
10523
10524	u8 syndrome[0x20];
10525
10526	u8 command_output[0x20];
10527	};
10528
10529	struct mlx5_ifc_cmd_in_bits {
10530	u8 opcode[0x10];
10531	u8 reserved_at_10[0x10];
10532
10533	u8 reserved_at_20[0x10];
10534	u8 op_mod[0x10];
10535
10536	u8 command[][0x20];
10537	};
10538
10539	struct mlx5_ifc_cmd_if_box_bits {
10540	u8 mailbox_data[512][0x8];
10541
10542	u8 reserved_at_1000[0x180];
10543
10544	u8 next_pointer_63_32[0x20];
10545
10546	u8 next_pointer_31_10[0x16];
10547	u8 reserved_at_11b6[0xa];
10548
10549	u8 block_number[0x20];
10550
10551	u8 reserved_at_11e0[0x8];
10552	u8 token[0x8];
10553	u8 ctrl_signature[0x8];
10554	u8 signature[0x8];
10555	};
10556
10557	struct mlx5_ifc_mtt_bits {
10558	u8 ptag_63_32[0x20];
10559
10560	u8 ptag_31_8[0x18];
10561	u8 reserved_at_38[0x6];
10562	u8 wr_en[0x1];
10563	u8 rd_en[0x1];
10564	};
10565
10566	struct mlx5_ifc_query_wol_rol_out_bits {
10567	u8 status[0x8];
10568	u8 reserved_at_8[0x18];
10569
10570	u8 syndrome[0x20];
10571
10572	u8 reserved_at_40[0x10];
10573	u8 rol_mode[0x8];
10574	u8 wol_mode[0x8];
10575
10576	u8 reserved_at_60[0x20];
10577	};
10578
10579	struct mlx5_ifc_query_wol_rol_in_bits {
10580	u8 opcode[0x10];
10581	u8 reserved_at_10[0x10];
10582
10583	u8 reserved_at_20[0x10];
10584	u8 op_mod[0x10];
10585
10586	u8 reserved_at_40[0x40];
10587	};
10588
10589	struct mlx5_ifc_set_wol_rol_out_bits {
10590	u8 status[0x8];
10591	u8 reserved_at_8[0x18];
10592
10593	u8 syndrome[0x20];
10594
10595	u8 reserved_at_40[0x40];
10596	};
10597
10598	struct mlx5_ifc_set_wol_rol_in_bits {
10599	u8 opcode[0x10];
10600	u8 reserved_at_10[0x10];
10601
10602	u8 reserved_at_20[0x10];
10603	u8 op_mod[0x10];
10604
10605	u8 rol_mode_valid[0x1];
10606	u8 wol_mode_valid[0x1];
10607	u8 reserved_at_42[0xe];
10608	u8 rol_mode[0x8];
10609	u8 wol_mode[0x8];
10610
10611	u8 reserved_at_60[0x20];
10612	};
10613
10614	enum {
10615	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10616	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10617	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10618	};
10619
10620	enum {
10621	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10622	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10623	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10624	};
10625
10626	enum {
10627	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10628	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10629	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10630	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10631	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10632	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10633	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10634	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10635	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10636	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10637	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10638	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12,
10639	};
10640
10641	struct mlx5_ifc_initial_seg_bits {
10642	u8 fw_rev_minor[0x10];
10643	u8 fw_rev_major[0x10];
10644
10645	u8 cmd_interface_rev[0x10];
10646	u8 fw_rev_subminor[0x10];
10647
10648	u8 reserved_at_40[0x40];
10649
10650	u8 cmdq_phy_addr_63_32[0x20];
10651
10652	u8 cmdq_phy_addr_31_12[0x14];
10653	u8 reserved_at_b4[0x2];
10654	u8 nic_interface[0x2];
10655	u8 log_cmdq_size[0x4];
10656	u8 log_cmdq_stride[0x4];
10657
10658	u8 command_doorbell_vector[0x20];
10659
10660	u8 reserved_at_e0[0xf00];
10661
10662	u8 initializing[0x1];
10663	u8 reserved_at_fe1[0x4];
10664	u8 nic_interface_supported[0x3];
10665	u8 embedded_cpu[0x1];
10666	u8 reserved_at_fe9[0x17];
10667
10668	struct mlx5_ifc_health_buffer_bits health_buffer;
10669
10670	u8 no_dram_nic_offset[0x20];
10671
10672	u8 reserved_at_1220[0x6e40];
10673
10674	u8 reserved_at_8060[0x1f];
10675	u8 clear_int[0x1];
10676
10677	u8 health_syndrome[0x8];
10678	u8 health_counter[0x18];
10679
10680	u8 reserved_at_80a0[0x17fc0];
10681	};
10682
10683	struct mlx5_ifc_mtpps_reg_bits {
10684	u8 reserved_at_0[0xc];
10685	u8 cap_number_of_pps_pins[0x4];
10686	u8 reserved_at_10[0x4];
10687	u8 cap_max_num_of_pps_in_pins[0x4];
10688	u8 reserved_at_18[0x4];
10689	u8 cap_max_num_of_pps_out_pins[0x4];
10690
10691	u8 reserved_at_20[0x13];
10692	u8 cap_log_min_npps_period[0x5];
10693	u8 reserved_at_38[0x3];
10694	u8 cap_log_min_out_pulse_duration_ns[0x5];
10695
10696	u8 reserved_at_40[0x4];
10697	u8 cap_pin_3_mode[0x4];
10698	u8 reserved_at_48[0x4];
10699	u8 cap_pin_2_mode[0x4];
10700	u8 reserved_at_50[0x4];
10701	u8 cap_pin_1_mode[0x4];
10702	u8 reserved_at_58[0x4];
10703	u8 cap_pin_0_mode[0x4];
10704
10705	u8 reserved_at_60[0x4];
10706	u8 cap_pin_7_mode[0x4];
10707	u8 reserved_at_68[0x4];
10708	u8 cap_pin_6_mode[0x4];
10709	u8 reserved_at_70[0x4];
10710	u8 cap_pin_5_mode[0x4];
10711	u8 reserved_at_78[0x4];
10712	u8 cap_pin_4_mode[0x4];
10713
10714	u8 field_select[0x20];
10715	u8 reserved_at_a0[0x20];
10716
10717	u8 npps_period[0x40];
10718
10719	u8 enable[0x1];
10720	u8 reserved_at_101[0xb];
10721	u8 pattern[0x4];
10722	u8 reserved_at_110[0x4];
10723	u8 pin_mode[0x4];
10724	u8 pin[0x8];
10725
10726	u8 reserved_at_120[0x2];
10727	u8 out_pulse_duration_ns[0x1e];
10728
10729	u8 time_stamp[0x40];
10730
10731	u8 out_pulse_duration[0x10];
10732	u8 out_periodic_adjustment[0x10];
10733	u8 enhanced_out_periodic_adjustment[0x20];
10734
10735	u8 reserved_at_1c0[0x20];
10736	};
10737
10738	struct mlx5_ifc_mtppse_reg_bits {
10739	u8 reserved_at_0[0x18];
10740	u8 pin[0x8];
10741	u8 event_arm[0x1];
10742	u8 reserved_at_21[0x1b];
10743	u8 event_generation_mode[0x4];
10744	u8 reserved_at_40[0x40];
10745	};
10746
10747	struct mlx5_ifc_mcqs_reg_bits {
10748	u8 last_index_flag[0x1];
10749	u8 reserved_at_1[0x7];
10750	u8 fw_device[0x8];
10751	u8 component_index[0x10];
10752
10753	u8 reserved_at_20[0x10];
10754	u8 identifier[0x10];
10755
10756	u8 reserved_at_40[0x17];
10757	u8 component_status[0x5];
10758	u8 component_update_state[0x4];
10759
10760	u8 last_update_state_changer_type[0x4];
10761	u8 last_update_state_changer_host_id[0x4];
10762	u8 reserved_at_68[0x18];
10763	};
10764
10765	struct mlx5_ifc_mcqi_cap_bits {
10766	u8 supported_info_bitmask[0x20];
10767
10768	u8 component_size[0x20];
10769
10770	u8 max_component_size[0x20];
10771
10772	u8 log_mcda_word_size[0x4];
10773	u8 reserved_at_64[0xc];
10774	u8 mcda_max_write_size[0x10];
10775
10776	u8 rd_en[0x1];
10777	u8 reserved_at_81[0x1];
10778	u8 match_chip_id[0x1];
10779	u8 match_psid[0x1];
10780	u8 check_user_timestamp[0x1];
10781	u8 match_base_guid_mac[0x1];
10782	u8 reserved_at_86[0x1a];
10783	};
10784
10785	struct mlx5_ifc_mcqi_version_bits {
10786	u8 reserved_at_0[0x2];
10787	u8 build_time_valid[0x1];
10788	u8 user_defined_time_valid[0x1];
10789	u8 reserved_at_4[0x14];
10790	u8 version_string_length[0x8];
10791
10792	u8 version[0x20];
10793
10794	u8 build_time[0x40];
10795
10796	u8 user_defined_time[0x40];
10797
10798	u8 build_tool_version[0x20];
10799
10800	u8 reserved_at_e0[0x20];
10801
10802	u8 version_string[92][0x8];
10803	};
10804
10805	struct mlx5_ifc_mcqi_activation_method_bits {
10806	u8 pending_server_ac_power_cycle[0x1];
10807	u8 pending_server_dc_power_cycle[0x1];
10808	u8 pending_server_reboot[0x1];
10809	u8 pending_fw_reset[0x1];
10810	u8 auto_activate[0x1];
10811	u8 all_hosts_sync[0x1];
10812	u8 device_hw_reset[0x1];
10813	u8 reserved_at_7[0x19];
10814	};
10815
10816	union mlx5_ifc_mcqi_reg_data_bits {
10817	struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10818	struct mlx5_ifc_mcqi_version_bits mcqi_version;
10819	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10820	};
10821
10822	struct mlx5_ifc_mcqi_reg_bits {
10823	u8 read_pending_component[0x1];
10824	u8 reserved_at_1[0xf];
10825	u8 component_index[0x10];
10826
10827	u8 reserved_at_20[0x20];
10828
10829	u8 reserved_at_40[0x1b];
10830	u8 info_type[0x5];
10831
10832	u8 info_size[0x20];
10833
10834	u8 offset[0x20];
10835
10836	u8 reserved_at_a0[0x10];
10837	u8 data_size[0x10];
10838
10839	union mlx5_ifc_mcqi_reg_data_bits data[];
10840	};
10841
10842	struct mlx5_ifc_mcc_reg_bits {
10843	u8 reserved_at_0[0x4];
10844	u8 time_elapsed_since_last_cmd[0xc];
10845	u8 reserved_at_10[0x8];
10846	u8 instruction[0x8];
10847
10848	u8 reserved_at_20[0x10];
10849	u8 component_index[0x10];
10850
10851	u8 reserved_at_40[0x8];
10852	u8 update_handle[0x18];
10853
10854	u8 handle_owner_type[0x4];
10855	u8 handle_owner_host_id[0x4];
10856	u8 reserved_at_68[0x1];
10857	u8 control_progress[0x7];
10858	u8 error_code[0x8];
10859	u8 reserved_at_78[0x4];
10860	u8 control_state[0x4];
10861
10862	u8 component_size[0x20];
10863
10864	u8 reserved_at_a0[0x60];
10865	};
10866
10867	struct mlx5_ifc_mcda_reg_bits {
10868	u8 reserved_at_0[0x8];
10869	u8 update_handle[0x18];
10870
10871	u8 offset[0x20];
10872
10873	u8 reserved_at_40[0x10];
10874	u8 size[0x10];
10875
10876	u8 reserved_at_60[0x20];
10877
10878	u8 data[][0x20];
10879	};
10880
10881	enum {
10882	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10883	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10884	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10885	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10886	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10887	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10888	};
10889
10890	enum {
10891	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10892	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10893	};
10894
10895	enum {
10896	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10897	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10898	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10899	};
10900
10901	struct mlx5_ifc_mfrl_reg_bits {
10902	u8 reserved_at_0[0x20];
10903
10904	u8 reserved_at_20[0x2];
10905	u8 pci_sync_for_fw_update_start[0x1];
10906	u8 pci_sync_for_fw_update_resp[0x2];
10907	u8 rst_type_sel[0x3];
10908	u8 reserved_at_28[0x4];
10909	u8 reset_state[0x4];
10910	u8 reset_type[0x8];
10911	u8 reset_level[0x8];
10912	};
10913
10914	struct mlx5_ifc_mirc_reg_bits {
10915	u8 reserved_at_0[0x18];
10916	u8 status_code[0x8];
10917
10918	u8 reserved_at_20[0x20];
10919	};
10920
10921	struct mlx5_ifc_pddr_monitor_opcode_bits {
10922	u8 reserved_at_0[0x10];
10923	u8 monitor_opcode[0x10];
10924	};
10925
10926	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10927	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10928	u8 reserved_at_0[0x20];
10929	};
10930
10931	enum {
10932	/* Monitor opcodes */
10933	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10934	};
10935
10936	struct mlx5_ifc_pddr_troubleshooting_page_bits {
10937	u8 reserved_at_0[0x10];
10938	u8 group_opcode[0x10];
10939
10940	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10941
10942	u8 reserved_at_40[0x20];
10943
10944	u8 status_message[59][0x20];
10945	};
10946
10947	union mlx5_ifc_pddr_reg_page_data_auto_bits {
10948	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10949	u8 reserved_at_0[0x7c0];
10950	};
10951
10952	enum {
10953	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10954	};
10955
10956	struct mlx5_ifc_pddr_reg_bits {
10957	u8 reserved_at_0[0x8];
10958	u8 local_port[0x8];
10959	u8 pnat[0x2];
10960	u8 reserved_at_12[0xe];
10961
10962	u8 reserved_at_20[0x18];
10963	u8 page_select[0x8];
10964
10965	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10966	};
10967
10968	struct mlx5_ifc_mrtc_reg_bits {
10969	u8 time_synced[0x1];
10970	u8 reserved_at_1[0x1f];
10971
10972	u8 reserved_at_20[0x20];
10973
10974	u8 time_h[0x20];
10975
10976	u8 time_l[0x20];
10977	};
10978
10979	struct mlx5_ifc_mtcap_reg_bits {
10980	u8 reserved_at_0[0x19];
10981	u8 sensor_count[0x7];
10982
10983	u8 reserved_at_20[0x20];
10984
10985	u8 sensor_map[0x40];
10986	};
10987
10988	struct mlx5_ifc_mtmp_reg_bits {
10989	u8 reserved_at_0[0x14];
10990	u8 sensor_index[0xc];
10991
10992	u8 reserved_at_20[0x10];
10993	u8 temperature[0x10];
10994
10995	u8 mte[0x1];
10996	u8 mtr[0x1];
10997	u8 reserved_at_42[0xe];
10998	u8 max_temperature[0x10];
10999
11000	u8 tee[0x2];
11001	u8 reserved_at_62[0xe];
11002	u8 temp_threshold_hi[0x10];
11003
11004	u8 reserved_at_80[0x10];
11005	u8 temp_threshold_lo[0x10];
11006
11007	u8 reserved_at_a0[0x20];
11008
11009	u8 sensor_name_hi[0x20];
11010	u8 sensor_name_lo[0x20];
11011	};
11012
11013	union mlx5_ifc_ports_control_registers_document_bits {
11014	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11015	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11016	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11017	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11018	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11019	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11020	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11021	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11022	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11023	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11024	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11025	struct mlx5_ifc_paos_reg_bits paos_reg;
11026	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11027	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11028	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11029	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11030	struct mlx5_ifc_peir_reg_bits peir_reg;
11031	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11032	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11033	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11034	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11035	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11036	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11037	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11038	struct mlx5_ifc_plib_reg_bits plib_reg;
11039	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11040	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11041	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11042	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11043	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11044	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11045	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11046	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11047	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11048	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11049	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11050	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11051	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11052	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11053	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11054	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11055	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11056	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11057	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11058	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11059	struct mlx5_ifc_pude_reg_bits pude_reg;
11060	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11061	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11062	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11063	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11064	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11065	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11066	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11067	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11068	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11069	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11070	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11071	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11072	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11073	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11074	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11075	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11076	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11077	u8 reserved_at_0[0x60e0];
11078	};
11079
11080	union mlx5_ifc_debug_enhancements_document_bits {
11081	struct mlx5_ifc_health_buffer_bits health_buffer;
11082	u8 reserved_at_0[0x200];
11083	};
11084
11085	union mlx5_ifc_uplink_pci_interface_document_bits {
11086	struct mlx5_ifc_initial_seg_bits initial_seg;
11087	u8 reserved_at_0[0x20060];
11088	};
11089
11090	struct mlx5_ifc_set_flow_table_root_out_bits {
11091	u8 status[0x8];
11092	u8 reserved_at_8[0x18];
11093
11094	u8 syndrome[0x20];
11095
11096	u8 reserved_at_40[0x40];
11097	};
11098
11099	struct mlx5_ifc_set_flow_table_root_in_bits {
11100	u8 opcode[0x10];
11101	u8 reserved_at_10[0x10];
11102
11103	u8 reserved_at_20[0x10];
11104	u8 op_mod[0x10];
11105
11106	u8 other_vport[0x1];
11107	u8 reserved_at_41[0xf];
11108	u8 vport_number[0x10];
11109
11110	u8 reserved_at_60[0x20];
11111
11112	u8 table_type[0x8];
11113	u8 reserved_at_88[0x7];
11114	u8 table_of_other_vport[0x1];
11115	u8 table_vport_number[0x10];
11116
11117	u8 reserved_at_a0[0x8];
11118	u8 table_id[0x18];
11119
11120	u8 reserved_at_c0[0x8];
11121	u8 underlay_qpn[0x18];
11122	u8 table_eswitch_owner_vhca_id_valid[0x1];
11123	u8 reserved_at_e1[0xf];
11124	u8 table_eswitch_owner_vhca_id[0x10];
11125	u8 reserved_at_100[0x100];
11126	};
11127
11128	enum {
11129	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
11130	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11131	};
11132
11133	struct mlx5_ifc_modify_flow_table_out_bits {
11134	u8 status[0x8];
11135	u8 reserved_at_8[0x18];
11136
11137	u8 syndrome[0x20];
11138
11139	u8 reserved_at_40[0x40];
11140	};
11141
11142	struct mlx5_ifc_modify_flow_table_in_bits {
11143	u8 opcode[0x10];
11144	u8 reserved_at_10[0x10];
11145
11146	u8 reserved_at_20[0x10];
11147	u8 op_mod[0x10];
11148
11149	u8 other_vport[0x1];
11150	u8 reserved_at_41[0xf];
11151	u8 vport_number[0x10];
11152
11153	u8 reserved_at_60[0x10];
11154	u8 modify_field_select[0x10];
11155
11156	u8 table_type[0x8];
11157	u8 reserved_at_88[0x18];
11158
11159	u8 reserved_at_a0[0x8];
11160	u8 table_id[0x18];
11161
11162	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11163	};
11164
11165	struct mlx5_ifc_ets_tcn_config_reg_bits {
11166	u8 g[0x1];
11167	u8 b[0x1];
11168	u8 r[0x1];
11169	u8 reserved_at_3[0x9];
11170	u8 group[0x4];
11171	u8 reserved_at_10[0x9];
11172	u8 bw_allocation[0x7];
11173
11174	u8 reserved_at_20[0xc];
11175	u8 max_bw_units[0x4];
11176	u8 reserved_at_30[0x8];
11177	u8 max_bw_value[0x8];
11178	};
11179
11180	struct mlx5_ifc_ets_global_config_reg_bits {
11181	u8 reserved_at_0[0x2];
11182	u8 r[0x1];
11183	u8 reserved_at_3[0x1d];
11184
11185	u8 reserved_at_20[0xc];
11186	u8 max_bw_units[0x4];
11187	u8 reserved_at_30[0x8];
11188	u8 max_bw_value[0x8];
11189	};
11190
11191	struct mlx5_ifc_qetc_reg_bits {
11192	u8 reserved_at_0[0x8];
11193	u8 port_number[0x8];
11194	u8 reserved_at_10[0x30];
11195
11196	struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
11197	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11198	};
11199
11200	struct mlx5_ifc_qpdpm_dscp_reg_bits {
11201	u8 e[0x1];
11202	u8 reserved_at_01[0x0b];
11203	u8 prio[0x04];
11204	};
11205
11206	struct mlx5_ifc_qpdpm_reg_bits {
11207	u8 reserved_at_0[0x8];
11208	u8 local_port[0x8];
11209	u8 reserved_at_10[0x10];
11210	struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
11211	};
11212
11213	struct mlx5_ifc_qpts_reg_bits {
11214	u8 reserved_at_0[0x8];
11215	u8 local_port[0x8];
11216	u8 reserved_at_10[0x2d];
11217	u8 trust_state[0x3];
11218	};
11219
11220	struct mlx5_ifc_pptb_reg_bits {
11221	u8 reserved_at_0[0x2];
11222	u8 mm[0x2];
11223	u8 reserved_at_4[0x4];
11224	u8 local_port[0x8];
11225	u8 reserved_at_10[0x6];
11226	u8 cm[0x1];
11227	u8 um[0x1];
11228	u8 pm[0x8];
11229
11230	u8 prio_x_buff[0x20];
11231
11232	u8 pm_msb[0x8];
11233	u8 reserved_at_48[0x10];
11234	u8 ctrl_buff[0x4];
11235	u8 untagged_buff[0x4];
11236	};
11237
11238	struct mlx5_ifc_sbcam_reg_bits {
11239	u8 reserved_at_0[0x8];
11240	u8 feature_group[0x8];
11241	u8 reserved_at_10[0x8];
11242	u8 access_reg_group[0x8];
11243
11244	u8 reserved_at_20[0x20];
11245
11246	u8 sb_access_reg_cap_mask[4][0x20];
11247
11248	u8 reserved_at_c0[0x80];
11249
11250	u8 sb_feature_cap_mask[4][0x20];
11251
11252	u8 reserved_at_1c0[0x40];
11253
11254	u8 cap_total_buffer_size[0x20];
11255
11256	u8 cap_cell_size[0x10];
11257	u8 cap_max_pg_buffers[0x8];
11258	u8 cap_num_pool_supported[0x8];
11259
11260	u8 reserved_at_240[0x8];
11261	u8 cap_sbsr_stat_size[0x8];
11262	u8 cap_max_tclass_data[0x8];
11263	u8 cap_max_cpu_ingress_tclass_sb[0x8];
11264	};
11265
11266	struct mlx5_ifc_pbmc_reg_bits {
11267	u8 reserved_at_0[0x8];
11268	u8 local_port[0x8];
11269	u8 reserved_at_10[0x10];
11270
11271	u8 xoff_timer_value[0x10];
11272	u8 xoff_refresh[0x10];
11273
11274	u8 reserved_at_40[0x9];
11275	u8 fullness_threshold[0x7];
11276	u8 port_buffer_size[0x10];
11277
11278	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11279
11280	u8 reserved_at_2e0[0x80];
11281	};
11282
11283	struct mlx5_ifc_sbpr_reg_bits {
11284	u8 desc[0x1];
11285	u8 snap[0x1];
11286	u8 reserved_at_2[0x4];
11287	u8 dir[0x2];
11288	u8 reserved_at_8[0x14];
11289	u8 pool[0x4];
11290
11291	u8 infi_size[0x1];
11292	u8 reserved_at_21[0x7];
11293	u8 size[0x18];
11294
11295	u8 reserved_at_40[0x1c];
11296	u8 mode[0x4];
11297
11298	u8 reserved_at_60[0x8];
11299	u8 buff_occupancy[0x18];
11300
11301	u8 clr[0x1];
11302	u8 reserved_at_81[0x7];
11303	u8 max_buff_occupancy[0x18];
11304
11305	u8 reserved_at_a0[0x8];
11306	u8 ext_buff_occupancy[0x18];
11307	};
11308
11309	struct mlx5_ifc_sbcm_reg_bits {
11310	u8 desc[0x1];
11311	u8 snap[0x1];
11312	u8 reserved_at_2[0x6];
11313	u8 local_port[0x8];
11314	u8 pnat[0x2];
11315	u8 pg_buff[0x6];
11316	u8 reserved_at_18[0x6];
11317	u8 dir[0x2];
11318
11319	u8 reserved_at_20[0x1f];
11320	u8 exc[0x1];
11321
11322	u8 reserved_at_40[0x40];
11323
11324	u8 reserved_at_80[0x8];
11325	u8 buff_occupancy[0x18];
11326
11327	u8 clr[0x1];
11328	u8 reserved_at_a1[0x7];
11329	u8 max_buff_occupancy[0x18];
11330
11331	u8 reserved_at_c0[0x8];
11332	u8 min_buff[0x18];
11333
11334	u8 infi_max[0x1];
11335	u8 reserved_at_e1[0x7];
11336	u8 max_buff[0x18];
11337
11338	u8 reserved_at_100[0x20];
11339
11340	u8 reserved_at_120[0x1c];
11341	u8 pool[0x4];
11342	};
11343
11344	struct mlx5_ifc_qtct_reg_bits {
11345	u8 reserved_at_0[0x8];
11346	u8 port_number[0x8];
11347	u8 reserved_at_10[0xd];
11348	u8 prio[0x3];
11349
11350	u8 reserved_at_20[0x1d];
11351	u8 tclass[0x3];
11352	};
11353
11354	struct mlx5_ifc_mcia_reg_bits {
11355	u8 l[0x1];
11356	u8 reserved_at_1[0x7];
11357	u8 module[0x8];
11358	u8 reserved_at_10[0x8];
11359	u8 status[0x8];
11360
11361	u8 i2c_device_address[0x8];
11362	u8 page_number[0x8];
11363	u8 device_address[0x10];
11364
11365	u8 reserved_at_40[0x10];
11366	u8 size[0x10];
11367
11368	u8 reserved_at_60[0x20];
11369
11370	u8 dword_0[0x20];
11371	u8 dword_1[0x20];
11372	u8 dword_2[0x20];
11373	u8 dword_3[0x20];
11374	u8 dword_4[0x20];
11375	u8 dword_5[0x20];
11376	u8 dword_6[0x20];
11377	u8 dword_7[0x20];
11378	u8 dword_8[0x20];
11379	u8 dword_9[0x20];
11380	u8 dword_10[0x20];
11381	u8 dword_11[0x20];
11382	};
11383
11384	struct mlx5_ifc_dcbx_param_bits {
11385	u8 dcbx_cee_cap[0x1];
11386	u8 dcbx_ieee_cap[0x1];
11387	u8 dcbx_standby_cap[0x1];
11388	u8 reserved_at_3[0x5];
11389	u8 port_number[0x8];
11390	u8 reserved_at_10[0xa];
11391	u8 max_application_table_size[6];
11392	u8 reserved_at_20[0x15];
11393	u8 version_oper[0x3];
11394	u8 reserved_at_38[5];
11395	u8 version_admin[0x3];
11396	u8 willing_admin[0x1];
11397	u8 reserved_at_41[0x3];
11398	u8 pfc_cap_oper[0x4];
11399	u8 reserved_at_48[0x4];
11400	u8 pfc_cap_admin[0x4];
11401	u8 reserved_at_50[0x4];
11402	u8 num_of_tc_oper[0x4];
11403	u8 reserved_at_58[0x4];
11404	u8 num_of_tc_admin[0x4];
11405	u8 remote_willing[0x1];
11406	u8 reserved_at_61[3];
11407	u8 remote_pfc_cap[4];
11408	u8 reserved_at_68[0x14];
11409	u8 remote_num_of_tc[0x4];
11410	u8 reserved_at_80[0x18];
11411	u8 error[0x8];
11412	u8 reserved_at_a0[0x160];
11413	};
11414
11415	enum {
11416	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11417	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11418	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11419	};
11420
11421	struct mlx5_ifc_lagc_bits {
11422	u8 fdb_selection_mode[0x1];
11423	u8 reserved_at_1[0x14];
11424	u8 port_select_mode[0x3];
11425	u8 reserved_at_18[0x5];
11426	u8 lag_state[0x3];
11427
11428	u8 reserved_at_20[0xc];
11429	u8 active_port[0x4];
11430	u8 reserved_at_30[0x4];
11431	u8 tx_remap_affinity_2[0x4];
11432	u8 reserved_at_38[0x4];
11433	u8 tx_remap_affinity_1[0x4];
11434	};
11435
11436	struct mlx5_ifc_create_lag_out_bits {
11437	u8 status[0x8];
11438	u8 reserved_at_8[0x18];
11439
11440	u8 syndrome[0x20];
11441
11442	u8 reserved_at_40[0x40];
11443	};
11444
11445	struct mlx5_ifc_create_lag_in_bits {
11446	u8 opcode[0x10];
11447	u8 reserved_at_10[0x10];
11448
11449	u8 reserved_at_20[0x10];
11450	u8 op_mod[0x10];
11451
11452	struct mlx5_ifc_lagc_bits ctx;
11453	};
11454
11455	struct mlx5_ifc_modify_lag_out_bits {
11456	u8 status[0x8];
11457	u8 reserved_at_8[0x18];
11458
11459	u8 syndrome[0x20];
11460
11461	u8 reserved_at_40[0x40];
11462	};
11463
11464	struct mlx5_ifc_modify_lag_in_bits {
11465	u8 opcode[0x10];
11466	u8 reserved_at_10[0x10];
11467
11468	u8 reserved_at_20[0x10];
11469	u8 op_mod[0x10];
11470
11471	u8 reserved_at_40[0x20];
11472	u8 field_select[0x20];
11473
11474	struct mlx5_ifc_lagc_bits ctx;
11475	};
11476
11477	struct mlx5_ifc_query_lag_out_bits {
11478	u8 status[0x8];
11479	u8 reserved_at_8[0x18];
11480
11481	u8 syndrome[0x20];
11482
11483	struct mlx5_ifc_lagc_bits ctx;
11484	};
11485
11486	struct mlx5_ifc_query_lag_in_bits {
11487	u8 opcode[0x10];
11488	u8 reserved_at_10[0x10];
11489
11490	u8 reserved_at_20[0x10];
11491	u8 op_mod[0x10];
11492
11493	u8 reserved_at_40[0x40];
11494	};
11495
11496	struct mlx5_ifc_destroy_lag_out_bits {
11497	u8 status[0x8];
11498	u8 reserved_at_8[0x18];
11499
11500	u8 syndrome[0x20];
11501
11502	u8 reserved_at_40[0x40];
11503	};
11504
11505	struct mlx5_ifc_destroy_lag_in_bits {
11506	u8 opcode[0x10];
11507	u8 reserved_at_10[0x10];
11508
11509	u8 reserved_at_20[0x10];
11510	u8 op_mod[0x10];
11511
11512	u8 reserved_at_40[0x40];
11513	};
11514
11515	struct mlx5_ifc_create_vport_lag_out_bits {
11516	u8 status[0x8];
11517	u8 reserved_at_8[0x18];
11518
11519	u8 syndrome[0x20];
11520
11521	u8 reserved_at_40[0x40];
11522	};
11523
11524	struct mlx5_ifc_create_vport_lag_in_bits {
11525	u8 opcode[0x10];
11526	u8 reserved_at_10[0x10];
11527
11528	u8 reserved_at_20[0x10];
11529	u8 op_mod[0x10];
11530
11531	u8 reserved_at_40[0x40];
11532	};
11533
11534	struct mlx5_ifc_destroy_vport_lag_out_bits {
11535	u8 status[0x8];
11536	u8 reserved_at_8[0x18];
11537
11538	u8 syndrome[0x20];
11539
11540	u8 reserved_at_40[0x40];
11541	};
11542
11543	struct mlx5_ifc_destroy_vport_lag_in_bits {
11544	u8 opcode[0x10];
11545	u8 reserved_at_10[0x10];
11546
11547	u8 reserved_at_20[0x10];
11548	u8 op_mod[0x10];
11549
11550	u8 reserved_at_40[0x40];
11551	};
11552
11553	enum {
11554	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11555	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11556	};
11557
11558	struct mlx5_ifc_modify_memic_in_bits {
11559	u8 opcode[0x10];
11560	u8 uid[0x10];
11561
11562	u8 reserved_at_20[0x10];
11563	u8 op_mod[0x10];
11564
11565	u8 reserved_at_40[0x20];
11566
11567	u8 reserved_at_60[0x18];
11568	u8 memic_operation_type[0x8];
11569
11570	u8 memic_start_addr[0x40];
11571
11572	u8 reserved_at_c0[0x140];
11573	};
11574
11575	struct mlx5_ifc_modify_memic_out_bits {
11576	u8 status[0x8];
11577	u8 reserved_at_8[0x18];
11578
11579	u8 syndrome[0x20];
11580
11581	u8 reserved_at_40[0x40];
11582
11583	u8 memic_operation_addr[0x40];
11584
11585	u8 reserved_at_c0[0x140];
11586	};
11587
11588	struct mlx5_ifc_alloc_memic_in_bits {
11589	u8 opcode[0x10];
11590	u8 reserved_at_10[0x10];
11591
11592	u8 reserved_at_20[0x10];
11593	u8 op_mod[0x10];
11594
11595	u8 reserved_at_30[0x20];
11596
11597	u8 reserved_at_40[0x18];
11598	u8 log_memic_addr_alignment[0x8];
11599
11600	u8 range_start_addr[0x40];
11601
11602	u8 range_size[0x20];
11603
11604	u8 memic_size[0x20];
11605	};
11606
11607	struct mlx5_ifc_alloc_memic_out_bits {
11608	u8 status[0x8];
11609	u8 reserved_at_8[0x18];
11610
11611	u8 syndrome[0x20];
11612
11613	u8 memic_start_addr[0x40];
11614	};
11615
11616	struct mlx5_ifc_dealloc_memic_in_bits {
11617	u8 opcode[0x10];
11618	u8 reserved_at_10[0x10];
11619
11620	u8 reserved_at_20[0x10];
11621	u8 op_mod[0x10];
11622
11623	u8 reserved_at_40[0x40];
11624
11625	u8 memic_start_addr[0x40];
11626
11627	u8 memic_size[0x20];
11628
11629	u8 reserved_at_e0[0x20];
11630	};
11631
11632	struct mlx5_ifc_dealloc_memic_out_bits {
11633	u8 status[0x8];
11634	u8 reserved_at_8[0x18];
11635
11636	u8 syndrome[0x20];
11637
11638	u8 reserved_at_40[0x40];
11639	};
11640
11641	struct mlx5_ifc_umem_bits {
11642	u8 reserved_at_0[0x80];
11643
11644	u8 ats[0x1];
11645	u8 reserved_at_81[0x1a];
11646	u8 log_page_size[0x5];
11647
11648	u8 page_offset[0x20];
11649
11650	u8 num_of_mtt[0x40];
11651
11652	struct mlx5_ifc_mtt_bits mtt[];
11653	};
11654
11655	struct mlx5_ifc_uctx_bits {
11656	u8 cap[0x20];
11657
11658	u8 reserved_at_20[0x160];
11659	};
11660
11661	struct mlx5_ifc_sw_icm_bits {
11662	u8 modify_field_select[0x40];
11663
11664	u8 reserved_at_40[0x18];
11665	u8 log_sw_icm_size[0x8];
11666
11667	u8 reserved_at_60[0x20];
11668
11669	u8 sw_icm_start_addr[0x40];
11670
11671	u8 reserved_at_c0[0x140];
11672	};
11673
11674	struct mlx5_ifc_geneve_tlv_option_bits {
11675	u8 modify_field_select[0x40];
11676
11677	u8 reserved_at_40[0x18];
11678	u8 geneve_option_fte_index[0x8];
11679
11680	u8 option_class[0x10];
11681	u8 option_type[0x8];
11682	u8 reserved_at_78[0x3];
11683	u8 option_data_length[0x5];
11684
11685	u8 reserved_at_80[0x180];
11686	};
11687
11688	struct mlx5_ifc_create_umem_in_bits {
11689	u8 opcode[0x10];
11690	u8 uid[0x10];
11691
11692	u8 reserved_at_20[0x10];
11693	u8 op_mod[0x10];
11694
11695	u8 reserved_at_40[0x40];
11696
11697	struct mlx5_ifc_umem_bits umem;
11698	};
11699
11700	struct mlx5_ifc_create_umem_out_bits {
11701	u8 status[0x8];
11702	u8 reserved_at_8[0x18];
11703
11704	u8 syndrome[0x20];
11705
11706	u8 reserved_at_40[0x8];
11707	u8 umem_id[0x18];
11708
11709	u8 reserved_at_60[0x20];
11710	};
11711
11712	struct mlx5_ifc_destroy_umem_in_bits {
11713	u8 opcode[0x10];
11714	u8 uid[0x10];
11715
11716	u8 reserved_at_20[0x10];
11717	u8 op_mod[0x10];
11718
11719	u8 reserved_at_40[0x8];
11720	u8 umem_id[0x18];
11721
11722	u8 reserved_at_60[0x20];
11723	};
11724
11725	struct mlx5_ifc_destroy_umem_out_bits {
11726	u8 status[0x8];
11727	u8 reserved_at_8[0x18];
11728
11729	u8 syndrome[0x20];
11730
11731	u8 reserved_at_40[0x40];
11732	};
11733
11734	struct mlx5_ifc_create_uctx_in_bits {
11735	u8 opcode[0x10];
11736	u8 reserved_at_10[0x10];
11737
11738	u8 reserved_at_20[0x10];
11739	u8 op_mod[0x10];
11740
11741	u8 reserved_at_40[0x40];
11742
11743	struct mlx5_ifc_uctx_bits uctx;
11744	};
11745
11746	struct mlx5_ifc_create_uctx_out_bits {
11747	u8 status[0x8];
11748	u8 reserved_at_8[0x18];
11749
11750	u8 syndrome[0x20];
11751
11752	u8 reserved_at_40[0x10];
11753	u8 uid[0x10];
11754
11755	u8 reserved_at_60[0x20];
11756	};
11757
11758	struct mlx5_ifc_destroy_uctx_in_bits {
11759	u8 opcode[0x10];
11760	u8 reserved_at_10[0x10];
11761
11762	u8 reserved_at_20[0x10];
11763	u8 op_mod[0x10];
11764
11765	u8 reserved_at_40[0x10];
11766	u8 uid[0x10];
11767
11768	u8 reserved_at_60[0x20];
11769	};
11770
11771	struct mlx5_ifc_destroy_uctx_out_bits {
11772	u8 status[0x8];
11773	u8 reserved_at_8[0x18];
11774
11775	u8 syndrome[0x20];
11776
11777	u8 reserved_at_40[0x40];
11778	};
11779
11780	struct mlx5_ifc_create_sw_icm_in_bits {
11781	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11782	struct mlx5_ifc_sw_icm_bits sw_icm;
11783	};
11784
11785	struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11786	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11787	struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11788	};
11789
11790	struct mlx5_ifc_mtrc_string_db_param_bits {
11791	u8 string_db_base_address[0x20];
11792
11793	u8 reserved_at_20[0x8];
11794	u8 string_db_size[0x18];
11795	};
11796
11797	struct mlx5_ifc_mtrc_cap_bits {
11798	u8 trace_owner[0x1];
11799	u8 trace_to_memory[0x1];
11800	u8 reserved_at_2[0x4];
11801	u8 trc_ver[0x2];
11802	u8 reserved_at_8[0x14];
11803	u8 num_string_db[0x4];
11804
11805	u8 first_string_trace[0x8];
11806	u8 num_string_trace[0x8];
11807	u8 reserved_at_30[0x28];
11808
11809	u8 log_max_trace_buffer_size[0x8];
11810
11811	u8 reserved_at_60[0x20];
11812
11813	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11814
11815	u8 reserved_at_280[0x180];
11816	};
11817
11818	struct mlx5_ifc_mtrc_conf_bits {
11819	u8 reserved_at_0[0x1c];
11820	u8 trace_mode[0x4];
11821	u8 reserved_at_20[0x18];
11822	u8 log_trace_buffer_size[0x8];
11823	u8 trace_mkey[0x20];
11824	u8 reserved_at_60[0x3a0];
11825	};
11826
11827	struct mlx5_ifc_mtrc_stdb_bits {
11828	u8 string_db_index[0x4];
11829	u8 reserved_at_4[0x4];
11830	u8 read_size[0x18];
11831	u8 start_offset[0x20];
11832	u8 string_db_data[];
11833	};
11834
11835	struct mlx5_ifc_mtrc_ctrl_bits {
11836	u8 trace_status[0x2];
11837	u8 reserved_at_2[0x2];
11838	u8 arm_event[0x1];
11839	u8 reserved_at_5[0xb];
11840	u8 modify_field_select[0x10];
11841	u8 reserved_at_20[0x2b];
11842	u8 current_timestamp52_32[0x15];
11843	u8 current_timestamp31_0[0x20];
11844	u8 reserved_at_80[0x180];
11845	};
11846
11847	struct mlx5_ifc_host_params_context_bits {
11848	u8 host_number[0x8];
11849	u8 reserved_at_8[0x7];
11850	u8 host_pf_disabled[0x1];
11851	u8 host_num_of_vfs[0x10];
11852
11853	u8 host_total_vfs[0x10];
11854	u8 host_pci_bus[0x10];
11855
11856	u8 reserved_at_40[0x10];
11857	u8 host_pci_device[0x10];
11858
11859	u8 reserved_at_60[0x10];
11860	u8 host_pci_function[0x10];
11861
11862	u8 reserved_at_80[0x180];
11863	};
11864
11865	struct mlx5_ifc_query_esw_functions_in_bits {
11866	u8 opcode[0x10];
11867	u8 reserved_at_10[0x10];
11868
11869	u8 reserved_at_20[0x10];
11870	u8 op_mod[0x10];
11871
11872	u8 reserved_at_40[0x40];
11873	};
11874
11875	struct mlx5_ifc_query_esw_functions_out_bits {
11876	u8 status[0x8];
11877	u8 reserved_at_8[0x18];
11878
11879	u8 syndrome[0x20];
11880
11881	u8 reserved_at_40[0x40];
11882
11883	struct mlx5_ifc_host_params_context_bits host_params_context;
11884
11885	u8 reserved_at_280[0x180];
11886	u8 host_sf_enable[][0x40];
11887	};
11888
11889	struct mlx5_ifc_sf_partition_bits {
11890	u8 reserved_at_0[0x10];
11891	u8 log_num_sf[0x8];
11892	u8 log_sf_bar_size[0x8];
11893	};
11894
11895	struct mlx5_ifc_query_sf_partitions_out_bits {
11896	u8 status[0x8];
11897	u8 reserved_at_8[0x18];
11898
11899	u8 syndrome[0x20];
11900
11901	u8 reserved_at_40[0x18];
11902	u8 num_sf_partitions[0x8];
11903
11904	u8 reserved_at_60[0x20];
11905
11906	struct mlx5_ifc_sf_partition_bits sf_partition[];
11907	};
11908
11909	struct mlx5_ifc_query_sf_partitions_in_bits {
11910	u8 opcode[0x10];
11911	u8 reserved_at_10[0x10];
11912
11913	u8 reserved_at_20[0x10];
11914	u8 op_mod[0x10];
11915
11916	u8 reserved_at_40[0x40];
11917	};
11918
11919	struct mlx5_ifc_dealloc_sf_out_bits {
11920	u8 status[0x8];
11921	u8 reserved_at_8[0x18];
11922
11923	u8 syndrome[0x20];
11924
11925	u8 reserved_at_40[0x40];
11926	};
11927
11928	struct mlx5_ifc_dealloc_sf_in_bits {
11929	u8 opcode[0x10];
11930	u8 reserved_at_10[0x10];
11931
11932	u8 reserved_at_20[0x10];
11933	u8 op_mod[0x10];
11934
11935	u8 reserved_at_40[0x10];
11936	u8 function_id[0x10];
11937
11938	u8 reserved_at_60[0x20];
11939	};
11940
11941	struct mlx5_ifc_alloc_sf_out_bits {
11942	u8 status[0x8];
11943	u8 reserved_at_8[0x18];
11944
11945	u8 syndrome[0x20];
11946
11947	u8 reserved_at_40[0x40];
11948	};
11949
11950	struct mlx5_ifc_alloc_sf_in_bits {
11951	u8 opcode[0x10];
11952	u8 reserved_at_10[0x10];
11953
11954	u8 reserved_at_20[0x10];
11955	u8 op_mod[0x10];
11956
11957	u8 reserved_at_40[0x10];
11958	u8 function_id[0x10];
11959
11960	u8 reserved_at_60[0x20];
11961	};
11962
11963	struct mlx5_ifc_affiliated_event_header_bits {
11964	u8 reserved_at_0[0x10];
11965	u8 obj_type[0x10];
11966
11967	u8 obj_id[0x20];
11968	};
11969
11970	enum {
11971	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11972	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11973	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11974	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11975	};
11976
11977	enum {
11978	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11979	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11980	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11981	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11982	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11983	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
11984	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
11985	};
11986
11987	enum {
11988	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11989	};
11990
11991	enum {
11992	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11993	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11994	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11995	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11996	};
11997
11998	enum {
11999	MLX5_IPSEC_ASO_MODE = 0x0,
12000	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12001	MLX5_IPSEC_ASO_INC_SN = 0x2,
12002	};
12003
12004	struct mlx5_ifc_ipsec_aso_bits {
12005	u8 valid[0x1];
12006	u8 reserved_at_201[0x1];
12007	u8 mode[0x2];
12008	u8 window_sz[0x2];
12009	u8 soft_lft_arm[0x1];
12010	u8 hard_lft_arm[0x1];
12011	u8 remove_flow_enable[0x1];
12012	u8 esn_event_arm[0x1];
12013	u8 reserved_at_20a[0x16];
12014
12015	u8 remove_flow_pkt_cnt[0x20];
12016
12017	u8 remove_flow_soft_lft[0x20];
12018
12019	u8 reserved_at_260[0x80];
12020
12021	u8 mode_parameter[0x20];
12022
12023	u8 replay_protection_window[0x100];
12024	};
12025
12026	struct mlx5_ifc_ipsec_obj_bits {
12027	u8 modify_field_select[0x40];
12028	u8 full_offload[0x1];
12029	u8 reserved_at_41[0x1];
12030	u8 esn_en[0x1];
12031	u8 esn_overlap[0x1];
12032	u8 reserved_at_44[0x2];
12033	u8 icv_length[0x2];
12034	u8 reserved_at_48[0x4];
12035	u8 aso_return_reg[0x4];
12036	u8 reserved_at_50[0x10];
12037
12038	u8 esn_msb[0x20];
12039
12040	u8 reserved_at_80[0x8];
12041	u8 dekn[0x18];
12042
12043	u8 salt[0x20];
12044
12045	u8 implicit_iv[0x40];
12046
12047	u8 reserved_at_100[0x8];
12048	u8 ipsec_aso_access_pd[0x18];
12049	u8 reserved_at_120[0xe0];
12050
12051	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12052	};
12053
12054	struct mlx5_ifc_create_ipsec_obj_in_bits {
12055	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12056	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12057	};
12058
12059	enum {
12060	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12061	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12062	};
12063
12064	struct mlx5_ifc_query_ipsec_obj_out_bits {
12065	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12066	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12067	};
12068
12069	struct mlx5_ifc_modify_ipsec_obj_in_bits {
12070	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12071	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12072	};
12073
12074	enum {
12075	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12076	};
12077
12078	enum {
12079	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12080	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12081	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12082	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12083	};
12084
12085	#define MLX5_MACSEC_ASO_INC_SN 0x2
12086	#define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12087
12088	struct mlx5_ifc_macsec_aso_bits {
12089	u8 valid[0x1];
12090	u8 reserved_at_1[0x1];
12091	u8 mode[0x2];
12092	u8 window_size[0x2];
12093	u8 soft_lifetime_arm[0x1];
12094	u8 hard_lifetime_arm[0x1];
12095	u8 remove_flow_enable[0x1];
12096	u8 epn_event_arm[0x1];
12097	u8 reserved_at_a[0x16];
12098
12099	u8 remove_flow_packet_count[0x20];
12100
12101	u8 remove_flow_soft_lifetime[0x20];
12102
12103	u8 reserved_at_60[0x80];
12104
12105	u8 mode_parameter[0x20];
12106
12107	u8 replay_protection_window[8][0x20];
12108	};
12109
12110	struct mlx5_ifc_macsec_offload_obj_bits {
12111	u8 modify_field_select[0x40];
12112
12113	u8 confidentiality_en[0x1];
12114	u8 reserved_at_41[0x1];
12115	u8 epn_en[0x1];
12116	u8 epn_overlap[0x1];
12117	u8 reserved_at_44[0x2];
12118	u8 confidentiality_offset[0x2];
12119	u8 reserved_at_48[0x4];
12120	u8 aso_return_reg[0x4];
12121	u8 reserved_at_50[0x10];
12122
12123	u8 epn_msb[0x20];
12124
12125	u8 reserved_at_80[0x8];
12126	u8 dekn[0x18];
12127
12128	u8 reserved_at_a0[0x20];
12129
12130	u8 sci[0x40];
12131
12132	u8 reserved_at_100[0x8];
12133	u8 macsec_aso_access_pd[0x18];
12134
12135	u8 reserved_at_120[0x60];
12136
12137	u8 salt[3][0x20];
12138
12139	u8 reserved_at_1e0[0x20];
12140
12141	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12142	};
12143
12144	struct mlx5_ifc_create_macsec_obj_in_bits {
12145	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12146	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12147	};
12148
12149	struct mlx5_ifc_modify_macsec_obj_in_bits {
12150	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12151	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12152	};
12153
12154	enum {
12155	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12156	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12157	};
12158
12159	struct mlx5_ifc_query_macsec_obj_out_bits {
12160	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12161	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12162	};
12163
12164	struct mlx5_ifc_wrapped_dek_bits {
12165	u8 gcm_iv[0x60];
12166
12167	u8 reserved_at_60[0x20];
12168
12169	u8 const0[0x1];
12170	u8 key_size[0x1];
12171	u8 reserved_at_82[0x2];
12172	u8 key2_invalid[0x1];
12173	u8 reserved_at_85[0x3];
12174	u8 pd[0x18];
12175
12176	u8 key_purpose[0x5];
12177	u8 reserved_at_a5[0x13];
12178	u8 kek_id[0x8];
12179
12180	u8 reserved_at_c0[0x40];
12181
12182	u8 key1[0x8][0x20];
12183
12184	u8 key2[0x8][0x20];
12185
12186	u8 reserved_at_300[0x40];
12187
12188	u8 const1[0x1];
12189	u8 reserved_at_341[0x1f];
12190
12191	u8 reserved_at_360[0x20];
12192
12193	u8 auth_tag[0x80];
12194	};
12195
12196	struct mlx5_ifc_encryption_key_obj_bits {
12197	u8 modify_field_select[0x40];
12198
12199	u8 state[0x8];
12200	u8 sw_wrapped[0x1];
12201	u8 reserved_at_49[0xb];
12202	u8 key_size[0x4];
12203	u8 reserved_at_58[0x4];
12204	u8 key_purpose[0x4];
12205
12206	u8 reserved_at_60[0x8];
12207	u8 pd[0x18];
12208
12209	u8 reserved_at_80[0x100];
12210
12211	u8 opaque[0x40];
12212
12213	u8 reserved_at_1c0[0x40];
12214
12215	u8 key[8][0x80];
12216
12217	u8 sw_wrapped_dek[8][0x80];
12218
12219	u8 reserved_at_a00[0x600];
12220	};
12221
12222	struct mlx5_ifc_create_encryption_key_in_bits {
12223	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12224	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12225	};
12226
12227	struct mlx5_ifc_modify_encryption_key_in_bits {
12228	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12229	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12230	};
12231
12232	enum {
12233	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
12234	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
12235	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
12236	MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
12237	};
12238
12239	struct mlx5_ifc_flow_meter_parameters_bits {
12240	u8 valid[0x1];
12241	u8 bucket_overflow[0x1];
12242	u8 start_color[0x2];
12243	u8 both_buckets_on_green[0x1];
12244	u8 reserved_at_5[0x1];
12245	u8 meter_mode[0x2];
12246	u8 reserved_at_8[0x18];
12247
12248	u8 reserved_at_20[0x20];
12249
12250	u8 reserved_at_40[0x3];
12251	u8 cbs_exponent[0x5];
12252	u8 cbs_mantissa[0x8];
12253	u8 reserved_at_50[0x3];
12254	u8 cir_exponent[0x5];
12255	u8 cir_mantissa[0x8];
12256
12257	u8 reserved_at_60[0x20];
12258
12259	u8 reserved_at_80[0x3];
12260	u8 ebs_exponent[0x5];
12261	u8 ebs_mantissa[0x8];
12262	u8 reserved_at_90[0x3];
12263	u8 eir_exponent[0x5];
12264	u8 eir_mantissa[0x8];
12265
12266	u8 reserved_at_a0[0x60];
12267	};
12268
12269	struct mlx5_ifc_flow_meter_aso_obj_bits {
12270	u8 modify_field_select[0x40];
12271
12272	u8 reserved_at_40[0x40];
12273
12274	u8 reserved_at_80[0x8];
12275	u8 meter_aso_access_pd[0x18];
12276
12277	u8 reserved_at_a0[0x160];
12278
12279	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12280	};
12281
12282	struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12283	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12284	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12285	};
12286
12287	struct mlx5_ifc_int_kek_obj_bits {
12288	u8 modify_field_select[0x40];
12289
12290	u8 state[0x8];
12291	u8 auto_gen[0x1];
12292	u8 reserved_at_49[0xb];
12293	u8 key_size[0x4];
12294	u8 reserved_at_58[0x8];
12295
12296	u8 reserved_at_60[0x8];
12297	u8 pd[0x18];
12298
12299	u8 reserved_at_80[0x180];
12300	u8 key[8][0x80];
12301
12302	u8 reserved_at_600[0x200];
12303	};
12304
12305	struct mlx5_ifc_create_int_kek_obj_in_bits {
12306	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12307	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12308	};
12309
12310	struct mlx5_ifc_create_int_kek_obj_out_bits {
12311	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12312	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12313	};
12314
12315	struct mlx5_ifc_sampler_obj_bits {
12316	u8 modify_field_select[0x40];
12317
12318	u8 table_type[0x8];
12319	u8 level[0x8];
12320	u8 reserved_at_50[0xf];
12321	u8 ignore_flow_level[0x1];
12322
12323	u8 sample_ratio[0x20];
12324
12325	u8 reserved_at_80[0x8];
12326	u8 sample_table_id[0x18];
12327
12328	u8 reserved_at_a0[0x8];
12329	u8 default_table_id[0x18];
12330
12331	u8 sw_steering_icm_address_rx[0x40];
12332	u8 sw_steering_icm_address_tx[0x40];
12333
12334	u8 reserved_at_140[0xa0];
12335	};
12336
12337	struct mlx5_ifc_create_sampler_obj_in_bits {
12338	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12339	struct mlx5_ifc_sampler_obj_bits sampler_object;
12340	};
12341
12342	struct mlx5_ifc_query_sampler_obj_out_bits {
12343	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12344	struct mlx5_ifc_sampler_obj_bits sampler_object;
12345	};
12346
12347	enum {
12348	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12349	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12350	};
12351
12352	enum {
12353	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12354	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12355	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12356	};
12357
12358	struct mlx5_ifc_tls_static_params_bits {
12359	u8 const_2[0x2];
12360	u8 tls_version[0x4];
12361	u8 const_1[0x2];
12362	u8 reserved_at_8[0x14];
12363	u8 encryption_standard[0x4];
12364
12365	u8 reserved_at_20[0x20];
12366
12367	u8 initial_record_number[0x40];
12368
12369	u8 resync_tcp_sn[0x20];
12370
12371	u8 gcm_iv[0x20];
12372
12373	u8 implicit_iv[0x40];
12374
12375	u8 reserved_at_100[0x8];
12376	u8 dek_index[0x18];
12377
12378	u8 reserved_at_120[0xe0];
12379	};
12380
12381	struct mlx5_ifc_tls_progress_params_bits {
12382	u8 next_record_tcp_sn[0x20];
12383
12384	u8 hw_resync_tcp_sn[0x20];
12385
12386	u8 record_tracker_state[0x2];
12387	u8 auth_state[0x2];
12388	u8 reserved_at_44[0x4];
12389	u8 hw_offset_record_number[0x18];
12390	};
12391
12392	enum {
12393	MLX5_MTT_PERM_READ = 1 << 0,
12394	MLX5_MTT_PERM_WRITE = 1 << 1,
12395	MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12396	};
12397
12398	enum {
12399	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
12400	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
12401	};
12402
12403	struct mlx5_ifc_suspend_vhca_in_bits {
12404	u8 opcode[0x10];
12405	u8 uid[0x10];
12406
12407	u8 reserved_at_20[0x10];
12408	u8 op_mod[0x10];
12409
12410	u8 reserved_at_40[0x10];
12411	u8 vhca_id[0x10];
12412
12413	u8 reserved_at_60[0x20];
12414	};
12415
12416	struct mlx5_ifc_suspend_vhca_out_bits {
12417	u8 status[0x8];
12418	u8 reserved_at_8[0x18];
12419
12420	u8 syndrome[0x20];
12421
12422	u8 reserved_at_40[0x40];
12423	};
12424
12425	enum {
12426	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
12427	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
12428	};
12429
12430	struct mlx5_ifc_resume_vhca_in_bits {
12431	u8 opcode[0x10];
12432	u8 uid[0x10];
12433
12434	u8 reserved_at_20[0x10];
12435	u8 op_mod[0x10];
12436
12437	u8 reserved_at_40[0x10];
12438	u8 vhca_id[0x10];
12439
12440	u8 reserved_at_60[0x20];
12441	};
12442
12443	struct mlx5_ifc_resume_vhca_out_bits {
12444	u8 status[0x8];
12445	u8 reserved_at_8[0x18];
12446
12447	u8 syndrome[0x20];
12448
12449	u8 reserved_at_40[0x40];
12450	};
12451
12452	struct mlx5_ifc_query_vhca_migration_state_in_bits {
12453	u8 opcode[0x10];
12454	u8 uid[0x10];
12455
12456	u8 reserved_at_20[0x10];
12457	u8 op_mod[0x10];
12458
12459	u8 incremental[0x1];
12460	u8 chunk[0x1];
12461	u8 reserved_at_42[0xe];
12462	u8 vhca_id[0x10];
12463
12464	u8 reserved_at_60[0x20];
12465	};
12466
12467	struct mlx5_ifc_query_vhca_migration_state_out_bits {
12468	u8 status[0x8];
12469	u8 reserved_at_8[0x18];
12470
12471	u8 syndrome[0x20];
12472
12473	u8 reserved_at_40[0x40];
12474
12475	u8 required_umem_size[0x20];
12476
12477	u8 reserved_at_a0[0x20];
12478
12479	u8 remaining_total_size[0x40];
12480
12481	u8 reserved_at_100[0x100];
12482	};
12483
12484	struct mlx5_ifc_save_vhca_state_in_bits {
12485	u8 opcode[0x10];
12486	u8 uid[0x10];
12487
12488	u8 reserved_at_20[0x10];
12489	u8 op_mod[0x10];
12490
12491	u8 incremental[0x1];
12492	u8 set_track[0x1];
12493	u8 reserved_at_42[0xe];
12494	u8 vhca_id[0x10];
12495
12496	u8 reserved_at_60[0x20];
12497
12498	u8 va[0x40];
12499
12500	u8 mkey[0x20];
12501
12502	u8 size[0x20];
12503	};
12504
12505	struct mlx5_ifc_save_vhca_state_out_bits {
12506	u8 status[0x8];
12507	u8 reserved_at_8[0x18];
12508
12509	u8 syndrome[0x20];
12510
12511	u8 actual_image_size[0x20];
12512
12513	u8 next_required_umem_size[0x20];
12514	};
12515
12516	struct mlx5_ifc_load_vhca_state_in_bits {
12517	u8 opcode[0x10];
12518	u8 uid[0x10];
12519
12520	u8 reserved_at_20[0x10];
12521	u8 op_mod[0x10];
12522
12523	u8 reserved_at_40[0x10];
12524	u8 vhca_id[0x10];
12525
12526	u8 reserved_at_60[0x20];
12527
12528	u8 va[0x40];
12529
12530	u8 mkey[0x20];
12531
12532	u8 size[0x20];
12533	};
12534
12535	struct mlx5_ifc_load_vhca_state_out_bits {
12536	u8 status[0x8];
12537	u8 reserved_at_8[0x18];
12538
12539	u8 syndrome[0x20];
12540
12541	u8 reserved_at_40[0x40];
12542	};
12543
12544	struct mlx5_ifc_adv_virtualization_cap_bits {
12545	u8 reserved_at_0[0x3];
12546	u8 pg_track_log_max_num[0x5];
12547	u8 pg_track_max_num_range[0x8];
12548	u8 pg_track_log_min_addr_space[0x8];
12549	u8 pg_track_log_max_addr_space[0x8];
12550
12551	u8 reserved_at_20[0x3];
12552	u8 pg_track_log_min_msg_size[0x5];
12553	u8 reserved_at_28[0x3];
12554	u8 pg_track_log_max_msg_size[0x5];
12555	u8 reserved_at_30[0x3];
12556	u8 pg_track_log_min_page_size[0x5];
12557	u8 reserved_at_38[0x3];
12558	u8 pg_track_log_max_page_size[0x5];
12559
12560	u8 reserved_at_40[0x7c0];
12561	};
12562
12563	struct mlx5_ifc_page_track_report_entry_bits {
12564	u8 dirty_address_high[0x20];
12565
12566	u8 dirty_address_low[0x20];
12567	};
12568
12569	enum {
12570	MLX5_PAGE_TRACK_STATE_TRACKING,
12571	MLX5_PAGE_TRACK_STATE_REPORTING,
12572	MLX5_PAGE_TRACK_STATE_ERROR,
12573	};
12574
12575	struct mlx5_ifc_page_track_range_bits {
12576	u8 start_address[0x40];
12577
12578	u8 length[0x40];
12579	};
12580
12581	struct mlx5_ifc_page_track_bits {
12582	u8 modify_field_select[0x40];
12583
12584	u8 reserved_at_40[0x10];
12585	u8 vhca_id[0x10];
12586
12587	u8 reserved_at_60[0x20];
12588
12589	u8 state[0x4];
12590	u8 track_type[0x4];
12591	u8 log_addr_space_size[0x8];
12592	u8 reserved_at_90[0x3];
12593	u8 log_page_size[0x5];
12594	u8 reserved_at_98[0x3];
12595	u8 log_msg_size[0x5];
12596
12597	u8 reserved_at_a0[0x8];
12598	u8 reporting_qpn[0x18];
12599
12600	u8 reserved_at_c0[0x18];
12601	u8 num_ranges[0x8];
12602
12603	u8 reserved_at_e0[0x20];
12604
12605	u8 range_start_address[0x40];
12606
12607	u8 length[0x40];
12608
12609	struct mlx5_ifc_page_track_range_bits track_range[0];
12610	};
12611
12612	struct mlx5_ifc_create_page_track_obj_in_bits {
12613	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12614	struct mlx5_ifc_page_track_bits obj_context;
12615	};
12616
12617	struct mlx5_ifc_modify_page_track_obj_in_bits {
12618	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12619	struct mlx5_ifc_page_track_bits obj_context;
12620	};
12621
12622	struct mlx5_ifc_msecq_reg_bits {
12623	u8 reserved_at_0[0x20];
12624
12625	u8 reserved_at_20[0x12];
12626	u8 network_option[0x2];
12627	u8 local_ssm_code[0x4];
12628	u8 local_enhanced_ssm_code[0x8];
12629
12630	u8 local_clock_identity[0x40];
12631
12632	u8 reserved_at_80[0x180];
12633	};
12634
12635	enum {
12636	MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
12637	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1),
12638	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2),
12639	};
12640
12641	enum mlx5_msees_admin_status {
12642	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
12643	MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
12644	};
12645
12646	enum mlx5_msees_oper_status {
12647	MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
12648	MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
12649	MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
12650	MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
12651	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
12652	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
12653	};
12654
12655	struct mlx5_ifc_msees_reg_bits {
12656	u8 reserved_at_0[0x8];
12657	u8 local_port[0x8];
12658	u8 pnat[0x2];
12659	u8 lp_msb[0x2];
12660	u8 reserved_at_14[0xc];
12661
12662	u8 field_select[0x20];
12663
12664	u8 admin_status[0x4];
12665	u8 oper_status[0x4];
12666	u8 ho_acq[0x1];
12667	u8 reserved_at_49[0xc];
12668	u8 admin_freq_measure[0x1];
12669	u8 oper_freq_measure[0x1];
12670	u8 failure_reason[0x9];
12671
12672	u8 frequency_diff[0x20];
12673
12674	u8 reserved_at_80[0x180];
12675	};
12676
12677	#endif /* MLX5_IFC_H */
12678