1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39/*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
50 */
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55/* pci_slot represents a physical slot */
56struct pci_slot {
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69/* File state for mmap()s on /proc/bus/pci/X/Y */
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75/* For PCI devices, the region numbers are assigned this way: */
76enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
84 /* Device-specific resources */
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90 /* Resources assigned to buses behind the bridge */
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97 /* Total resources associated with a PCI device */
98 PCI_NUM_RESOURCES,
99
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104/**
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
111 *
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
114 */
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123/* The number of legacy PCI INTx interrupts */
124#define PCI_NUM_INTX 4
125
126/*
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
129 */
130typedef int __bitwise pci_power_t;
131
132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
137#define PCI_UNKNOWN ((pci_power_t __force) 5)
138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140/* Remember to update this when the list above changes! */
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
145 return pci_power_names[1 + (__force int) state];
146}
147
148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
152
153/**
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
157 */
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208};
209
210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
221};
222
223/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
230 PCIE_LNK_X12 = 0x0c,
231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
234};
235
236/* Based on the PCI Hotplug Spec, but some values are made up by us */
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
264enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
265enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
266
267struct pci_cap_saved_data {
268 u16 cap_nr;
269 bool cap_extended;
270 unsigned int size;
271 u32 data[0];
272};
273
274struct pci_cap_saved_state {
275 struct hlist_node next;
276 struct pci_cap_saved_data cap;
277};
278
279struct irq_affinity;
280struct pcie_link_state;
281struct pci_vpd;
282struct pci_sriov;
283struct pci_ats;
284
285/* The pci_dev structure describes PCI devices */
286struct pci_dev {
287 struct list_head bus_list; /* Node in per-bus list */
288 struct pci_bus *bus; /* Bus this device is on */
289 struct pci_bus *subordinate; /* Bus this device bridges to */
290
291 void *sysdata; /* Hook for sys-specific extension */
292 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
293 struct pci_slot *slot; /* Physical slot this device is in */
294
295 unsigned int devfn; /* Encoded device & function index */
296 unsigned short vendor;
297 unsigned short device;
298 unsigned short subsystem_vendor;
299 unsigned short subsystem_device;
300 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
301 u8 revision; /* PCI revision, low byte of class word */
302 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
303#ifdef CONFIG_PCIEAER
304 u16 aer_cap; /* AER capability offset */
305 struct aer_stats *aer_stats; /* AER stats for this device */
306#endif
307 u8 pcie_cap; /* PCIe capability offset */
308 u8 msi_cap; /* MSI capability offset */
309 u8 msix_cap; /* MSI-X capability offset */
310 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
311 u8 rom_base_reg; /* Config register controlling ROM */
312 u8 pin; /* Interrupt pin this device uses */
313 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
314 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
315
316 struct pci_driver *driver; /* Driver bound to this device */
317 u64 dma_mask; /* Mask of the bits of bus address this
318 device implements. Normally this is
319 0xffffffff. You only need to change
320 this if your device has broken DMA
321 or supports 64-bit transfers. */
322
323 struct device_dma_parameters dma_parms;
324
325 pci_power_t current_state; /* Current operating state. In ACPI,
326 this is D0-D3, D0 being fully
327 functional, and D3 being off. */
328 u8 pm_cap; /* PM capability offset */
329 unsigned int pme_support:5; /* Bitmask of states from which PME#
330 can be generated */
331 unsigned int pme_poll:1; /* Poll device's PME status bit */
332 unsigned int d1_support:1; /* Low power state D1 is supported */
333 unsigned int d2_support:1; /* Low power state D2 is supported */
334 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold:1; /* D3cold is forbidden */
336 unsigned int bridge_d3:1; /* Allow D3 for bridge */
337 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
338 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
339 decoding during BAR sizing */
340 unsigned int wakeup_prepared:1;
341 unsigned int runtime_d3cold:1; /* Whether go through runtime
342 D3cold, not set for devices
343 powered on/off by the
344 corresponding bridge */
345 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
346 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
347 controlled exclusively by
348 user sysfs */
349 unsigned int d3_delay; /* D3->D0 transition time in ms */
350 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
351
352#ifdef CONFIG_PCIEASPM
353 struct pcie_link_state *link_state; /* ASPM link state */
354 unsigned int ltr_path:1; /* Latency Tolerance Reporting
355 supported from root to here */
356#endif
357 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
358
359 pci_channel_state_t error_state; /* Current connectivity state */
360 struct device dev; /* Generic device interface */
361
362 int cfg_size; /* Size of config space */
363
364 /*
365 * Instead of touching interrupt line and base address registers
366 * directly, use the values stored here. They might be different!
367 */
368 unsigned int irq;
369 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
370
371 bool match_driver; /* Skip attaching driver */
372
373 unsigned int transparent:1; /* Subtractive decode bridge */
374 unsigned int multifunction:1; /* Multi-function device */
375
376 unsigned int is_busmaster:1; /* Is busmaster */
377 unsigned int no_msi:1; /* May not use MSI */
378 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
379 unsigned int block_cfg_access:1; /* Config space access blocked */
380 unsigned int broken_parity_status:1; /* Generates false positive parity */
381 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
382 unsigned int msi_enabled:1;
383 unsigned int msix_enabled:1;
384 unsigned int ari_enabled:1; /* ARI forwarding */
385 unsigned int ats_enabled:1; /* Address Translation Svc */
386 unsigned int pasid_enabled:1; /* Process Address Space ID */
387 unsigned int pri_enabled:1; /* Page Request Interface */
388 unsigned int is_managed:1;
389 unsigned int needs_freset:1; /* Requires fundamental reset */
390 unsigned int state_saved:1;
391 unsigned int is_physfn:1;
392 unsigned int is_virtfn:1;
393 unsigned int reset_fn:1;
394 unsigned int is_hotplug_bridge:1;
395 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
396 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
397 unsigned int __aer_firmware_first_valid:1;
398 unsigned int __aer_firmware_first:1;
399 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
400 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
401 unsigned int irq_managed:1;
402 unsigned int has_secondary_link:1;
403 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
404 unsigned int is_probed:1; /* Device probing in progress */
405 pci_dev_flags_t dev_flags;
406 atomic_t enable_cnt; /* pci_enable_device has been called */
407
408 u32 saved_config_space[16]; /* Config space saved at suspend time */
409 struct hlist_head saved_cap_space;
410 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
411 int rom_attr_enabled; /* Display of ROM attribute enabled? */
412 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
413 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
414
415#ifdef CONFIG_HOTPLUG_PCI_PCIE
416 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
417#endif
418#ifdef CONFIG_PCIE_PTM
419 unsigned int ptm_root:1;
420 unsigned int ptm_enabled:1;
421 u8 ptm_granularity;
422#endif
423#ifdef CONFIG_PCI_MSI
424 const struct attribute_group **msi_irq_groups;
425#endif
426 struct pci_vpd *vpd;
427#ifdef CONFIG_PCI_ATS
428 union {
429 struct pci_sriov *sriov; /* PF: SR-IOV info */
430 struct pci_dev *physfn; /* VF: related PF */
431 };
432 u16 ats_cap; /* ATS Capability offset */
433 u8 ats_stu; /* ATS Smallest Translation Unit */
434 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
435#endif
436#ifdef CONFIG_PCI_PRI
437 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
438#endif
439#ifdef CONFIG_PCI_PASID
440 u16 pasid_features;
441#endif
442 phys_addr_t rom; /* Physical address if not from BAR */
443 size_t romlen; /* Length if not from BAR */
444 char *driver_override; /* Driver name to force a match */
445
446 unsigned long priv_flags; /* Private flags for the PCI driver */
447};
448
449static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
450{
451#ifdef CONFIG_PCI_IOV
452 if (dev->is_virtfn)
453 dev = dev->physfn;
454#endif
455 return dev;
456}
457
458struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
459
460#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
461#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
462
463static inline int pci_channel_offline(struct pci_dev *pdev)
464{
465 return (pdev->error_state != pci_channel_io_normal);
466}
467
468struct pci_host_bridge {
469 struct device dev;
470 struct pci_bus *bus; /* Root bus */
471 struct pci_ops *ops;
472 void *sysdata;
473 int busnr;
474 struct list_head windows; /* resource_entry */
475 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
476 int (*map_irq)(const struct pci_dev *, u8, u8);
477 void (*release_fn)(struct pci_host_bridge *);
478 void *release_data;
479 struct msi_controller *msi;
480 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
481 unsigned int no_ext_tags:1; /* No Extended Tags */
482 unsigned int native_aer:1; /* OS may use PCIe AER */
483 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
484 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
485 unsigned int native_pme:1; /* OS may use PCIe PME */
486 unsigned int native_ltr:1; /* OS may use PCIe LTR */
487 /* Resource alignment requirements */
488 resource_size_t (*align_resource)(struct pci_dev *dev,
489 const struct resource *res,
490 resource_size_t start,
491 resource_size_t size,
492 resource_size_t align);
493 unsigned long private[0] ____cacheline_aligned;
494};
495
496#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
497
498static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
499{
500 return (void *)bridge->private;
501}
502
503static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
504{
505 return container_of(priv, struct pci_host_bridge, private);
506}
507
508struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
509struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
510 size_t priv);
511void pci_free_host_bridge(struct pci_host_bridge *bridge);
512struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
513
514void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
515 void (*release_fn)(struct pci_host_bridge *),
516 void *release_data);
517
518int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
519
520/*
521 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
522 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
523 * buses below host bridges or subtractive decode bridges) go in the list.
524 * Use pci_bus_for_each_resource() to iterate through all the resources.
525 */
526
527/*
528 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
529 * and there's no way to program the bridge with the details of the window.
530 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
531 * decode bit set, because they are explicit and can be programmed with _SRS.
532 */
533#define PCI_SUBTRACTIVE_DECODE 0x1
534
535struct pci_bus_resource {
536 struct list_head list;
537 struct resource *res;
538 unsigned int flags;
539};
540
541#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
542
543struct pci_bus {
544 struct list_head node; /* Node in list of buses */
545 struct pci_bus *parent; /* Parent bus this bridge is on */
546 struct list_head children; /* List of child buses */
547 struct list_head devices; /* List of devices on this bus */
548 struct pci_dev *self; /* Bridge device as seen by parent */
549 struct list_head slots; /* List of slots on this bus;
550 protected by pci_slot_mutex */
551 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
552 struct list_head resources; /* Address space routed to this bus */
553 struct resource busn_res; /* Bus numbers routed to this bus */
554
555 struct pci_ops *ops; /* Configuration access functions */
556 struct msi_controller *msi; /* MSI controller */
557 void *sysdata; /* Hook for sys-specific extension */
558 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
559
560 unsigned char number; /* Bus number */
561 unsigned char primary; /* Number of primary bridge */
562 unsigned char max_bus_speed; /* enum pci_bus_speed */
563 unsigned char cur_bus_speed; /* enum pci_bus_speed */
564#ifdef CONFIG_PCI_DOMAINS_GENERIC
565 int domain_nr;
566#endif
567
568 char name[48];
569
570 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
571 pci_bus_flags_t bus_flags; /* Inherited by child buses */
572 struct device *bridge;
573 struct device dev;
574 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
575 struct bin_attribute *legacy_mem; /* Legacy mem */
576 unsigned int is_added:1;
577};
578
579#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
580
581/*
582 * Returns true if the PCI bus is root (behind host-PCI bridge),
583 * false otherwise
584 *
585 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
586 * This is incorrect because "virtual" buses added for SR-IOV (via
587 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
588 */
589static inline bool pci_is_root_bus(struct pci_bus *pbus)
590{
591 return !(pbus->parent);
592}
593
594/**
595 * pci_is_bridge - check if the PCI device is a bridge
596 * @dev: PCI device
597 *
598 * Return true if the PCI device is bridge whether it has subordinate
599 * or not.
600 */
601static inline bool pci_is_bridge(struct pci_dev *dev)
602{
603 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
604 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
605}
606
607#define for_each_pci_bridge(dev, bus) \
608 list_for_each_entry(dev, &bus->devices, bus_list) \
609 if (!pci_is_bridge(dev)) {} else
610
611static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
612{
613 dev = pci_physfn(dev);
614 if (pci_is_root_bus(dev->bus))
615 return NULL;
616
617 return dev->bus->self;
618}
619
620struct device *pci_get_host_bridge_device(struct pci_dev *dev);
621void pci_put_host_bridge_device(struct device *dev);
622
623#ifdef CONFIG_PCI_MSI
624static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
625{
626 return pci_dev->msi_enabled || pci_dev->msix_enabled;
627}
628#else
629static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
630#endif
631
632/* Error values that may be returned by PCI functions */
633#define PCIBIOS_SUCCESSFUL 0x00
634#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
635#define PCIBIOS_BAD_VENDOR_ID 0x83
636#define PCIBIOS_DEVICE_NOT_FOUND 0x86
637#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
638#define PCIBIOS_SET_FAILED 0x88
639#define PCIBIOS_BUFFER_TOO_SMALL 0x89
640
641/* Translate above to generic errno for passing back through non-PCI code */
642static inline int pcibios_err_to_errno(int err)
643{
644 if (err <= PCIBIOS_SUCCESSFUL)
645 return err; /* Assume already errno */
646
647 switch (err) {
648 case PCIBIOS_FUNC_NOT_SUPPORTED:
649 return -ENOENT;
650 case PCIBIOS_BAD_VENDOR_ID:
651 return -ENOTTY;
652 case PCIBIOS_DEVICE_NOT_FOUND:
653 return -ENODEV;
654 case PCIBIOS_BAD_REGISTER_NUMBER:
655 return -EFAULT;
656 case PCIBIOS_SET_FAILED:
657 return -EIO;
658 case PCIBIOS_BUFFER_TOO_SMALL:
659 return -ENOSPC;
660 }
661
662 return -ERANGE;
663}
664
665/* Low-level architecture-dependent routines */
666
667struct pci_ops {
668 int (*add_bus)(struct pci_bus *bus);
669 void (*remove_bus)(struct pci_bus *bus);
670 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
671 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
672 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
673};
674
675/*
676 * ACPI needs to be able to access PCI config space before we've done a
677 * PCI bus scan and created pci_bus structures.
678 */
679int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
680 int reg, int len, u32 *val);
681int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
682 int reg, int len, u32 val);
683
684#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
685typedef u64 pci_bus_addr_t;
686#else
687typedef u32 pci_bus_addr_t;
688#endif
689
690struct pci_bus_region {
691 pci_bus_addr_t start;
692 pci_bus_addr_t end;
693};
694
695struct pci_dynids {
696 spinlock_t lock; /* Protects list, index */
697 struct list_head list; /* For IDs added at runtime */
698};
699
700
701/*
702 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
703 * a set of callbacks in struct pci_error_handlers, that device driver
704 * will be notified of PCI bus errors, and will be driven to recovery
705 * when an error occurs.
706 */
707
708typedef unsigned int __bitwise pci_ers_result_t;
709
710enum pci_ers_result {
711 /* No result/none/not supported in device driver */
712 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
713
714 /* Device driver can recover without slot reset */
715 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
716
717 /* Device driver wants slot to be reset */
718 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
719
720 /* Device has completely failed, is unrecoverable */
721 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
722
723 /* Device driver is fully recovered and operational */
724 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
725
726 /* No AER capabilities registered for the driver */
727 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
728};
729
730/* PCI bus error event callbacks */
731struct pci_error_handlers {
732 /* PCI bus error detected on this device */
733 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
734 enum pci_channel_state error);
735
736 /* MMIO has been re-enabled, but not DMA */
737 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
738
739 /* PCI slot has been reset */
740 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
741
742 /* PCI function reset prepare or completed */
743 void (*reset_prepare)(struct pci_dev *dev);
744 void (*reset_done)(struct pci_dev *dev);
745
746 /* Device driver may resume normal operations */
747 void (*resume)(struct pci_dev *dev);
748};
749
750
751struct module;
752struct pci_driver {
753 struct list_head node;
754 const char *name;
755 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
756 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
757 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
758 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
759 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
760 int (*resume_early)(struct pci_dev *dev);
761 int (*resume) (struct pci_dev *dev); /* Device woken up */
762 void (*shutdown) (struct pci_dev *dev);
763 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
764 const struct pci_error_handlers *err_handler;
765 const struct attribute_group **groups;
766 struct device_driver driver;
767 struct pci_dynids dynids;
768};
769
770#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
771
772/**
773 * PCI_DEVICE - macro used to describe a specific PCI device
774 * @vend: the 16 bit PCI Vendor ID
775 * @dev: the 16 bit PCI Device ID
776 *
777 * This macro is used to create a struct pci_device_id that matches a
778 * specific device. The subvendor and subdevice fields will be set to
779 * PCI_ANY_ID.
780 */
781#define PCI_DEVICE(vend,dev) \
782 .vendor = (vend), .device = (dev), \
783 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
784
785/**
786 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
787 * @vend: the 16 bit PCI Vendor ID
788 * @dev: the 16 bit PCI Device ID
789 * @subvend: the 16 bit PCI Subvendor ID
790 * @subdev: the 16 bit PCI Subdevice ID
791 *
792 * This macro is used to create a struct pci_device_id that matches a
793 * specific device with subsystem information.
794 */
795#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
796 .vendor = (vend), .device = (dev), \
797 .subvendor = (subvend), .subdevice = (subdev)
798
799/**
800 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
801 * @dev_class: the class, subclass, prog-if triple for this device
802 * @dev_class_mask: the class mask for this device
803 *
804 * This macro is used to create a struct pci_device_id that matches a
805 * specific PCI class. The vendor, device, subvendor, and subdevice
806 * fields will be set to PCI_ANY_ID.
807 */
808#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
809 .class = (dev_class), .class_mask = (dev_class_mask), \
810 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
811 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
812
813/**
814 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
815 * @vend: the vendor name
816 * @dev: the 16 bit PCI Device ID
817 *
818 * This macro is used to create a struct pci_device_id that matches a
819 * specific PCI device. The subvendor, and subdevice fields will be set
820 * to PCI_ANY_ID. The macro allows the next field to follow as the device
821 * private data.
822 */
823#define PCI_VDEVICE(vend, dev) \
824 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
825 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
826
827/**
828 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
829 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
830 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
831 * @data: the driver data to be filled
832 *
833 * This macro is used to create a struct pci_device_id that matches a
834 * specific PCI device. The subvendor, and subdevice fields will be set
835 * to PCI_ANY_ID.
836 */
837#define PCI_DEVICE_DATA(vend, dev, data) \
838 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
839 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
840 .driver_data = (kernel_ulong_t)(data)
841
842enum {
843 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
844 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
845 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
846 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
847 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
848 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
849 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
850};
851
852/* These external functions are only available when PCI support is enabled */
853#ifdef CONFIG_PCI
854
855extern unsigned int pci_flags;
856
857static inline void pci_set_flags(int flags) { pci_flags = flags; }
858static inline void pci_add_flags(int flags) { pci_flags |= flags; }
859static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
860static inline int pci_has_flag(int flag) { return pci_flags & flag; }
861
862void pcie_bus_configure_settings(struct pci_bus *bus);
863
864enum pcie_bus_config_types {
865 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
866 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
867 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
868 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
869 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
870};
871
872extern enum pcie_bus_config_types pcie_bus_config;
873
874extern struct bus_type pci_bus_type;
875
876/* Do NOT directly access these two variables, unless you are arch-specific PCI
877 * code, or PCI core code. */
878extern struct list_head pci_root_buses; /* List of all known PCI buses */
879/* Some device drivers need know if PCI is initiated */
880int no_pci_devices(void);
881
882void pcibios_resource_survey_bus(struct pci_bus *bus);
883void pcibios_bus_add_device(struct pci_dev *pdev);
884void pcibios_add_bus(struct pci_bus *bus);
885void pcibios_remove_bus(struct pci_bus *bus);
886void pcibios_fixup_bus(struct pci_bus *);
887int __must_check pcibios_enable_device(struct pci_dev *, int mask);
888/* Architecture-specific versions may override this (weak) */
889char *pcibios_setup(char *str);
890
891/* Used only when drivers/pci/setup.c is used */
892resource_size_t pcibios_align_resource(void *, const struct resource *,
893 resource_size_t,
894 resource_size_t);
895
896/* Weak but can be overriden by arch */
897void pci_fixup_cardbus(struct pci_bus *);
898
899/* Generic PCI functions used internally */
900
901void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
902 struct resource *res);
903void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
904 struct pci_bus_region *region);
905void pcibios_scan_specific_bus(int busn);
906struct pci_bus *pci_find_bus(int domain, int busnr);
907void pci_bus_add_devices(const struct pci_bus *bus);
908struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
909struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
910 struct pci_ops *ops, void *sysdata,
911 struct list_head *resources);
912int pci_host_probe(struct pci_host_bridge *bridge);
913int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
914int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
915void pci_bus_release_busn_res(struct pci_bus *b);
916struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
917 struct pci_ops *ops, void *sysdata,
918 struct list_head *resources);
919int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
920struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
921 int busnr);
922void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
923struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
924 const char *name,
925 struct hotplug_slot *hotplug);
926void pci_destroy_slot(struct pci_slot *slot);
927#ifdef CONFIG_SYSFS
928void pci_dev_assign_slot(struct pci_dev *dev);
929#else
930static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
931#endif
932int pci_scan_slot(struct pci_bus *bus, int devfn);
933struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
934void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
935unsigned int pci_scan_child_bus(struct pci_bus *bus);
936void pci_bus_add_device(struct pci_dev *dev);
937void pci_read_bridge_bases(struct pci_bus *child);
938struct resource *pci_find_parent_resource(const struct pci_dev *dev,
939 struct resource *res);
940struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
941u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
942int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
943u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
944struct pci_dev *pci_dev_get(struct pci_dev *dev);
945void pci_dev_put(struct pci_dev *dev);
946void pci_remove_bus(struct pci_bus *b);
947void pci_stop_and_remove_bus_device(struct pci_dev *dev);
948void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
949void pci_stop_root_bus(struct pci_bus *bus);
950void pci_remove_root_bus(struct pci_bus *bus);
951void pci_setup_cardbus(struct pci_bus *bus);
952void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
953void pci_sort_breadthfirst(void);
954#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
955#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
956
957/* Generic PCI functions exported to card drivers */
958
959enum pci_lost_interrupt_reason {
960 PCI_LOST_IRQ_NO_INFORMATION = 0,
961 PCI_LOST_IRQ_DISABLE_MSI,
962 PCI_LOST_IRQ_DISABLE_MSIX,
963 PCI_LOST_IRQ_DISABLE_ACPI,
964};
965enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
966int pci_find_capability(struct pci_dev *dev, int cap);
967int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
968int pci_find_ext_capability(struct pci_dev *dev, int cap);
969int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
970int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
971int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
972struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
973
974struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
975 struct pci_dev *from);
976struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
977 unsigned int ss_vendor, unsigned int ss_device,
978 struct pci_dev *from);
979struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
980struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
981 unsigned int devfn);
982struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
983int pci_dev_present(const struct pci_device_id *ids);
984
985int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
986 int where, u8 *val);
987int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
988 int where, u16 *val);
989int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
990 int where, u32 *val);
991int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
992 int where, u8 val);
993int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
994 int where, u16 val);
995int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
996 int where, u32 val);
997
998int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
999 int where, int size, u32 *val);
1000int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1001 int where, int size, u32 val);
1002int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1003 int where, int size, u32 *val);
1004int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1005 int where, int size, u32 val);
1006
1007struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1008
1009int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1010int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1011int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1012int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1013int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1014int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1015
1016int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1017int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1018int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1019int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1020int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1021 u16 clear, u16 set);
1022int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1023 u32 clear, u32 set);
1024
1025static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1026 u16 set)
1027{
1028 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1029}
1030
1031static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1032 u32 set)
1033{
1034 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1035}
1036
1037static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1038 u16 clear)
1039{
1040 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1041}
1042
1043static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1044 u32 clear)
1045{
1046 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1047}
1048
1049/* User-space driven config access */
1050int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1051int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1052int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1053int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1054int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1055int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1056
1057int __must_check pci_enable_device(struct pci_dev *dev);
1058int __must_check pci_enable_device_io(struct pci_dev *dev);
1059int __must_check pci_enable_device_mem(struct pci_dev *dev);
1060int __must_check pci_reenable_device(struct pci_dev *);
1061int __must_check pcim_enable_device(struct pci_dev *pdev);
1062void pcim_pin_device(struct pci_dev *pdev);
1063
1064static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1065{
1066 /*
1067 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1068 * writable and no quirk has marked the feature broken.
1069 */
1070 return !pdev->broken_intx_masking;
1071}
1072
1073static inline int pci_is_enabled(struct pci_dev *pdev)
1074{
1075 return (atomic_read(&pdev->enable_cnt) > 0);
1076}
1077
1078static inline int pci_is_managed(struct pci_dev *pdev)
1079{
1080 return pdev->is_managed;
1081}
1082
1083void pci_disable_device(struct pci_dev *dev);
1084
1085extern unsigned int pcibios_max_latency;
1086void pci_set_master(struct pci_dev *dev);
1087void pci_clear_master(struct pci_dev *dev);
1088
1089int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1090int pci_set_cacheline_size(struct pci_dev *dev);
1091#define HAVE_PCI_SET_MWI
1092int __must_check pci_set_mwi(struct pci_dev *dev);
1093int __must_check pcim_set_mwi(struct pci_dev *dev);
1094int pci_try_set_mwi(struct pci_dev *dev);
1095void pci_clear_mwi(struct pci_dev *dev);
1096void pci_intx(struct pci_dev *dev, int enable);
1097bool pci_check_and_mask_intx(struct pci_dev *dev);
1098bool pci_check_and_unmask_intx(struct pci_dev *dev);
1099int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1100int pci_wait_for_pending_transaction(struct pci_dev *dev);
1101int pcix_get_max_mmrbc(struct pci_dev *dev);
1102int pcix_get_mmrbc(struct pci_dev *dev);
1103int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1104int pcie_get_readrq(struct pci_dev *dev);
1105int pcie_set_readrq(struct pci_dev *dev, int rq);
1106int pcie_get_mps(struct pci_dev *dev);
1107int pcie_set_mps(struct pci_dev *dev, int mps);
1108u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1109 enum pci_bus_speed *speed,
1110 enum pcie_link_width *width);
1111void pcie_print_link_status(struct pci_dev *dev);
1112bool pcie_has_flr(struct pci_dev *dev);
1113int pcie_flr(struct pci_dev *dev);
1114int __pci_reset_function_locked(struct pci_dev *dev);
1115int pci_reset_function(struct pci_dev *dev);
1116int pci_reset_function_locked(struct pci_dev *dev);
1117int pci_try_reset_function(struct pci_dev *dev);
1118int pci_probe_reset_slot(struct pci_slot *slot);
1119int pci_probe_reset_bus(struct pci_bus *bus);
1120int pci_reset_bus(struct pci_dev *dev);
1121void pci_reset_secondary_bus(struct pci_dev *dev);
1122void pcibios_reset_secondary_bus(struct pci_dev *dev);
1123void pci_update_resource(struct pci_dev *dev, int resno);
1124int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1125int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1126void pci_release_resource(struct pci_dev *dev, int resno);
1127int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1128int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1129bool pci_device_is_present(struct pci_dev *pdev);
1130void pci_ignore_hotplug(struct pci_dev *dev);
1131
1132int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1133 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1134 const char *fmt, ...);
1135void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1136
1137/* ROM control related routines */
1138int pci_enable_rom(struct pci_dev *pdev);
1139void pci_disable_rom(struct pci_dev *pdev);
1140void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1141void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1142void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1143
1144/* Power management related routines */
1145int pci_save_state(struct pci_dev *dev);
1146void pci_restore_state(struct pci_dev *dev);
1147struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1148int pci_load_saved_state(struct pci_dev *dev,
1149 struct pci_saved_state *state);
1150int pci_load_and_free_saved_state(struct pci_dev *dev,
1151 struct pci_saved_state **state);
1152struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1153struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1154 u16 cap);
1155int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1156int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1157 u16 cap, unsigned int size);
1158int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1159int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1160pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1161bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1162void pci_pme_active(struct pci_dev *dev, bool enable);
1163int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1164int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1165int pci_prepare_to_sleep(struct pci_dev *dev);
1166int pci_back_from_sleep(struct pci_dev *dev);
1167bool pci_dev_run_wake(struct pci_dev *dev);
1168bool pci_check_pme_status(struct pci_dev *dev);
1169void pci_pme_wakeup_bus(struct pci_bus *bus);
1170void pci_d3cold_enable(struct pci_dev *dev);
1171void pci_d3cold_disable(struct pci_dev *dev);
1172bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1173void pci_wakeup_bus(struct pci_bus *bus);
1174void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1175
1176/* PCI Virtual Channel */
1177int pci_save_vc_state(struct pci_dev *dev);
1178void pci_restore_vc_state(struct pci_dev *dev);
1179void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1180
1181/* For use by arch with custom probe code */
1182void set_pcie_port_type(struct pci_dev *pdev);
1183void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1184
1185/* Functions for PCI Hotplug drivers to use */
1186int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1187unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1188unsigned int pci_rescan_bus(struct pci_bus *bus);
1189void pci_lock_rescan_remove(void);
1190void pci_unlock_rescan_remove(void);
1191
1192/* Vital Product Data routines */
1193ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1194ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1195int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1196
1197/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1198resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1199void pci_bus_assign_resources(const struct pci_bus *bus);
1200void pci_bus_claim_resources(struct pci_bus *bus);
1201void pci_bus_size_bridges(struct pci_bus *bus);
1202int pci_claim_resource(struct pci_dev *, int);
1203int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1204void pci_assign_unassigned_resources(void);
1205void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1206void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1207void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1208int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1209void pdev_enable_device(struct pci_dev *);
1210int pci_enable_resources(struct pci_dev *, int mask);
1211void pci_assign_irq(struct pci_dev *dev);
1212struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1213#define HAVE_PCI_REQ_REGIONS 2
1214int __must_check pci_request_regions(struct pci_dev *, const char *);
1215int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1216void pci_release_regions(struct pci_dev *);
1217int __must_check pci_request_region(struct pci_dev *, int, const char *);
1218int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1219void pci_release_region(struct pci_dev *, int);
1220int pci_request_selected_regions(struct pci_dev *, int, const char *);
1221int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1222void pci_release_selected_regions(struct pci_dev *, int);
1223
1224/* drivers/pci/bus.c */
1225struct pci_bus *pci_bus_get(struct pci_bus *bus);
1226void pci_bus_put(struct pci_bus *bus);
1227void pci_add_resource(struct list_head *resources, struct resource *res);
1228void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1229 resource_size_t offset);
1230void pci_free_resource_list(struct list_head *resources);
1231void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1232 unsigned int flags);
1233struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1234void pci_bus_remove_resources(struct pci_bus *bus);
1235int devm_request_pci_bus_resources(struct device *dev,
1236 struct list_head *resources);
1237
1238#define pci_bus_for_each_resource(bus, res, i) \
1239 for (i = 0; \
1240 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1241 i++)
1242
1243int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1244 struct resource *res, resource_size_t size,
1245 resource_size_t align, resource_size_t min,
1246 unsigned long type_mask,
1247 resource_size_t (*alignf)(void *,
1248 const struct resource *,
1249 resource_size_t,
1250 resource_size_t),
1251 void *alignf_data);
1252
1253
1254int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1255 resource_size_t size);
1256unsigned long pci_address_to_pio(phys_addr_t addr);
1257phys_addr_t pci_pio_to_address(unsigned long pio);
1258int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1259int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1260 phys_addr_t phys_addr);
1261void pci_unmap_iospace(struct resource *res);
1262void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1263 resource_size_t offset,
1264 resource_size_t size);
1265void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1266 struct resource *res);
1267
1268static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1269{
1270 struct pci_bus_region region;
1271
1272 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1273 return region.start;
1274}
1275
1276/* Proper probing supporting hot-pluggable devices */
1277int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1278 const char *mod_name);
1279
1280/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1281#define pci_register_driver(driver) \
1282 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1283
1284void pci_unregister_driver(struct pci_driver *dev);
1285
1286/**
1287 * module_pci_driver() - Helper macro for registering a PCI driver
1288 * @__pci_driver: pci_driver struct
1289 *
1290 * Helper macro for PCI drivers which do not do anything special in module
1291 * init/exit. This eliminates a lot of boilerplate. Each module may only
1292 * use this macro once, and calling it replaces module_init() and module_exit()
1293 */
1294#define module_pci_driver(__pci_driver) \
1295 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1296
1297/**
1298 * builtin_pci_driver() - Helper macro for registering a PCI driver
1299 * @__pci_driver: pci_driver struct
1300 *
1301 * Helper macro for PCI drivers which do not do anything special in their
1302 * init code. This eliminates a lot of boilerplate. Each driver may only
1303 * use this macro once, and calling it replaces device_initcall(...)
1304 */
1305#define builtin_pci_driver(__pci_driver) \
1306 builtin_driver(__pci_driver, pci_register_driver)
1307
1308struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1309int pci_add_dynid(struct pci_driver *drv,
1310 unsigned int vendor, unsigned int device,
1311 unsigned int subvendor, unsigned int subdevice,
1312 unsigned int class, unsigned int class_mask,
1313 unsigned long driver_data);
1314const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1315 struct pci_dev *dev);
1316int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1317 int pass);
1318
1319void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1320 void *userdata);
1321int pci_cfg_space_size(struct pci_dev *dev);
1322unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1323void pci_setup_bridge(struct pci_bus *bus);
1324resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1325 unsigned long type);
1326
1327#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1328#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1329
1330int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1331 unsigned int command_bits, u32 flags);
1332
1333#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1334#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1335#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1336#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1337#define PCI_IRQ_ALL_TYPES \
1338 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1339
1340/* kmem_cache style wrapper around pci_alloc_consistent() */
1341
1342#include <linux/pci-dma.h>
1343#include <linux/dmapool.h>
1344
1345#define pci_pool dma_pool
1346#define pci_pool_create(name, pdev, size, align, allocation) \
1347 dma_pool_create(name, &pdev->dev, size, align, allocation)
1348#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1349#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1350#define pci_pool_zalloc(pool, flags, handle) \
1351 dma_pool_zalloc(pool, flags, handle)
1352#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1353
1354struct msix_entry {
1355 u32 vector; /* Kernel uses to write allocated vector */
1356 u16 entry; /* Driver uses to specify entry, OS writes */
1357};
1358
1359#ifdef CONFIG_PCI_MSI
1360int pci_msi_vec_count(struct pci_dev *dev);
1361void pci_disable_msi(struct pci_dev *dev);
1362int pci_msix_vec_count(struct pci_dev *dev);
1363void pci_disable_msix(struct pci_dev *dev);
1364void pci_restore_msi_state(struct pci_dev *dev);
1365int pci_msi_enabled(void);
1366int pci_enable_msi(struct pci_dev *dev);
1367int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1368 int minvec, int maxvec);
1369static inline int pci_enable_msix_exact(struct pci_dev *dev,
1370 struct msix_entry *entries, int nvec)
1371{
1372 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1373 if (rc < 0)
1374 return rc;
1375 return 0;
1376}
1377int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1378 unsigned int max_vecs, unsigned int flags,
1379 const struct irq_affinity *affd);
1380
1381void pci_free_irq_vectors(struct pci_dev *dev);
1382int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1383const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1384int pci_irq_get_node(struct pci_dev *pdev, int vec);
1385
1386#else
1387static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1388static inline void pci_disable_msi(struct pci_dev *dev) { }
1389static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1390static inline void pci_disable_msix(struct pci_dev *dev) { }
1391static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1392static inline int pci_msi_enabled(void) { return 0; }
1393static inline int pci_enable_msi(struct pci_dev *dev)
1394{ return -ENOSYS; }
1395static inline int pci_enable_msix_range(struct pci_dev *dev,
1396 struct msix_entry *entries, int minvec, int maxvec)
1397{ return -ENOSYS; }
1398static inline int pci_enable_msix_exact(struct pci_dev *dev,
1399 struct msix_entry *entries, int nvec)
1400{ return -ENOSYS; }
1401
1402static inline int
1403pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1404 unsigned int max_vecs, unsigned int flags,
1405 const struct irq_affinity *aff_desc)
1406{
1407 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1408 return 1;
1409 return -ENOSPC;
1410}
1411
1412static inline void pci_free_irq_vectors(struct pci_dev *dev)
1413{
1414}
1415
1416static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1417{
1418 if (WARN_ON_ONCE(nr > 0))
1419 return -EINVAL;
1420 return dev->irq;
1421}
1422static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1423 int vec)
1424{
1425 return cpu_possible_mask;
1426}
1427
1428static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1429{
1430 return first_online_node;
1431}
1432#endif
1433
1434static inline int
1435pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1436 unsigned int max_vecs, unsigned int flags)
1437{
1438 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1439 NULL);
1440}
1441
1442/**
1443 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1444 * @d: the INTx IRQ domain
1445 * @node: the DT node for the device whose interrupt we're translating
1446 * @intspec: the interrupt specifier data from the DT
1447 * @intsize: the number of entries in @intspec
1448 * @out_hwirq: pointer at which to write the hwirq number
1449 * @out_type: pointer at which to write the interrupt type
1450 *
1451 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1452 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1453 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1454 * INTx value to obtain the hwirq number.
1455 *
1456 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1457 */
1458static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1459 struct device_node *node,
1460 const u32 *intspec,
1461 unsigned int intsize,
1462 unsigned long *out_hwirq,
1463 unsigned int *out_type)
1464{
1465 const u32 intx = intspec[0];
1466
1467 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1468 return -EINVAL;
1469
1470 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1471 return 0;
1472}
1473
1474#ifdef CONFIG_PCIEPORTBUS
1475extern bool pcie_ports_disabled;
1476extern bool pcie_ports_native;
1477#else
1478#define pcie_ports_disabled true
1479#define pcie_ports_native false
1480#endif
1481
1482#ifdef CONFIG_PCIEASPM
1483bool pcie_aspm_support_enabled(void);
1484#else
1485static inline bool pcie_aspm_support_enabled(void) { return false; }
1486#endif
1487
1488#ifdef CONFIG_PCIEAER
1489bool pci_aer_available(void);
1490#else
1491static inline bool pci_aer_available(void) { return false; }
1492#endif
1493
1494#ifdef CONFIG_PCIE_ECRC
1495void pcie_set_ecrc_checking(struct pci_dev *dev);
1496void pcie_ecrc_get_policy(char *str);
1497#else
1498static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1499static inline void pcie_ecrc_get_policy(char *str) { }
1500#endif
1501
1502bool pci_ats_disabled(void);
1503
1504#ifdef CONFIG_PCI_ATS
1505/* Address Translation Service */
1506void pci_ats_init(struct pci_dev *dev);
1507int pci_enable_ats(struct pci_dev *dev, int ps);
1508void pci_disable_ats(struct pci_dev *dev);
1509int pci_ats_queue_depth(struct pci_dev *dev);
1510#else
1511static inline void pci_ats_init(struct pci_dev *d) { }
1512static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1513static inline void pci_disable_ats(struct pci_dev *d) { }
1514static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1515#endif
1516
1517#ifdef CONFIG_PCIE_PTM
1518int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1519#else
1520static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1521{ return -EINVAL; }
1522#endif
1523
1524void pci_cfg_access_lock(struct pci_dev *dev);
1525bool pci_cfg_access_trylock(struct pci_dev *dev);
1526void pci_cfg_access_unlock(struct pci_dev *dev);
1527
1528/*
1529 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1530 * a PCI domain is defined to be a set of PCI buses which share
1531 * configuration space.
1532 */
1533#ifdef CONFIG_PCI_DOMAINS
1534extern int pci_domains_supported;
1535#else
1536enum { pci_domains_supported = 0 };
1537static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1538static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1539#endif /* CONFIG_PCI_DOMAINS */
1540
1541/*
1542 * Generic implementation for PCI domain support. If your
1543 * architecture does not need custom management of PCI
1544 * domains then this implementation will be used
1545 */
1546#ifdef CONFIG_PCI_DOMAINS_GENERIC
1547static inline int pci_domain_nr(struct pci_bus *bus)
1548{
1549 return bus->domain_nr;
1550}
1551#ifdef CONFIG_ACPI
1552int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1553#else
1554static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1555{ return 0; }
1556#endif
1557int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1558#endif
1559
1560/* Some architectures require additional setup to direct VGA traffic */
1561typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1562 unsigned int command_bits, u32 flags);
1563void pci_register_set_vga_state(arch_set_vga_state_t func);
1564
1565static inline int
1566pci_request_io_regions(struct pci_dev *pdev, const char *name)
1567{
1568 return pci_request_selected_regions(pdev,
1569 pci_select_bars(pdev, IORESOURCE_IO), name);
1570}
1571
1572static inline void
1573pci_release_io_regions(struct pci_dev *pdev)
1574{
1575 return pci_release_selected_regions(pdev,
1576 pci_select_bars(pdev, IORESOURCE_IO));
1577}
1578
1579static inline int
1580pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1581{
1582 return pci_request_selected_regions(pdev,
1583 pci_select_bars(pdev, IORESOURCE_MEM), name);
1584}
1585
1586static inline void
1587pci_release_mem_regions(struct pci_dev *pdev)
1588{
1589 return pci_release_selected_regions(pdev,
1590 pci_select_bars(pdev, IORESOURCE_MEM));
1591}
1592
1593#else /* CONFIG_PCI is not enabled */
1594
1595static inline void pci_set_flags(int flags) { }
1596static inline void pci_add_flags(int flags) { }
1597static inline void pci_clear_flags(int flags) { }
1598static inline int pci_has_flag(int flag) { return 0; }
1599
1600/*
1601 * If the system does not have PCI, clearly these return errors. Define
1602 * these as simple inline functions to avoid hair in drivers.
1603 */
1604#define _PCI_NOP(o, s, t) \
1605 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1606 int where, t val) \
1607 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1608
1609#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1610 _PCI_NOP(o, word, u16 x) \
1611 _PCI_NOP(o, dword, u32 x)
1612_PCI_NOP_ALL(read, *)
1613_PCI_NOP_ALL(write,)
1614
1615static inline struct pci_dev *pci_get_device(unsigned int vendor,
1616 unsigned int device,
1617 struct pci_dev *from)
1618{ return NULL; }
1619
1620static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1621 unsigned int device,
1622 unsigned int ss_vendor,
1623 unsigned int ss_device,
1624 struct pci_dev *from)
1625{ return NULL; }
1626
1627static inline struct pci_dev *pci_get_class(unsigned int class,
1628 struct pci_dev *from)
1629{ return NULL; }
1630
1631#define pci_dev_present(ids) (0)
1632#define no_pci_devices() (1)
1633#define pci_dev_put(dev) do { } while (0)
1634
1635static inline void pci_set_master(struct pci_dev *dev) { }
1636static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1637static inline void pci_disable_device(struct pci_dev *dev) { }
1638static inline int pci_assign_resource(struct pci_dev *dev, int i)
1639{ return -EBUSY; }
1640static inline int __pci_register_driver(struct pci_driver *drv,
1641 struct module *owner)
1642{ return 0; }
1643static inline int pci_register_driver(struct pci_driver *drv)
1644{ return 0; }
1645static inline void pci_unregister_driver(struct pci_driver *drv) { }
1646static inline int pci_find_capability(struct pci_dev *dev, int cap)
1647{ return 0; }
1648static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1649 int cap)
1650{ return 0; }
1651static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1652{ return 0; }
1653
1654/* Power management related routines */
1655static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1656static inline void pci_restore_state(struct pci_dev *dev) { }
1657static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1658{ return 0; }
1659static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1660{ return 0; }
1661static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1662 pm_message_t state)
1663{ return PCI_D0; }
1664static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1665 int enable)
1666{ return 0; }
1667
1668static inline struct resource *pci_find_resource(struct pci_dev *dev,
1669 struct resource *res)
1670{ return NULL; }
1671static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1672{ return -EIO; }
1673static inline void pci_release_regions(struct pci_dev *dev) { }
1674
1675static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1676
1677static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1678static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1679{ return 0; }
1680static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1681
1682static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1683{ return NULL; }
1684static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1685 unsigned int devfn)
1686{ return NULL; }
1687static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1688 unsigned int bus, unsigned int devfn)
1689{ return NULL; }
1690
1691static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1692static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1693
1694#define dev_is_pci(d) (false)
1695#define dev_is_pf(d) (false)
1696static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1697{ return false; }
1698static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1699 struct device_node *node,
1700 const u32 *intspec,
1701 unsigned int intsize,
1702 unsigned long *out_hwirq,
1703 unsigned int *out_type)
1704{ return -EINVAL; }
1705#endif /* CONFIG_PCI */
1706
1707/* Include architecture-dependent settings and functions */
1708
1709#include <asm/pci.h>
1710
1711/* These two functions provide almost identical functionality. Depennding
1712 * on the architecture, one will be implemented as a wrapper around the
1713 * other (in drivers/pci/mmap.c).
1714 *
1715 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1716 * is expected to be an offset within that region.
1717 *
1718 * pci_mmap_page_range() is the legacy architecture-specific interface,
1719 * which accepts a "user visible" resource address converted by
1720 * pci_resource_to_user(), as used in the legacy mmap() interface in
1721 * /proc/bus/pci/.
1722 */
1723int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1724 struct vm_area_struct *vma,
1725 enum pci_mmap_state mmap_state, int write_combine);
1726int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1727 struct vm_area_struct *vma,
1728 enum pci_mmap_state mmap_state, int write_combine);
1729
1730#ifndef arch_can_pci_mmap_wc
1731#define arch_can_pci_mmap_wc() 0
1732#endif
1733
1734#ifndef arch_can_pci_mmap_io
1735#define arch_can_pci_mmap_io() 0
1736#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1737#else
1738int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1739#endif
1740
1741#ifndef pci_root_bus_fwnode
1742#define pci_root_bus_fwnode(bus) NULL
1743#endif
1744
1745/*
1746 * These helpers provide future and backwards compatibility
1747 * for accessing popular PCI BAR info
1748 */
1749#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1750#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1751#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1752#define pci_resource_len(dev,bar) \
1753 ((pci_resource_start((dev), (bar)) == 0 && \
1754 pci_resource_end((dev), (bar)) == \
1755 pci_resource_start((dev), (bar))) ? 0 : \
1756 \
1757 (pci_resource_end((dev), (bar)) - \
1758 pci_resource_start((dev), (bar)) + 1))
1759
1760/*
1761 * Similar to the helpers above, these manipulate per-pci_dev
1762 * driver-specific data. They are really just a wrapper around
1763 * the generic device structure functions of these calls.
1764 */
1765static inline void *pci_get_drvdata(struct pci_dev *pdev)
1766{
1767 return dev_get_drvdata(&pdev->dev);
1768}
1769
1770static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1771{
1772 dev_set_drvdata(&pdev->dev, data);
1773}
1774
1775static inline const char *pci_name(const struct pci_dev *pdev)
1776{
1777 return dev_name(&pdev->dev);
1778}
1779
1780
1781/*
1782 * Some archs don't want to expose struct resource to userland as-is
1783 * in sysfs and /proc
1784 */
1785#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1786void pci_resource_to_user(const struct pci_dev *dev, int bar,
1787 const struct resource *rsrc,
1788 resource_size_t *start, resource_size_t *end);
1789#else
1790static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1791 const struct resource *rsrc, resource_size_t *start,
1792 resource_size_t *end)
1793{
1794 *start = rsrc->start;
1795 *end = rsrc->end;
1796}
1797#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1798
1799
1800/*
1801 * The world is not perfect and supplies us with broken PCI devices.
1802 * For at least a part of these bugs we need a work-around, so both
1803 * generic (drivers/pci/quirks.c) and per-architecture code can define
1804 * fixup hooks to be called for particular buggy devices.
1805 */
1806
1807struct pci_fixup {
1808 u16 vendor; /* Or PCI_ANY_ID */
1809 u16 device; /* Or PCI_ANY_ID */
1810 u32 class; /* Or PCI_ANY_ID */
1811 unsigned int class_shift; /* should be 0, 8, 16 */
1812 void (*hook)(struct pci_dev *dev);
1813};
1814
1815enum pci_fixup_pass {
1816 pci_fixup_early, /* Before probing BARs */
1817 pci_fixup_header, /* After reading configuration header */
1818 pci_fixup_final, /* Final phase of device fixups */
1819 pci_fixup_enable, /* pci_enable_device() time */
1820 pci_fixup_resume, /* pci_device_resume() */
1821 pci_fixup_suspend, /* pci_device_suspend() */
1822 pci_fixup_resume_early, /* pci_device_resume_early() */
1823 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1824};
1825
1826/* Anonymous variables would be nice... */
1827#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1828 class_shift, hook) \
1829 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1830 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1831 = { vendor, device, class, class_shift, hook };
1832
1833#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1834 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1836 hook, vendor, device, class, class_shift, hook)
1837#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1838 class_shift, hook) \
1839 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1840 hook, vendor, device, class, class_shift, hook)
1841#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1842 class_shift, hook) \
1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1844 hook, vendor, device, class, class_shift, hook)
1845#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1846 class_shift, hook) \
1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1848 hook, vendor, device, class, class_shift, hook)
1849#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1850 class_shift, hook) \
1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1852 resume##hook, vendor, device, class, class_shift, hook)
1853#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1854 class_shift, hook) \
1855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1856 resume_early##hook, vendor, device, class, class_shift, hook)
1857#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1858 class_shift, hook) \
1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1860 suspend##hook, vendor, device, class, class_shift, hook)
1861#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1862 class_shift, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1864 suspend_late##hook, vendor, device, class, class_shift, hook)
1865
1866#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1868 hook, vendor, device, PCI_ANY_ID, 0, hook)
1869#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1870 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1871 hook, vendor, device, PCI_ANY_ID, 0, hook)
1872#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1873 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1874 hook, vendor, device, PCI_ANY_ID, 0, hook)
1875#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1877 hook, vendor, device, PCI_ANY_ID, 0, hook)
1878#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1880 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1881#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1882 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1883 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1884#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1885 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1886 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1887#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1888 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1889 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1890
1891#ifdef CONFIG_PCI_QUIRKS
1892void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1893#else
1894static inline void pci_fixup_device(enum pci_fixup_pass pass,
1895 struct pci_dev *dev) { }
1896#endif
1897
1898void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1899void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1900void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1901int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1902int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1903 const char *name);
1904void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1905
1906extern int pci_pci_problems;
1907#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1908#define PCIPCI_TRITON 2
1909#define PCIPCI_NATOMA 4
1910#define PCIPCI_VIAETBF 8
1911#define PCIPCI_VSFX 16
1912#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1913#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1914
1915extern unsigned long pci_cardbus_io_size;
1916extern unsigned long pci_cardbus_mem_size;
1917extern u8 pci_dfl_cache_line_size;
1918extern u8 pci_cache_line_size;
1919
1920extern unsigned long pci_hotplug_io_size;
1921extern unsigned long pci_hotplug_mem_size;
1922extern unsigned long pci_hotplug_bus_size;
1923
1924/* Architecture-specific versions may override these (weak) */
1925void pcibios_disable_device(struct pci_dev *dev);
1926void pcibios_set_master(struct pci_dev *dev);
1927int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1928 enum pcie_reset_state state);
1929int pcibios_add_device(struct pci_dev *dev);
1930void pcibios_release_device(struct pci_dev *dev);
1931void pcibios_penalize_isa_irq(int irq, int active);
1932int pcibios_alloc_irq(struct pci_dev *dev);
1933void pcibios_free_irq(struct pci_dev *dev);
1934resource_size_t pcibios_default_alignment(void);
1935
1936#ifdef CONFIG_HIBERNATE_CALLBACKS
1937extern struct dev_pm_ops pcibios_pm_ops;
1938#endif
1939
1940#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1941void __init pci_mmcfg_early_init(void);
1942void __init pci_mmcfg_late_init(void);
1943#else
1944static inline void pci_mmcfg_early_init(void) { }
1945static inline void pci_mmcfg_late_init(void) { }
1946#endif
1947
1948int pci_ext_cfg_avail(void);
1949
1950void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1951void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1952
1953#ifdef CONFIG_PCI_IOV
1954int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1955int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1956
1957int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1958void pci_disable_sriov(struct pci_dev *dev);
1959int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1960void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1961int pci_num_vf(struct pci_dev *dev);
1962int pci_vfs_assigned(struct pci_dev *dev);
1963int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1964int pci_sriov_get_totalvfs(struct pci_dev *dev);
1965int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1966resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1967void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1968
1969/* Arch may override these (weak) */
1970int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1971int pcibios_sriov_disable(struct pci_dev *pdev);
1972resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1973#else
1974static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1975{
1976 return -ENOSYS;
1977}
1978static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1979{
1980 return -ENOSYS;
1981}
1982static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1983{ return -ENODEV; }
1984static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
1985{
1986 return -ENOSYS;
1987}
1988static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1989 int id) { }
1990static inline void pci_disable_sriov(struct pci_dev *dev) { }
1991static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1992static inline int pci_vfs_assigned(struct pci_dev *dev)
1993{ return 0; }
1994static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1995{ return 0; }
1996static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1997{ return 0; }
1998#define pci_sriov_configure_simple NULL
1999static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2000{ return 0; }
2001static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2002#endif
2003
2004#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2005void pci_hp_create_module_link(struct pci_slot *pci_slot);
2006void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2007#endif
2008
2009/**
2010 * pci_pcie_cap - get the saved PCIe capability offset
2011 * @dev: PCI device
2012 *
2013 * PCIe capability offset is calculated at PCI device initialization
2014 * time and saved in the data structure. This function returns saved
2015 * PCIe capability offset. Using this instead of pci_find_capability()
2016 * reduces unnecessary search in the PCI configuration space. If you
2017 * need to calculate PCIe capability offset from raw device for some
2018 * reasons, please use pci_find_capability() instead.
2019 */
2020static inline int pci_pcie_cap(struct pci_dev *dev)
2021{
2022 return dev->pcie_cap;
2023}
2024
2025/**
2026 * pci_is_pcie - check if the PCI device is PCI Express capable
2027 * @dev: PCI device
2028 *
2029 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2030 */
2031static inline bool pci_is_pcie(struct pci_dev *dev)
2032{
2033 return pci_pcie_cap(dev);
2034}
2035
2036/**
2037 * pcie_caps_reg - get the PCIe Capabilities Register
2038 * @dev: PCI device
2039 */
2040static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2041{
2042 return dev->pcie_flags_reg;
2043}
2044
2045/**
2046 * pci_pcie_type - get the PCIe device/port type
2047 * @dev: PCI device
2048 */
2049static inline int pci_pcie_type(const struct pci_dev *dev)
2050{
2051 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2052}
2053
2054static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2055{
2056 while (1) {
2057 if (!pci_is_pcie(dev))
2058 break;
2059 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2060 return dev;
2061 if (!dev->bus->self)
2062 break;
2063 dev = dev->bus->self;
2064 }
2065 return NULL;
2066}
2067
2068void pci_request_acs(void);
2069bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2070bool pci_acs_path_enabled(struct pci_dev *start,
2071 struct pci_dev *end, u16 acs_flags);
2072int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2073
2074#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2075#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2076
2077/* Large Resource Data Type Tag Item Names */
2078#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2079#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2080#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2081
2082#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2083#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2084#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2085
2086/* Small Resource Data Type Tag Item Names */
2087#define PCI_VPD_STIN_END 0x0f /* End */
2088
2089#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2090
2091#define PCI_VPD_SRDT_TIN_MASK 0x78
2092#define PCI_VPD_SRDT_LEN_MASK 0x07
2093#define PCI_VPD_LRDT_TIN_MASK 0x7f
2094
2095#define PCI_VPD_LRDT_TAG_SIZE 3
2096#define PCI_VPD_SRDT_TAG_SIZE 1
2097
2098#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2099
2100#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2101#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2102#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2103#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2104
2105/**
2106 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2107 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2108 *
2109 * Returns the extracted Large Resource Data Type length.
2110 */
2111static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2112{
2113 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2114}
2115
2116/**
2117 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2118 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2119 *
2120 * Returns the extracted Large Resource Data Type Tag item.
2121 */
2122static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2123{
2124 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2125}
2126
2127/**
2128 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2129 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2130 *
2131 * Returns the extracted Small Resource Data Type length.
2132 */
2133static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2134{
2135 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2136}
2137
2138/**
2139 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2140 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2141 *
2142 * Returns the extracted Small Resource Data Type Tag Item.
2143 */
2144static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2145{
2146 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2147}
2148
2149/**
2150 * pci_vpd_info_field_size - Extracts the information field length
2151 * @lrdt: Pointer to the beginning of an information field header
2152 *
2153 * Returns the extracted information field length.
2154 */
2155static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2156{
2157 return info_field[2];
2158}
2159
2160/**
2161 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2162 * @buf: Pointer to buffered vpd data
2163 * @off: The offset into the buffer at which to begin the search
2164 * @len: The length of the vpd buffer
2165 * @rdt: The Resource Data Type to search for
2166 *
2167 * Returns the index where the Resource Data Type was found or
2168 * -ENOENT otherwise.
2169 */
2170int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2171
2172/**
2173 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2174 * @buf: Pointer to buffered vpd data
2175 * @off: The offset into the buffer at which to begin the search
2176 * @len: The length of the buffer area, relative to off, in which to search
2177 * @kw: The keyword to search for
2178 *
2179 * Returns the index where the information field keyword was found or
2180 * -ENOENT otherwise.
2181 */
2182int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2183 unsigned int len, const char *kw);
2184
2185/* PCI <-> OF binding helpers */
2186#ifdef CONFIG_OF
2187struct device_node;
2188struct irq_domain;
2189void pci_set_of_node(struct pci_dev *dev);
2190void pci_release_of_node(struct pci_dev *dev);
2191void pci_set_bus_of_node(struct pci_bus *bus);
2192void pci_release_bus_of_node(struct pci_bus *bus);
2193struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2194int pci_parse_request_of_pci_ranges(struct device *dev,
2195 struct list_head *resources,
2196 struct resource **bus_range);
2197
2198/* Arch may override this (weak) */
2199struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2200
2201#else /* CONFIG_OF */
2202static inline void pci_set_of_node(struct pci_dev *dev) { }
2203static inline void pci_release_of_node(struct pci_dev *dev) { }
2204static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2205static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2206static inline struct irq_domain *
2207pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2208static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2209 struct list_head *resources,
2210 struct resource **bus_range)
2211{
2212 return -EINVAL;
2213}
2214#endif /* CONFIG_OF */
2215
2216static inline struct device_node *
2217pci_device_to_OF_node(const struct pci_dev *pdev)
2218{
2219 return pdev ? pdev->dev.of_node : NULL;
2220}
2221
2222static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2223{
2224 return bus ? bus->dev.of_node : NULL;
2225}
2226
2227#ifdef CONFIG_ACPI
2228struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2229
2230void
2231pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2232#else
2233static inline struct irq_domain *
2234pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2235#endif
2236
2237#ifdef CONFIG_EEH
2238static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2239{
2240 return pdev->dev.archdata.edev;
2241}
2242#endif
2243
2244void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2245bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2246int pci_for_each_dma_alias(struct pci_dev *pdev,
2247 int (*fn)(struct pci_dev *pdev,
2248 u16 alias, void *data), void *data);
2249
2250/* Helper functions for operation of device flag */
2251static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2252{
2253 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2254}
2255static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2256{
2257 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2258}
2259static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2260{
2261 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2262}
2263
2264/**
2265 * pci_ari_enabled - query ARI forwarding status
2266 * @bus: the PCI bus
2267 *
2268 * Returns true if ARI forwarding is enabled.
2269 */
2270static inline bool pci_ari_enabled(struct pci_bus *bus)
2271{
2272 return bus->self && bus->self->ari_enabled;
2273}
2274
2275/**
2276 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2277 * @pdev: PCI device to check
2278 *
2279 * Walk upwards from @pdev and check for each encountered bridge if it's part
2280 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2281 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2282 */
2283static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2284{
2285 struct pci_dev *parent = pdev;
2286
2287 if (pdev->is_thunderbolt)
2288 return true;
2289
2290 while ((parent = pci_upstream_bridge(parent)))
2291 if (parent->is_thunderbolt)
2292 return true;
2293
2294 return false;
2295}
2296
2297#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2298void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2299#endif
2300
2301/* Provide the legacy pci_dma_* API */
2302#include <linux/pci-dma-compat.h>
2303
2304#define pci_printk(level, pdev, fmt, arg...) \
2305 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2306
2307#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2308#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2309#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2310#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2311#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2312#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2313#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2314#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2315
2316#endif /* LINUX_PCI_H */
2317