| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2012 ARM Ltd. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __PERF_ARM_PMUV3_H |
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| 7 | #define __PERF_ARM_PMUV3_H |
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| 8 | |
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| 9 | #define ARMV8_PMU_MAX_COUNTERS 32 |
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| 10 | #define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1) |
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| 11 | |
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| 12 | /* |
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| 13 | * Common architectural and microarchitectural event numbers. |
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| 14 | */ |
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| 15 | #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000 |
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| 16 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001 |
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| 17 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002 |
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| 18 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003 |
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| 19 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004 |
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| 20 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005 |
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| 21 | #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006 |
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| 22 | #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007 |
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| 23 | #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008 |
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| 24 | #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009 |
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| 25 | #define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A |
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| 26 | #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B |
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| 27 | #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C |
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| 28 | #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D |
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| 29 | #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E |
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| 30 | #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F |
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| 31 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010 |
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| 32 | #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011 |
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| 33 | #define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012 |
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| 34 | #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013 |
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| 35 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014 |
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| 36 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015 |
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| 37 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016 |
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| 38 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017 |
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| 39 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018 |
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| 40 | #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019 |
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| 41 | #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A |
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| 42 | #define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B |
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| 43 | #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C |
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| 44 | #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D |
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| 45 | #define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E |
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| 46 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F |
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| 47 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020 |
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| 48 | #define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021 |
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| 49 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022 |
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| 50 | #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023 |
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| 51 | #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024 |
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| 52 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025 |
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| 53 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026 |
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| 54 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027 |
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| 55 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028 |
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| 56 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029 |
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| 57 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A |
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| 58 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B |
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| 59 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C |
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| 60 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D |
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| 61 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E |
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| 62 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F |
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| 63 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030 |
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| 64 | #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031 |
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| 65 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032 |
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| 66 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033 |
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| 67 | #define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034 |
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| 68 | #define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035 |
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| 69 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036 |
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| 70 | #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037 |
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| 71 | #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038 |
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| 72 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039 |
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| 73 | #define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A |
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| 74 | #define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B |
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| 75 | #define ARMV8_PMUV3_PERFCTR_STALL 0x003C |
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| 76 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D |
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| 77 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E |
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| 78 | #define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F |
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| 79 | |
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| 80 | /* Statistical profiling extension microarchitectural events */ |
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| 81 | #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000 |
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| 82 | #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001 |
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| 83 | #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002 |
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| 84 | #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003 |
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| 85 | |
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| 86 | /* AMUv1 architecture events */ |
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| 87 | #define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004 |
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| 88 | #define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005 |
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| 89 | |
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| 90 | /* long-latency read miss events */ |
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| 91 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006 |
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| 92 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009 |
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| 93 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A |
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| 94 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B |
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| 95 | |
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| 96 | /* Trace buffer events */ |
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| 97 | #define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C |
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| 98 | #define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E |
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| 99 | |
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| 100 | /* Trace unit events */ |
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| 101 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010 |
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| 102 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011 |
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| 103 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012 |
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| 104 | #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013 |
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| 105 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018 |
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| 106 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019 |
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| 107 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A |
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| 108 | #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B |
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| 109 | |
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| 110 | /* additional latency from alignment events */ |
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| 111 | #define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020 |
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| 112 | #define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021 |
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| 113 | #define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022 |
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| 114 | |
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| 115 | /* Armv8.5 Memory Tagging Extension events */ |
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| 116 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024 |
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| 117 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025 |
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| 118 | #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026 |
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| 119 | |
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| 120 | /* ARMv8 recommended implementation defined event types */ |
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| 121 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040 |
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| 122 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041 |
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| 123 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042 |
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| 124 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043 |
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| 125 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044 |
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| 126 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045 |
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| 127 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046 |
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| 128 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047 |
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| 129 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048 |
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| 130 | |
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| 131 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C |
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| 132 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D |
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| 133 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E |
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| 134 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F |
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| 135 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050 |
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| 136 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051 |
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| 137 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052 |
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| 138 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053 |
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| 139 | |
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| 140 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056 |
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| 141 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057 |
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| 142 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058 |
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| 143 | |
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| 144 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C |
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| 145 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D |
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| 146 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E |
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| 147 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F |
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| 148 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060 |
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| 149 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061 |
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| 150 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062 |
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| 151 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063 |
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| 152 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064 |
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| 153 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065 |
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| 154 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066 |
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| 155 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067 |
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| 156 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068 |
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| 157 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069 |
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| 158 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A |
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| 159 | |
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| 160 | #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C |
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| 161 | #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D |
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| 162 | #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E |
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| 163 | #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F |
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| 164 | #define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070 |
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| 165 | #define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071 |
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| 166 | #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072 |
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| 167 | #define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073 |
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| 168 | #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074 |
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| 169 | #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075 |
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| 170 | #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076 |
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| 171 | #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077 |
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| 172 | #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078 |
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| 173 | #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079 |
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| 174 | #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A |
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| 175 | |
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| 176 | #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C |
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| 177 | #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D |
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| 178 | #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E |
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| 179 | |
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| 180 | #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081 |
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| 181 | #define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082 |
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| 182 | #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083 |
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| 183 | #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084 |
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| 184 | |
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| 185 | #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086 |
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| 186 | #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087 |
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| 187 | #define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088 |
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| 188 | |
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| 189 | #define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A |
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| 190 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B |
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| 191 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C |
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| 192 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D |
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| 193 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E |
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| 194 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F |
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| 195 | #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090 |
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| 196 | #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091 |
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| 197 | |
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| 198 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0 |
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| 199 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1 |
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| 200 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2 |
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| 201 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3 |
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| 202 | |
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| 203 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6 |
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| 204 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7 |
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| 205 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8 |
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| 206 | |
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| 207 | /* |
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| 208 | * Per-CPU PMCR: config reg |
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| 209 | */ |
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| 210 | #define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */ |
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| 211 | #define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */ |
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| 212 | #define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */ |
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| 213 | #define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ |
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| 214 | #define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */ |
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| 215 | #define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ |
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| 216 | #define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ |
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| 217 | #define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */ |
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| 218 | #define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */ |
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| 219 | /* Mask for writable bits */ |
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| 220 | #define ARMV8_PMU_PMCR_MASK (ARMV8_PMU_PMCR_E | ARMV8_PMU_PMCR_P | \ |
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| 221 | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_D | \ |
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| 222 | ARMV8_PMU_PMCR_X | ARMV8_PMU_PMCR_DP | \ |
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| 223 | ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP) |
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| 224 | |
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| 225 | /* |
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| 226 | * PMOVSR: counters overflow flag status reg |
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| 227 | */ |
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| 228 | #define ARMV8_PMU_OVSR_P GENMASK(30, 0) |
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| 229 | #define ARMV8_PMU_OVSR_C BIT(31) |
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| 230 | /* Mask for writable bits is both P and C fields */ |
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| 231 | #define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C) |
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| 232 | |
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| 233 | /* |
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| 234 | * PMXEVTYPER: Event selection reg |
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| 235 | */ |
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| 236 | #define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */ |
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| 237 | #define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */ |
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| 238 | #define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */ |
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| 239 | |
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| 240 | /* |
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| 241 | * Event filters for PMUv3 |
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| 242 | */ |
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| 243 | #define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) |
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| 244 | #define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) |
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| 245 | #define ARMV8_PMU_EXCLUDE_NS_EL1 (1U << 29) |
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| 246 | #define ARMV8_PMU_EXCLUDE_NS_EL0 (1U << 28) |
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| 247 | #define ARMV8_PMU_INCLUDE_EL2 (1U << 27) |
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| 248 | #define ARMV8_PMU_EXCLUDE_EL3 (1U << 26) |
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| 249 | |
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| 250 | /* |
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| 251 | * PMUSERENR: user enable reg |
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| 252 | */ |
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| 253 | #define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */ |
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| 254 | #define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */ |
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| 255 | #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ |
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| 256 | #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ |
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| 257 | /* Mask for writable bits */ |
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| 258 | #define ARMV8_PMU_USERENR_MASK (ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \ |
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| 259 | ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER) |
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| 260 | |
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| 261 | /* PMMIR_EL1.SLOTS mask */ |
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| 262 | #define ARMV8_PMU_SLOTS GENMASK(7, 0) |
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| 263 | #define ARMV8_PMU_BUS_SLOTS GENMASK(15, 8) |
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| 264 | #define ARMV8_PMU_BUS_WIDTH GENMASK(19, 16) |
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| 265 | #define ARMV8_PMU_THWIDTH GENMASK(23, 20) |
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| 266 | |
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| 267 | /* |
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| 268 | * This code is really good |
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| 269 | */ |
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| 270 | |
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| 271 | #define PMEVN_CASE(n, case_macro) \ |
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| 272 | case n: case_macro(n); break |
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| 273 | |
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| 274 | #define PMEVN_SWITCH(x, case_macro) \ |
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| 275 | do { \ |
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| 276 | switch (x) { \ |
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| 277 | PMEVN_CASE(0, case_macro); \ |
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| 278 | PMEVN_CASE(1, case_macro); \ |
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| 279 | PMEVN_CASE(2, case_macro); \ |
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| 280 | PMEVN_CASE(3, case_macro); \ |
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| 281 | PMEVN_CASE(4, case_macro); \ |
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| 282 | PMEVN_CASE(5, case_macro); \ |
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| 283 | PMEVN_CASE(6, case_macro); \ |
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| 284 | PMEVN_CASE(7, case_macro); \ |
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| 285 | PMEVN_CASE(8, case_macro); \ |
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| 286 | PMEVN_CASE(9, case_macro); \ |
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| 287 | PMEVN_CASE(10, case_macro); \ |
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| 288 | PMEVN_CASE(11, case_macro); \ |
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| 289 | PMEVN_CASE(12, case_macro); \ |
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| 290 | PMEVN_CASE(13, case_macro); \ |
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| 291 | PMEVN_CASE(14, case_macro); \ |
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| 292 | PMEVN_CASE(15, case_macro); \ |
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| 293 | PMEVN_CASE(16, case_macro); \ |
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| 294 | PMEVN_CASE(17, case_macro); \ |
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| 295 | PMEVN_CASE(18, case_macro); \ |
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| 296 | PMEVN_CASE(19, case_macro); \ |
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| 297 | PMEVN_CASE(20, case_macro); \ |
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| 298 | PMEVN_CASE(21, case_macro); \ |
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| 299 | PMEVN_CASE(22, case_macro); \ |
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| 300 | PMEVN_CASE(23, case_macro); \ |
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| 301 | PMEVN_CASE(24, case_macro); \ |
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| 302 | PMEVN_CASE(25, case_macro); \ |
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| 303 | PMEVN_CASE(26, case_macro); \ |
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| 304 | PMEVN_CASE(27, case_macro); \ |
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| 305 | PMEVN_CASE(28, case_macro); \ |
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| 306 | PMEVN_CASE(29, case_macro); \ |
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| 307 | PMEVN_CASE(30, case_macro); \ |
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| 308 | default: WARN(1, "Invalid PMEV* index\n"); \ |
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| 309 | } \ |
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| 310 | } while (0) |
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| 311 | |
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| 312 | #endif |
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| 313 | |
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