| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Intel Low Power Subsystem PWM controller driver */ |
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| 3 | |
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| 4 | #ifndef __PLATFORM_DATA_X86_PWM_LPSS_H |
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| 5 | #define __PLATFORM_DATA_X86_PWM_LPSS_H |
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| 6 | |
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| 7 | #include <linux/types.h> |
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| 8 | |
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| 9 | struct device; |
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| 10 | |
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| 11 | struct pwm_lpss_chip; |
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| 12 | |
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| 13 | struct pwm_lpss_boardinfo { |
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| 14 | unsigned long clk_rate; |
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| 15 | unsigned int npwm; |
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| 16 | unsigned long base_unit_bits; |
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| 17 | /* |
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| 18 | * Some versions of the IP may stuck in the state machine if enable |
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| 19 | * bit is not set, and hence update bit will show busy status till |
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| 20 | * the reset. For the rest it may be otherwise. |
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| 21 | */ |
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| 22 | bool bypass; |
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| 23 | /* |
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| 24 | * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device |
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| 25 | * messes with the PWM0 controllers state, |
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| 26 | */ |
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| 27 | bool other_devices_aml_touches_pwm_regs; |
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| 28 | }; |
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| 29 | |
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| 30 | struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base, |
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| 31 | const struct pwm_lpss_boardinfo *info); |
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| 32 | |
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| 33 | #endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ |
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| 34 | |
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