| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __LINUX_SPI_EEPROM_H |
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| 3 | #define __LINUX_SPI_EEPROM_H |
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| 4 | |
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| 5 | #include <linux/memory.h> |
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| 6 | |
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| 7 | /* |
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| 8 | * Put one of these structures in platform_data for SPI EEPROMS handled |
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| 9 | * by the "at25" driver. On SPI, most EEPROMS understand the same core |
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| 10 | * command set. If you need to support EEPROMs that don't yet fit, add |
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| 11 | * flags to support those protocol options. These values all come from |
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| 12 | * the chip datasheets. |
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| 13 | */ |
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| 14 | struct spi_eeprom { |
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| 15 | u32 byte_len; |
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| 16 | char name[10]; |
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| 17 | u32 page_size; /* for writes */ |
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| 18 | u16 flags; |
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| 19 | #define EE_ADDR1 0x0001 /* 8 bit addrs */ |
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| 20 | #define EE_ADDR2 0x0002 /* 16 bit addrs */ |
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| 21 | #define EE_ADDR3 0x0004 /* 24 bit addrs */ |
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| 22 | #define EE_READONLY 0x0008 /* disallow writes */ |
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| 23 | |
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| 24 | /* |
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| 25 | * Certain EEPROMS have a size that is larger than the number of address |
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| 26 | * bytes would allow (e.g. like M95040 from ST that has 512 Byte size |
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| 27 | * but uses only one address byte (A0 to A7) for addressing.) For |
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| 28 | * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte |
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| 29 | * is used. This instruction bit is normally defined as don't care for |
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| 30 | * other AT25 like chips. |
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| 31 | */ |
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| 32 | #define EE_INSTR_BIT3_IS_ADDR 0x0010 |
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| 33 | |
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| 34 | void *context; |
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| 35 | }; |
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| 36 | |
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| 37 | #endif /* __LINUX_SPI_EEPROM_H */ |
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| 38 | |
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