1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * tc358743 - Toshiba HDMI to CSI-2 bridge |
4 | * |
5 | * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved. |
6 | */ |
7 | |
8 | /* |
9 | * References (c = chapter, p = page): |
10 | * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 |
11 | * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls |
12 | */ |
13 | |
14 | #ifndef _TC358743_ |
15 | #define _TC358743_ |
16 | |
17 | enum tc358743_ddc5v_delays { |
18 | DDC5V_DELAY_0_MS, |
19 | DDC5V_DELAY_50_MS, |
20 | DDC5V_DELAY_100_MS, |
21 | DDC5V_DELAY_200_MS, |
22 | }; |
23 | |
24 | enum tc358743_hdmi_detection_delay { |
25 | HDMI_MODE_DELAY_0_MS, |
26 | HDMI_MODE_DELAY_25_MS, |
27 | HDMI_MODE_DELAY_50_MS, |
28 | HDMI_MODE_DELAY_100_MS, |
29 | }; |
30 | |
31 | struct tc358743_platform_data { |
32 | /* System clock connected to REFCLK (pin H5) */ |
33 | u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ |
34 | |
35 | /* DDC +5V debounce delay to avoid spurious interrupts when the cable |
36 | * is connected. |
37 | * Sets DDC5V_MODE in register DDC_CTL. |
38 | * Default: DDC5V_DELAY_0_MS |
39 | */ |
40 | enum tc358743_ddc5v_delays ddc5v_delay; |
41 | |
42 | bool enable_hdcp; |
43 | |
44 | /* |
45 | * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO |
46 | * level to somewhere in the middle (e.g. 300), so it can cover speed |
47 | * mismatches in input and output ports. |
48 | */ |
49 | u16 fifo_level; |
50 | |
51 | /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */ |
52 | u16 pll_prd; |
53 | u16 pll_fbd; |
54 | |
55 | /* CSI |
56 | * Calculate CSI parameters with REF_02 for the highest resolution your |
57 | * CSI interface can handle. The driver will adjust the number of CSI |
58 | * lanes in use according to the pixel clock. |
59 | * |
60 | * The values in brackets are calculated with REF_02 when the number of |
61 | * bps pr lane is 823.5 MHz, and can serve as a starting point. |
62 | */ |
63 | u32 lineinitcnt; /* (0x00001770) */ |
64 | u32 lptxtimecnt; /* (0x00000005) */ |
65 | u32 ; /* (0x00001d04) */ |
66 | u32 tclk_trailcnt; /* (0x00000000) */ |
67 | u32 ; /* (0x00000505) */ |
68 | u32 twakeup; /* (0x00004650) */ |
69 | u32 tclk_postcnt; /* (0x00000000) */ |
70 | u32 ths_trailcnt; /* (0x00000004) */ |
71 | u32 hstxvregcnt; /* (0x00000005) */ |
72 | |
73 | /* DVI->HDMI detection delay to avoid unnecessary switching between DVI |
74 | * and HDMI mode. |
75 | * Sets HDMI_DET_V in register HDMI_DET. |
76 | * Default: HDMI_MODE_DELAY_0_MS |
77 | */ |
78 | enum tc358743_hdmi_detection_delay hdmi_detection_delay; |
79 | |
80 | /* Reset PHY automatically when TMDS clock goes from DC to AC. |
81 | * Sets PHY_AUTO_RST2 in register PHY_CTL2. |
82 | * Default: false |
83 | */ |
84 | bool hdmi_phy_auto_reset_tmds_detected; |
85 | |
86 | /* Reset PHY automatically when TMDS clock passes 21 MHz. |
87 | * Sets PHY_AUTO_RST3 in register PHY_CTL2. |
88 | * Default: false |
89 | */ |
90 | bool hdmi_phy_auto_reset_tmds_in_range; |
91 | |
92 | /* Reset PHY automatically when TMDS clock is detected. |
93 | * Sets PHY_AUTO_RST4 in register PHY_CTL2. |
94 | * Default: false |
95 | */ |
96 | bool hdmi_phy_auto_reset_tmds_valid; |
97 | |
98 | /* Reset HDMI PHY automatically when hsync period is out of range. |
99 | * Sets H_PI_RST in register HV_RST. |
100 | * Default: false |
101 | */ |
102 | bool hdmi_phy_auto_reset_hsync_out_of_range; |
103 | |
104 | /* Reset HDMI PHY automatically when vsync period is out of range. |
105 | * Sets V_PI_RST in register HV_RST. |
106 | * Default: false |
107 | */ |
108 | bool hdmi_phy_auto_reset_vsync_out_of_range; |
109 | }; |
110 | |
111 | /* custom controls */ |
112 | /* Audio sample rate in Hz */ |
113 | #define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0) |
114 | /* Audio present status */ |
115 | #define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1) |
116 | |
117 | #endif |
118 | |