1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * QMC management |
4 | * |
5 | * Copyright 2022 CS GROUP France |
6 | * |
7 | * Author: Herve Codina <herve.codina@bootlin.com> |
8 | */ |
9 | #ifndef __SOC_FSL_QMC_H__ |
10 | #define __SOC_FSL_QMC_H__ |
11 | |
12 | #include <linux/bits.h> |
13 | #include <linux/types.h> |
14 | |
15 | struct device_node; |
16 | struct device; |
17 | struct qmc_chan; |
18 | |
19 | struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name); |
20 | struct qmc_chan *qmc_chan_get_bychild(struct device_node *np); |
21 | void qmc_chan_put(struct qmc_chan *chan); |
22 | struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct device_node *np, |
23 | const char *phandle_name); |
24 | struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct device_node *np); |
25 | |
26 | enum qmc_mode { |
27 | QMC_TRANSPARENT, |
28 | QMC_HDLC, |
29 | }; |
30 | |
31 | struct qmc_chan_info { |
32 | enum qmc_mode mode; |
33 | unsigned long rx_fs_rate; |
34 | unsigned long rx_bit_rate; |
35 | u8 nb_rx_ts; |
36 | unsigned long tx_fs_rate; |
37 | unsigned long tx_bit_rate; |
38 | u8 nb_tx_ts; |
39 | }; |
40 | |
41 | int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info); |
42 | |
43 | struct qmc_chan_ts_info { |
44 | u64 rx_ts_mask_avail; |
45 | u64 tx_ts_mask_avail; |
46 | u64 rx_ts_mask; |
47 | u64 tx_ts_mask; |
48 | }; |
49 | |
50 | int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info); |
51 | int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info); |
52 | |
53 | struct qmc_chan_param { |
54 | enum qmc_mode mode; |
55 | union { |
56 | struct { |
57 | u16 max_rx_buf_size; |
58 | u16 max_rx_frame_size; |
59 | bool is_crc32; |
60 | } hdlc; |
61 | struct { |
62 | u16 max_rx_buf_size; |
63 | } transp; |
64 | }; |
65 | }; |
66 | |
67 | int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param); |
68 | |
69 | int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, |
70 | void (*complete)(void *context), void *context); |
71 | |
72 | /* Flags available (ORed) for read complete() flags parameter in HDLC mode. |
73 | * No flags are available in transparent mode and the read complete() flags |
74 | * parameter has no meaning in transparent mode. |
75 | */ |
76 | #define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */ |
77 | #define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */ |
78 | #define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */ |
79 | #define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */ |
80 | #define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */ |
81 | #define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */ |
82 | |
83 | int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length, |
84 | void (*complete)(void *context, size_t length, |
85 | unsigned int flags), |
86 | void *context); |
87 | |
88 | #define QMC_CHAN_READ (1<<0) |
89 | #define QMC_CHAN_WRITE (1<<1) |
90 | #define QMC_CHAN_ALL (QMC_CHAN_READ | QMC_CHAN_WRITE) |
91 | |
92 | int qmc_chan_start(struct qmc_chan *chan, int direction); |
93 | int qmc_chan_stop(struct qmc_chan *chan, int direction); |
94 | int qmc_chan_reset(struct qmc_chan *chan, int direction); |
95 | |
96 | #endif /* __SOC_FSL_QMC_H__ */ |
97 | |