| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Microsemi Ocelot Switch driver |
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| 4 | * |
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| 5 | * Copyright (c) 2017 Microsemi Corporation |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _MSCC_OCELOT_ANA_H_ |
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| 9 | #define _MSCC_OCELOT_ANA_H_ |
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| 10 | |
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| 11 | #define ANA_ANAGEFIL_B_DOM_EN BIT(22) |
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| 12 | #define ANA_ANAGEFIL_B_DOM_VAL BIT(21) |
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| 13 | #define ANA_ANAGEFIL_AGE_LOCKED BIT(20) |
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| 14 | #define ANA_ANAGEFIL_PID_EN BIT(19) |
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| 15 | #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) |
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| 16 | #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14) |
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| 17 | #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) |
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| 18 | #define ANA_ANAGEFIL_VID_EN BIT(13) |
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| 19 | #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) |
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| 20 | #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0) |
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| 21 | |
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| 22 | #define ANA_STORMLIMIT_CFG_RSZ 0x4 |
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| 23 | |
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| 24 | #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) |
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| 25 | #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3) |
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| 26 | #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) |
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| 27 | #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2) |
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| 28 | #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) |
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| 29 | #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0) |
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| 30 | |
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| 31 | #define ANA_AUTOAGE_AGE_FAST BIT(21) |
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| 32 | #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1)) |
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| 33 | #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1) |
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| 34 | #define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1) |
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| 35 | #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0) |
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| 36 | |
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| 37 | #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1) |
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| 38 | #define ANA_MACTOPTIONS_SHADOW BIT(0) |
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| 39 | |
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| 40 | #define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12)) |
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| 41 | #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12) |
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| 42 | #define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12) |
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| 43 | #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11) |
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| 44 | #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10) |
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| 45 | #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9) |
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| 46 | #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8) |
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| 47 | #define ANA_AGENCTRL_MIRROR_CPU BIT(7) |
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| 48 | #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6) |
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| 49 | #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5) |
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| 50 | #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4) |
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| 51 | #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3) |
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| 52 | #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2) |
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| 53 | #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1) |
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| 54 | #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0) |
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| 55 | |
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| 56 | #define ANA_FLOODING_RSZ 0x4 |
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| 57 | |
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| 58 | #define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12)) |
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| 59 | #define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12) |
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| 60 | #define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12) |
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| 61 | #define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6)) |
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| 62 | #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6) |
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| 63 | #define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6) |
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| 64 | #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) |
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| 65 | #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0) |
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| 66 | |
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| 67 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18)) |
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| 68 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18) |
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| 69 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18) |
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| 70 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12)) |
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| 71 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12) |
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| 72 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12) |
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| 73 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6)) |
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| 74 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6) |
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| 75 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6) |
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| 76 | #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) |
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| 77 | #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0) |
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| 78 | |
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| 79 | #define ANA_SFLOW_CFG_RSZ 0x4 |
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| 80 | |
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| 81 | #define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2)) |
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| 82 | #define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2) |
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| 83 | #define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2) |
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| 84 | #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1) |
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| 85 | #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0) |
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| 86 | |
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| 87 | #define ANA_PORT_MODE_RSZ 0x4 |
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| 88 | |
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| 89 | #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3) |
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| 90 | #define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1)) |
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| 91 | #define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1) |
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| 92 | #define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1) |
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| 93 | #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0) |
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| 94 | |
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| 95 | #define ANA_CUT_THRU_CFG_RSZ 0x4 |
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| 96 | |
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| 97 | #define ANA_PGID_PGID_RSZ 0x4 |
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| 98 | |
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| 99 | #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) |
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| 100 | #define ANA_PGID_PGID_PGID_M GENMASK(11, 0) |
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| 101 | #define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27)) |
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| 102 | #define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27) |
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| 103 | #define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27) |
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| 104 | |
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| 105 | #define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16)) |
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| 106 | #define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16) |
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| 107 | #define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16) |
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| 108 | #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) |
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| 109 | #define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0) |
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| 110 | |
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| 111 | #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16) |
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| 112 | #define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9)) |
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| 113 | #define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9) |
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| 114 | #define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9) |
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| 115 | #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8) |
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| 116 | #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) |
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| 117 | #define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0) |
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| 118 | |
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| 119 | #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15) |
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| 120 | #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14) |
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| 121 | #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13) |
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| 122 | #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12) |
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| 123 | #define ANA_TABLES_MACACCESS_VALID BIT(11) |
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| 124 | #define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9)) |
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| 125 | #define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9) |
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| 126 | #define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9) |
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| 127 | #define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3)) |
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| 128 | #define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3) |
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| 129 | #define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3) |
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| 130 | #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) |
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| 131 | #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0) |
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| 132 | #define MACACCESS_CMD_IDLE 0 |
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| 133 | #define MACACCESS_CMD_LEARN 1 |
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| 134 | #define MACACCESS_CMD_FORGET 2 |
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| 135 | #define MACACCESS_CMD_AGE 3 |
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| 136 | #define MACACCESS_CMD_GET_NEXT 4 |
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| 137 | #define MACACCESS_CMD_INIT 5 |
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| 138 | #define MACACCESS_CMD_READ 6 |
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| 139 | #define MACACCESS_CMD_WRITE 7 |
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| 140 | |
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| 141 | #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2)) |
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| 142 | #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2) |
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| 143 | #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2) |
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| 144 | #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) |
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| 145 | #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0) |
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| 146 | #define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0 |
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| 147 | #define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2 |
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| 148 | #define ANA_TABLES_VLANACCESS_CMD_INIT 0x3 |
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| 149 | |
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| 150 | #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17) |
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| 151 | #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16) |
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| 152 | #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15) |
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| 153 | #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14) |
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| 154 | #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13) |
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| 155 | #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12) |
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| 156 | #define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0)) |
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| 157 | #define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0) |
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| 158 | |
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| 159 | #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2)) |
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| 160 | #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2) |
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| 161 | #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2) |
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| 162 | #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) |
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| 163 | #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0) |
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| 164 | |
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| 165 | #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21)) |
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| 166 | #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21) |
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| 167 | #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21) |
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| 168 | #define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15)) |
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| 169 | #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15) |
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| 170 | #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15) |
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| 171 | #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14) |
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| 172 | #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10) |
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| 173 | #define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0)) |
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| 174 | #define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0) |
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| 175 | |
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| 176 | #define ANA_TABLES_ENTRYLIM_RSZ 0x4 |
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| 177 | |
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| 178 | #define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14)) |
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| 179 | #define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14) |
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| 180 | #define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14) |
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| 181 | #define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0)) |
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| 182 | #define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0) |
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| 183 | |
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| 184 | #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4)) |
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| 185 | #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4) |
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| 186 | #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4) |
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| 187 | #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3) |
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| 188 | #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2) |
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| 189 | #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0)) |
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| 190 | #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0) |
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| 191 | |
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| 192 | #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30)) |
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| 193 | #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30) |
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| 194 | #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30) |
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| 195 | #define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16)) |
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| 196 | #define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16) |
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| 197 | #define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16) |
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| 198 | #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14) |
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| 199 | #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8)) |
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| 200 | #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8) |
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| 201 | #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8) |
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| 202 | #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7) |
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| 203 | #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6) |
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| 204 | #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5) |
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| 205 | #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0)) |
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| 206 | #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0) |
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| 207 | |
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| 208 | #define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16)) |
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| 209 | #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16) |
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| 210 | #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16) |
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| 211 | #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0)) |
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| 212 | #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0) |
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| 213 | |
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| 214 | #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1)) |
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| 215 | #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1) |
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| 216 | #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1) |
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| 217 | #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0) |
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| 218 | |
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| 219 | #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22) |
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| 220 | #define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19)) |
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| 221 | #define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19) |
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| 222 | #define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19) |
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| 223 | #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18) |
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| 224 | #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2)) |
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| 225 | #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2) |
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| 226 | #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2) |
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| 227 | #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0)) |
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| 228 | #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0) |
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| 229 | |
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| 230 | #define SFIDACCESS_CMD_IDLE 0 |
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| 231 | #define SFIDACCESS_CMD_READ 1 |
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| 232 | #define SFIDACCESS_CMD_WRITE 2 |
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| 233 | #define SFIDACCESS_CMD_INIT 3 |
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| 234 | |
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| 235 | #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26) |
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| 236 | #define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18)) |
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| 237 | #define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18) |
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| 238 | #define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18) |
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| 239 | #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17) |
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| 240 | #define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8)) |
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| 241 | #define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8) |
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| 242 | #define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8) |
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| 243 | #define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0)) |
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| 244 | #define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0) |
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| 245 | |
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| 246 | #define ANA_MSTI_STATE_RSZ 0x4 |
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| 247 | |
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| 248 | #define ANA_OAM_UPM_LM_CNT_RSZ 0x4 |
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| 249 | |
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| 250 | #define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0)) |
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| 251 | #define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0) |
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| 252 | #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) |
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| 253 | |
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| 254 | #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) |
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| 255 | #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) |
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| 256 | #define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16)) |
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| 257 | #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16) |
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| 258 | #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16) |
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| 259 | #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) |
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| 260 | #define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21)) |
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| 261 | #define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21) |
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| 262 | #define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21) |
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| 263 | #define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24) |
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| 264 | #define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24)) |
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| 265 | #define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21)) |
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| 266 | #define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21) |
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| 267 | #define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21) |
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| 268 | #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) |
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| 269 | |
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| 270 | #define ANA_SG_GCL_GS_CONFIG_RSZ 0x4 |
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| 271 | |
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| 272 | #define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0)) |
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| 273 | #define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0) |
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| 274 | #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) |
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| 275 | |
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| 276 | #define ANA_SG_GCL_TI_CONFIG_RSZ 0x4 |
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| 277 | |
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| 278 | #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) |
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| 279 | #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) |
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| 280 | #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16) |
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| 281 | #define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20)) |
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| 282 | #define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20) |
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| 283 | #define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20) |
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| 284 | #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) |
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| 285 | |
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| 286 | #define ANA_PORT_VLAN_CFG_GSZ 0x100 |
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| 287 | |
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| 288 | #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21) |
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| 289 | #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20) |
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| 290 | #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18)) |
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| 291 | #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18) |
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| 292 | #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18) |
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| 293 | #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17) |
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| 294 | #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16) |
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| 295 | #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15) |
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| 296 | #define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12)) |
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| 297 | #define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12) |
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| 298 | #define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) |
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| 299 | #define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0)) |
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| 300 | #define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0) |
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| 301 | |
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| 302 | #define ANA_PORT_DROP_CFG_GSZ 0x100 |
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| 303 | |
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| 304 | #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) |
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| 305 | #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5) |
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| 306 | #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4) |
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| 307 | #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) |
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| 308 | #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) |
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| 309 | #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1) |
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| 310 | #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) |
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| 311 | |
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| 312 | #define ANA_PORT_QOS_CFG_GSZ 0x100 |
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| 313 | |
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| 314 | #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8) |
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| 315 | #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5)) |
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| 316 | #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5) |
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| 317 | #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5) |
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| 318 | #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4) |
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| 319 | #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3) |
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| 320 | #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2) |
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| 321 | #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0)) |
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| 322 | #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0) |
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| 323 | |
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| 324 | #define ANA_PORT_VCAP_CFG_GSZ 0x100 |
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| 325 | |
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| 326 | #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14) |
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| 327 | #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11)) |
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| 328 | #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11) |
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| 329 | #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11) |
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| 330 | #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8)) |
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| 331 | #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8) |
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| 332 | #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8) |
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| 333 | #define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0)) |
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| 334 | #define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0) |
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| 335 | |
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| 336 | #define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100 |
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| 337 | #define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4 |
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| 338 | |
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| 339 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4)) |
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| 340 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4) |
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| 341 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4) |
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| 342 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2)) |
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| 343 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2) |
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| 344 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) |
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| 345 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0)) |
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| 346 | #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0) |
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| 347 | |
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| 348 | #define ANA_PORT_VCAP_S2_CFG_GSZ 0x100 |
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| 349 | |
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| 350 | #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17)) |
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| 351 | #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17) |
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| 352 | #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17) |
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| 353 | #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15)) |
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| 354 | #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15) |
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| 355 | #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15) |
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| 356 | #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14) |
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| 357 | #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12)) |
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| 358 | #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12) |
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| 359 | #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12) |
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| 360 | #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10)) |
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| 361 | #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10) |
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| 362 | #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10) |
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| 363 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8)) |
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| 364 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8) |
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| 365 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8) |
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| 366 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6)) |
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| 367 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6) |
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| 368 | #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6) |
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| 369 | #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2)) |
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| 370 | #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2) |
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| 371 | #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2) |
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| 372 | #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0)) |
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| 373 | #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0) |
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| 374 | |
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| 375 | #define ANA_PORT_PCP_DEI_MAP_GSZ 0x100 |
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| 376 | #define ANA_PORT_PCP_DEI_MAP_RSZ 0x4 |
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| 377 | |
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| 378 | #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3) |
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| 379 | #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0)) |
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| 380 | #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0) |
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| 381 | |
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| 382 | #define ANA_PORT_CPU_FWD_CFG_GSZ 0x100 |
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| 383 | |
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| 384 | #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7) |
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| 385 | #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6) |
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| 386 | #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5) |
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| 387 | #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4) |
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| 388 | #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3) |
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| 389 | #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2) |
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| 390 | #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1) |
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| 391 | #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0) |
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| 392 | |
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| 393 | #define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100 |
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| 394 | |
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| 395 | #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) |
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| 396 | #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16) |
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| 397 | #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) |
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| 398 | #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0)) |
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| 399 | #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0) |
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| 400 | |
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| 401 | #define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100 |
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| 402 | |
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| 403 | #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) |
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| 404 | #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16) |
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| 405 | #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) |
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| 406 | #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0)) |
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| 407 | #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0) |
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| 408 | |
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| 409 | #define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100 |
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| 410 | |
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| 411 | #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) |
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| 412 | #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16) |
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| 413 | #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) |
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| 414 | #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0)) |
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| 415 | #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0) |
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| 416 | |
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| 417 | #define ANA_PORT_PORT_CFG_GSZ 0x100 |
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| 418 | |
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| 419 | #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15) |
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| 420 | #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14) |
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| 421 | #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13) |
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| 422 | #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12) |
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| 423 | #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11) |
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| 424 | #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10) |
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| 425 | #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9) |
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| 426 | #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8) |
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| 427 | #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7) |
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| 428 | #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) |
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| 429 | #define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2)) |
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| 430 | #define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2) |
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| 431 | #define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2) |
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| 432 | #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1) |
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| 433 | #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0) |
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| 434 | |
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| 435 | #define ANA_PORT_POL_CFG_GSZ 0x100 |
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| 436 | |
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| 437 | #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19) |
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| 438 | #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18) |
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| 439 | #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17) |
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| 440 | #define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9)) |
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| 441 | #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9) |
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| 442 | #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9) |
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| 443 | #define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0)) |
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| 444 | #define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0) |
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| 445 | |
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| 446 | #define ANA_PORT_PTP_CFG_GSZ 0x100 |
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| 447 | |
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| 448 | #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0) |
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| 449 | |
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| 450 | #define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100 |
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| 451 | |
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| 452 | #define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100 |
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| 453 | |
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| 454 | #define ANA_PORT_SFID_CFG_GSZ 0x100 |
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| 455 | #define ANA_PORT_SFID_CFG_RSZ 0x4 |
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| 456 | |
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| 457 | #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8) |
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| 458 | #define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0)) |
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| 459 | #define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0) |
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| 460 | |
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| 461 | #define ANA_PFC_PFC_CFG_GSZ 0x40 |
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| 462 | |
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| 463 | #define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2)) |
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| 464 | #define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2) |
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| 465 | #define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2) |
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| 466 | #define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0)) |
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| 467 | #define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0) |
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| 468 | |
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| 469 | #define ANA_PFC_PFC_TIMER_GSZ 0x40 |
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| 470 | #define ANA_PFC_PFC_TIMER_RSZ 0x4 |
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| 471 | |
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| 472 | #define ANA_IPT_OAM_MEP_CFG_GSZ 0x8 |
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| 473 | |
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| 474 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6)) |
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| 475 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6) |
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| 476 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6) |
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| 477 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1)) |
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| 478 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1) |
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| 479 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1) |
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| 480 | #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0) |
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| 481 | |
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| 482 | #define ANA_IPT_IPT_GSZ 0x8 |
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| 483 | |
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| 484 | #define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15)) |
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| 485 | #define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15) |
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| 486 | #define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15) |
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| 487 | #define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7)) |
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| 488 | #define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7) |
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| 489 | #define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7) |
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| 490 | #define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0)) |
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| 491 | #define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0) |
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| 492 | |
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| 493 | #define ANA_PPT_PPT_RSZ 0x4 |
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| 494 | |
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| 495 | #define ANA_FID_MAP_FID_MAP_RSZ 0x4 |
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| 496 | |
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| 497 | #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6)) |
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| 498 | #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6) |
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| 499 | #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6) |
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| 500 | #define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0)) |
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| 501 | #define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0) |
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| 502 | |
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| 503 | #define ANA_AGGR_CFG_AC_RND_ENA BIT(7) |
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| 504 | #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6) |
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| 505 | #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5) |
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| 506 | #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4) |
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| 507 | #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3) |
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| 508 | #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2) |
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| 509 | #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1) |
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| 510 | #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0) |
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| 511 | |
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| 512 | #define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27)) |
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| 513 | #define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27) |
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| 514 | #define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27) |
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| 515 | #define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24)) |
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| 516 | #define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24) |
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| 517 | #define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24) |
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| 518 | #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21)) |
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| 519 | #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21) |
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| 520 | #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21) |
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| 521 | #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18)) |
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| 522 | #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18) |
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| 523 | #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18) |
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| 524 | #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15)) |
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| 525 | #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15) |
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| 526 | #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15) |
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| 527 | #define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12)) |
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| 528 | #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12) |
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| 529 | #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12) |
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| 530 | #define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9)) |
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| 531 | #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9) |
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| 532 | #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9) |
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| 533 | #define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6)) |
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| 534 | #define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6) |
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| 535 | #define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6) |
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| 536 | #define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3)) |
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| 537 | #define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3) |
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| 538 | #define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3) |
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| 539 | #define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0)) |
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| 540 | #define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0) |
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| 541 | |
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| 542 | #define ANA_CPUQ_8021_CFG_RSZ 0x4 |
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| 543 | |
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| 544 | #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6)) |
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| 545 | #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6) |
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| 546 | #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6) |
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| 547 | #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3)) |
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| 548 | #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3) |
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| 549 | #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3) |
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| 550 | #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0)) |
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| 551 | #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0) |
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| 552 | |
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| 553 | #define ANA_DSCP_CFG_RSZ 0x4 |
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| 554 | |
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| 555 | #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) |
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| 556 | #define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8)) |
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| 557 | #define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8) |
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| 558 | #define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8) |
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| 559 | #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2)) |
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| 560 | #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2) |
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| 561 | #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2) |
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| 562 | #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) |
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| 563 | #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) |
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| 564 | |
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| 565 | #define ANA_DSCP_REWR_CFG_RSZ 0x4 |
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| 566 | |
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| 567 | #define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4 |
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| 568 | |
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| 569 | #define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4 |
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| 570 | |
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| 571 | #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16)) |
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| 572 | #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16) |
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| 573 | #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16) |
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| 574 | #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0)) |
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| 575 | #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0) |
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| 576 | |
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| 577 | #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12) |
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| 578 | #define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0)) |
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| 579 | #define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0) |
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| 580 | |
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| 581 | #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3) |
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| 582 | #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2) |
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| 583 | #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1) |
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| 584 | #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0) |
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| 585 | |
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| 586 | #define ANA_FID_CFG_VID_MC_ENA BIT(0) |
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| 587 | |
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| 588 | #define ANA_POL_PIR_CFG_GSZ 0x20 |
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| 589 | |
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| 590 | #define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) |
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| 591 | #define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6) |
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| 592 | #define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) |
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| 593 | #define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0)) |
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| 594 | #define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0) |
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| 595 | |
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| 596 | #define ANA_POL_CIR_CFG_GSZ 0x20 |
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| 597 | |
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| 598 | #define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) |
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| 599 | #define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6) |
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| 600 | #define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) |
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| 601 | #define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) |
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| 602 | #define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0) |
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| 603 | |
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| 604 | #define ANA_POL_MODE_CFG_GSZ 0x20 |
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| 605 | |
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| 606 | #define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5)) |
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| 607 | #define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5) |
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| 608 | #define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5) |
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| 609 | #define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3)) |
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| 610 | #define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3) |
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| 611 | #define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3) |
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| 612 | #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2) |
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| 613 | #define ANA_POL_MODE_CFG_CIR_ENA BIT(1) |
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| 614 | #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0) |
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| 615 | |
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| 616 | #define ANA_POL_PIR_STATE_GSZ 0x20 |
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| 617 | |
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| 618 | #define ANA_POL_CIR_STATE_GSZ 0x20 |
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| 619 | |
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| 620 | #define ANA_POL_STATE_GSZ 0x20 |
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| 621 | |
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| 622 | #define ANA_POL_FLOWC_RSZ 0x4 |
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| 623 | |
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| 624 | #define ANA_POL_FLOWC_POL_FLOWC BIT(0) |
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| 625 | |
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| 626 | #define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4)) |
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| 627 | #define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4) |
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| 628 | #define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4) |
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| 629 | #define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0)) |
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| 630 | #define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0) |
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| 631 | |
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| 632 | #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1) |
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| 633 | #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0) |
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| 634 | |
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| 635 | #endif |
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| 636 | |
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