1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef __SOC_QCOM_TCS_H__ |
7 | #define __SOC_QCOM_TCS_H__ |
8 | |
9 | #define MAX_RPMH_PAYLOAD 16 |
10 | |
11 | /** |
12 | * rpmh_state: state for the request |
13 | * |
14 | * RPMH_SLEEP_STATE: State of the resource when the processor subsystem |
15 | * is powered down. There is no client using the |
16 | * resource actively. |
17 | * RPMH_WAKE_ONLY_STATE: Resume resource state to the value previously |
18 | * requested before the processor was powered down. |
19 | * RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state |
20 | * is aggregated immediately. |
21 | */ |
22 | enum rpmh_state { |
23 | RPMH_SLEEP_STATE, |
24 | RPMH_WAKE_ONLY_STATE, |
25 | RPMH_ACTIVE_ONLY_STATE, |
26 | }; |
27 | |
28 | /** |
29 | * struct tcs_cmd: an individual request to RPMH. |
30 | * |
31 | * @addr: the address of the resource slv_id:18:16 | offset:0:15 |
32 | * @data: the resource state request |
33 | * @wait: ensure that this command is complete before returning. |
34 | * Setting "wait" here only makes sense during rpmh_write_batch() for |
35 | * active-only transfers, this is because: |
36 | * rpmh_write() - Always waits. |
37 | * (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl) |
38 | * rpmh_write_async() - Never waits. |
39 | * (There's no request completion callback) |
40 | */ |
41 | struct tcs_cmd { |
42 | u32 addr; |
43 | u32 data; |
44 | u32 wait; |
45 | }; |
46 | |
47 | /** |
48 | * struct tcs_request: A set of tcs_cmds sent together in a TCS |
49 | * |
50 | * @state: state for the request. |
51 | * @wait_for_compl: wait until we get a response from the h/w accelerator |
52 | * (same as setting cmd->wait for all commands in the request) |
53 | * @num_cmds: the number of @cmds in this request |
54 | * @cmds: an array of tcs_cmds |
55 | */ |
56 | struct tcs_request { |
57 | enum rpmh_state state; |
58 | u32 wait_for_compl; |
59 | u32 num_cmds; |
60 | struct tcs_cmd *cmds; |
61 | }; |
62 | |
63 | #define BCM_TCS_CMD_COMMIT_SHFT 30 |
64 | #define BCM_TCS_CMD_COMMIT_MASK 0x40000000 |
65 | #define BCM_TCS_CMD_VALID_SHFT 29 |
66 | #define BCM_TCS_CMD_VALID_MASK 0x20000000 |
67 | #define BCM_TCS_CMD_VOTE_X_SHFT 14 |
68 | #define BCM_TCS_CMD_VOTE_MASK 0x3fff |
69 | #define BCM_TCS_CMD_VOTE_Y_SHFT 0 |
70 | #define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000 |
71 | |
72 | /* Construct a Bus Clock Manager (BCM) specific TCS command */ |
73 | #define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \ |
74 | (((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \ |
75 | ((valid) << BCM_TCS_CMD_VALID_SHFT) | \ |
76 | ((cpu_to_le32(vote_x) & \ |
77 | BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \ |
78 | ((cpu_to_le32(vote_y) & \ |
79 | BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT)) |
80 | |
81 | #endif /* __SOC_QCOM_TCS_H__ */ |
82 | |