| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Functions and macros to control the flowcontroller |
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| 4 | * |
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| 5 | * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __SOC_TEGRA_FLOWCTRL_H__ |
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| 9 | #define __SOC_TEGRA_FLOWCTRL_H__ |
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| 10 | |
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| 11 | #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 |
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| 12 | #define FLOW_CTRL_WAITEVENT (2 << 29) |
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| 13 | #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) |
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| 14 | #define FLOW_CTRL_JTAG_RESUME (1 << 28) |
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| 15 | #define FLOW_CTRL_SCLK_RESUME (1 << 27) |
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| 16 | #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) |
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| 17 | #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) |
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| 18 | #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) |
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| 19 | #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) |
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| 20 | #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) |
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| 21 | #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) |
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| 22 | #define FLOW_CTRL_CPU0_CSR 0x8 |
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| 23 | #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) |
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| 24 | #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) |
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| 25 | #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) |
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| 26 | #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) |
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| 27 | #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ |
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| 28 | FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ |
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| 29 | FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) |
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| 30 | #define FLOW_CTRL_CSR_ENABLE (1 << 0) |
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| 31 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 |
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| 32 | #define FLOW_CTRL_CPU1_CSR 0x18 |
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| 33 | |
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| 34 | #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) |
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| 35 | #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) |
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| 36 | #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 |
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| 37 | |
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| 38 | #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) |
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| 39 | #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) |
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| 40 | #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) |
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| 41 | |
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| 42 | #ifndef __ASSEMBLY__ |
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| 43 | #ifdef CONFIG_SOC_TEGRA_FLOWCTRL |
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| 44 | u32 flowctrl_read_cpu_csr(unsigned int cpuid); |
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| 45 | void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); |
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| 46 | void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); |
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| 47 | |
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| 48 | void flowctrl_cpu_suspend_enter(unsigned int cpuid); |
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| 49 | void flowctrl_cpu_suspend_exit(unsigned int cpuid); |
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| 50 | #else |
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| 51 | static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid) |
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| 52 | { |
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| 53 | return 0; |
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| 54 | } |
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| 55 | |
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| 56 | static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) |
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| 57 | { |
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| 58 | } |
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| 59 | |
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| 60 | static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {} |
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| 61 | |
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| 62 | static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid) |
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| 63 | { |
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| 64 | } |
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| 65 | |
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| 66 | static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid) |
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| 67 | { |
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| 68 | } |
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| 69 | #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */ |
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| 70 | #endif /* __ASSEMBLY */ |
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| 71 | #endif /* __SOC_TEGRA_FLOWCTRL_H__ */ |
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| 72 | |
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