1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef __SOC_TEGRA_FUSE_H__ |
7 | #define __SOC_TEGRA_FUSE_H__ |
8 | |
9 | #include <linux/types.h> |
10 | |
11 | #define TEGRA20 0x20 |
12 | #define TEGRA30 0x30 |
13 | #define TEGRA114 0x35 |
14 | #define TEGRA124 0x40 |
15 | #define TEGRA132 0x13 |
16 | #define TEGRA210 0x21 |
17 | #define TEGRA186 0x18 |
18 | #define TEGRA194 0x19 |
19 | #define TEGRA234 0x23 |
20 | #define TEGRA264 0x26 |
21 | |
22 | #define TEGRA_FUSE_SKU_CALIB_0 0xf0 |
23 | #define TEGRA30_FUSE_SATA_CALIB 0x124 |
24 | #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 |
25 | |
26 | #ifndef __ASSEMBLY__ |
27 | |
28 | enum tegra_revision { |
29 | TEGRA_REVISION_UNKNOWN = 0, |
30 | TEGRA_REVISION_A01, |
31 | TEGRA_REVISION_A02, |
32 | TEGRA_REVISION_A03, |
33 | TEGRA_REVISION_A03p, |
34 | TEGRA_REVISION_A04, |
35 | TEGRA_REVISION_MAX, |
36 | }; |
37 | |
38 | enum tegra_platform { |
39 | TEGRA_PLATFORM_SILICON = 0, |
40 | TEGRA_PLATFORM_QT, |
41 | TEGRA_PLATFORM_SYSTEM_FPGA, |
42 | TEGRA_PLATFORM_UNIT_FPGA, |
43 | TEGRA_PLATFORM_ASIM_QT, |
44 | TEGRA_PLATFORM_ASIM_LINSIM, |
45 | TEGRA_PLATFORM_DSIM_ASIM_LINSIM, |
46 | TEGRA_PLATFORM_VERIFICATION_SIMULATION, |
47 | TEGRA_PLATFORM_VDK, |
48 | TEGRA_PLATFORM_VSP, |
49 | TEGRA_PLATFORM_MAX, |
50 | }; |
51 | |
52 | struct tegra_sku_info { |
53 | int sku_id; |
54 | int cpu_process_id; |
55 | int cpu_speedo_id; |
56 | int cpu_speedo_value; |
57 | int cpu_iddq_value; |
58 | int soc_process_id; |
59 | int soc_speedo_id; |
60 | int soc_speedo_value; |
61 | int gpu_process_id; |
62 | int gpu_speedo_id; |
63 | int gpu_speedo_value; |
64 | enum tegra_revision revision; |
65 | enum tegra_platform platform; |
66 | }; |
67 | |
68 | #ifdef CONFIG_ARCH_TEGRA |
69 | extern struct tegra_sku_info tegra_sku_info; |
70 | u32 tegra_read_straps(void); |
71 | u32 tegra_read_ram_code(void); |
72 | int tegra_fuse_readl(unsigned long offset, u32 *value); |
73 | u32 tegra_read_chipid(void); |
74 | u8 tegra_get_chip_id(void); |
75 | u8 tegra_get_platform(void); |
76 | bool tegra_is_silicon(void); |
77 | int tegra194_miscreg_mask_serror(void); |
78 | #else |
79 | static struct tegra_sku_info tegra_sku_info __maybe_unused; |
80 | |
81 | static inline u32 tegra_read_straps(void) |
82 | { |
83 | return 0; |
84 | } |
85 | |
86 | static inline u32 tegra_read_ram_code(void) |
87 | { |
88 | return 0; |
89 | } |
90 | |
91 | static inline int tegra_fuse_readl(unsigned long offset, u32 *value) |
92 | { |
93 | return -ENODEV; |
94 | } |
95 | |
96 | static inline u32 tegra_read_chipid(void) |
97 | { |
98 | return 0; |
99 | } |
100 | |
101 | static inline u8 tegra_get_chip_id(void) |
102 | { |
103 | return 0; |
104 | } |
105 | |
106 | static inline u8 tegra_get_platform(void) |
107 | { |
108 | return 0; |
109 | } |
110 | |
111 | static inline bool tegra_is_silicon(void) |
112 | { |
113 | return false; |
114 | } |
115 | |
116 | static inline int tegra194_miscreg_mask_serror(void) |
117 | { |
118 | return false; |
119 | } |
120 | #endif |
121 | |
122 | struct device *tegra_soc_device_register(void); |
123 | |
124 | #endif /* __ASSEMBLY__ */ |
125 | |
126 | #endif /* __SOC_TEGRA_FUSE_H__ */ |
127 | |