1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __SOC_TEGRA_FUSE_H__
18#define __SOC_TEGRA_FUSE_H__
19
20#define TEGRA20 0x20
21#define TEGRA30 0x30
22#define TEGRA114 0x35
23#define TEGRA124 0x40
24#define TEGRA132 0x13
25#define TEGRA210 0x21
26
27#define TEGRA_FUSE_SKU_CALIB_0 0xf0
28#define TEGRA30_FUSE_SATA_CALIB 0x124
29#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
30
31#ifndef __ASSEMBLY__
32
33u32 tegra_read_chipid(void);
34u8 tegra_get_chip_id(void);
35
36enum tegra_revision {
37 TEGRA_REVISION_UNKNOWN = 0,
38 TEGRA_REVISION_A01,
39 TEGRA_REVISION_A02,
40 TEGRA_REVISION_A03,
41 TEGRA_REVISION_A03p,
42 TEGRA_REVISION_A04,
43 TEGRA_REVISION_MAX,
44};
45
46struct tegra_sku_info {
47 int sku_id;
48 int cpu_process_id;
49 int cpu_speedo_id;
50 int cpu_speedo_value;
51 int cpu_iddq_value;
52 int soc_process_id;
53 int soc_speedo_id;
54 int soc_speedo_value;
55 int gpu_process_id;
56 int gpu_speedo_id;
57 int gpu_speedo_value;
58 enum tegra_revision revision;
59};
60
61u32 tegra_read_straps(void);
62u32 tegra_read_ram_code(void);
63int tegra_fuse_readl(unsigned long offset, u32 *value);
64
65extern struct tegra_sku_info tegra_sku_info;
66
67struct device *tegra_soc_device_register(void);
68
69#endif /* __ASSEMBLY__ */
70
71#endif /* __SOC_TEGRA_FUSE_H__ */
72