1 | /* |
2 | * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device |
3 | * |
4 | * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha |
5 | * |
6 | * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $ |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public |
9 | * License. See the file COPYING in the main directory of this archive for |
10 | * more details. |
11 | */ |
12 | |
13 | #ifndef TGAFB_H |
14 | #define TGAFB_H |
15 | |
16 | /* |
17 | * TGA hardware description (minimal) |
18 | */ |
19 | |
20 | #define TGA_TYPE_8PLANE 0 |
21 | #define TGA_TYPE_24PLANE 1 |
22 | #define TGA_TYPE_24PLUSZ 3 |
23 | |
24 | /* |
25 | * Offsets within Memory Space |
26 | */ |
27 | |
28 | #define TGA_ROM_OFFSET 0x0000000 |
29 | #define TGA_REGS_OFFSET 0x0100000 |
30 | #define TGA_8PLANE_FB_OFFSET 0x0200000 |
31 | #define TGA_24PLANE_FB_OFFSET 0x0804000 |
32 | #define TGA_24PLUSZ_FB_OFFSET 0x1004000 |
33 | |
34 | #define TGA_FOREGROUND_REG 0x0020 |
35 | #define TGA_BACKGROUND_REG 0x0024 |
36 | #define TGA_PLANEMASK_REG 0x0028 |
37 | #define TGA_PIXELMASK_ONESHOT_REG 0x002c |
38 | #define TGA_MODE_REG 0x0030 |
39 | #define TGA_RASTEROP_REG 0x0034 |
40 | #define TGA_PIXELSHIFT_REG 0x0038 |
41 | #define TGA_DEEP_REG 0x0050 |
42 | #define TGA_START_REG 0x0054 |
43 | #define TGA_PIXELMASK_REG 0x005c |
44 | #define TGA_CURSOR_BASE_REG 0x0060 |
45 | #define TGA_HORIZ_REG 0x0064 |
46 | #define TGA_VERT_REG 0x0068 |
47 | #define TGA_BASE_ADDR_REG 0x006c |
48 | #define TGA_VALID_REG 0x0070 |
49 | #define TGA_CURSOR_XY_REG 0x0074 |
50 | #define TGA_INTR_STAT_REG 0x007c |
51 | #define TGA_DATA_REG 0x0080 |
52 | #define TGA_RAMDAC_SETUP_REG 0x00c0 |
53 | #define TGA_BLOCK_COLOR0_REG 0x0140 |
54 | #define TGA_BLOCK_COLOR1_REG 0x0144 |
55 | #define TGA_BLOCK_COLOR2_REG 0x0148 |
56 | #define TGA_BLOCK_COLOR3_REG 0x014c |
57 | #define TGA_BLOCK_COLOR4_REG 0x0150 |
58 | #define TGA_BLOCK_COLOR5_REG 0x0154 |
59 | #define TGA_BLOCK_COLOR6_REG 0x0158 |
60 | #define TGA_BLOCK_COLOR7_REG 0x015c |
61 | #define TGA_COPY64_SRC 0x0160 |
62 | #define TGA_COPY64_DST 0x0164 |
63 | #define TGA_CLOCK_REG 0x01e8 |
64 | #define TGA_RAMDAC_REG 0x01f0 |
65 | #define TGA_CMD_STAT_REG 0x01f8 |
66 | |
67 | |
68 | /* |
69 | * Useful defines for managing the registers |
70 | */ |
71 | |
72 | #define TGA_HORIZ_ODD 0x80000000 |
73 | #define TGA_HORIZ_POLARITY 0x40000000 |
74 | #define TGA_HORIZ_ACT_MSB 0x30000000 |
75 | #define TGA_HORIZ_BP 0x0fe00000 |
76 | #define TGA_HORIZ_SYNC 0x001fc000 |
77 | #define TGA_HORIZ_FP 0x00007c00 |
78 | #define TGA_HORIZ_ACT_LSB 0x000001ff |
79 | |
80 | #define TGA_VERT_SE 0x80000000 |
81 | #define TGA_VERT_POLARITY 0x40000000 |
82 | #define TGA_VERT_RESERVED 0x30000000 |
83 | #define TGA_VERT_BP 0x0fc00000 |
84 | #define TGA_VERT_SYNC 0x003f0000 |
85 | #define TGA_VERT_FP 0x0000f800 |
86 | #define TGA_VERT_ACTIVE 0x000007ff |
87 | |
88 | #define TGA_VALID_VIDEO 0x01 |
89 | #define TGA_VALID_BLANK 0x02 |
90 | #define TGA_VALID_CURSOR 0x04 |
91 | |
92 | #define TGA_MODE_SBM_8BPP 0x000 |
93 | #define TGA_MODE_SBM_24BPP 0x300 |
94 | |
95 | #define TGA_MODE_SIMPLE 0x00 |
96 | #define TGA_MODE_SIMPLEZ 0x10 |
97 | #define TGA_MODE_OPAQUE_STIPPLE 0x01 |
98 | #define TGA_MODE_OPAQUE_FILL 0x21 |
99 | #define TGA_MODE_TRANSPARENT_STIPPLE 0x03 |
100 | #define TGA_MODE_TRANSPARENT_FILL 0x23 |
101 | #define TGA_MODE_BLOCK_STIPPLE 0x0d |
102 | #define TGA_MODE_BLOCK_FILL 0x2d |
103 | #define TGA_MODE_COPY 0x07 |
104 | #define TGA_MODE_DMA_READ_COPY_ND 0x17 |
105 | #define TGA_MODE_DMA_READ_COPY_D 0x37 |
106 | #define TGA_MODE_DMA_WRITE_COPY 0x1f |
107 | |
108 | |
109 | /* |
110 | * Useful defines for managing the ICS1562 PLL clock |
111 | */ |
112 | |
113 | #define TGA_PLL_BASE_FREQ 14318 /* .18 */ |
114 | #define TGA_PLL_MAX_FREQ 230000 |
115 | |
116 | |
117 | /* |
118 | * Useful defines for managing the BT485 on the 8-plane TGA |
119 | */ |
120 | |
121 | #define BT485_READ_BIT 0x01 |
122 | #define BT485_WRITE_BIT 0x00 |
123 | |
124 | #define BT485_ADDR_PAL_WRITE 0x00 |
125 | #define BT485_DATA_PAL 0x02 |
126 | #define BT485_PIXEL_MASK 0x04 |
127 | #define BT485_ADDR_PAL_READ 0x06 |
128 | #define BT485_ADDR_CUR_WRITE 0x08 |
129 | #define BT485_DATA_CUR 0x0a |
130 | #define BT485_CMD_0 0x0c |
131 | #define BT485_ADDR_CUR_READ 0x0e |
132 | #define BT485_CMD_1 0x10 |
133 | #define BT485_CMD_2 0x12 |
134 | #define BT485_STATUS 0x14 |
135 | #define BT485_CMD_3 0x14 |
136 | #define BT485_CUR_RAM 0x16 |
137 | #define BT485_CUR_LOW_X 0x18 |
138 | #define BT485_CUR_HIGH_X 0x1a |
139 | #define BT485_CUR_LOW_Y 0x1c |
140 | #define BT485_CUR_HIGH_Y 0x1e |
141 | |
142 | |
143 | /* |
144 | * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s |
145 | */ |
146 | |
147 | #define BT463_ADDR_LO 0x0 |
148 | #define BT463_ADDR_HI 0x1 |
149 | #define BT463_REG_ACC 0x2 |
150 | #define BT463_PALETTE 0x3 |
151 | |
152 | #define BT463_CUR_CLR_0 0x0100 |
153 | #define BT463_CUR_CLR_1 0x0101 |
154 | |
155 | #define BT463_CMD_REG_0 0x0201 |
156 | #define BT463_CMD_REG_1 0x0202 |
157 | #define BT463_CMD_REG_2 0x0203 |
158 | |
159 | #define BT463_READ_MASK_0 0x0205 |
160 | #define BT463_READ_MASK_1 0x0206 |
161 | #define BT463_READ_MASK_2 0x0207 |
162 | #define BT463_READ_MASK_3 0x0208 |
163 | |
164 | #define BT463_BLINK_MASK_0 0x0209 |
165 | #define BT463_BLINK_MASK_1 0x020a |
166 | #define BT463_BLINK_MASK_2 0x020b |
167 | #define BT463_BLINK_MASK_3 0x020c |
168 | |
169 | #define BT463_WINDOW_TYPE_BASE 0x0300 |
170 | |
171 | /* |
172 | * Useful defines for managing the BT459 on the 8-plane SFB+s |
173 | */ |
174 | |
175 | #define BT459_ADDR_LO 0x0 |
176 | #define BT459_ADDR_HI 0x1 |
177 | #define BT459_REG_ACC 0x2 |
178 | #define BT459_PALETTE 0x3 |
179 | |
180 | #define BT459_CUR_CLR_1 0x0181 |
181 | #define BT459_CUR_CLR_2 0x0182 |
182 | #define BT459_CUR_CLR_3 0x0183 |
183 | |
184 | #define BT459_CMD_REG_0 0x0201 |
185 | #define BT459_CMD_REG_1 0x0202 |
186 | #define BT459_CMD_REG_2 0x0203 |
187 | |
188 | #define BT459_READ_MASK 0x0204 |
189 | |
190 | #define BT459_BLINK_MASK 0x0206 |
191 | |
192 | #define BT459_CUR_CMD_REG 0x0300 |
193 | |
194 | /* |
195 | * The framebuffer driver private data. |
196 | */ |
197 | |
198 | struct tga_par { |
199 | /* PCI/TC device. */ |
200 | struct device *dev; |
201 | |
202 | /* Device dependent information. */ |
203 | void __iomem *tga_mem_base; |
204 | void __iomem *tga_fb_base; |
205 | void __iomem *tga_regs_base; |
206 | u8 tga_type; /* TGA_TYPE_XXX */ |
207 | u8 tga_chip_rev; /* dc21030 revision */ |
208 | |
209 | /* Remember blank mode. */ |
210 | u8 vesa_blanked; |
211 | |
212 | /* Define the video mode. */ |
213 | u32 xres, yres; /* resolution in pixels */ |
214 | u32 htimings; /* horizontal timing register */ |
215 | u32 vtimings; /* vertical timing register */ |
216 | u32 pll_freq; /* pixclock in mhz */ |
217 | u32 bits_per_pixel; /* bits per pixel */ |
218 | u32 sync_on_green; /* set if sync is on green */ |
219 | u32 palette[16]; |
220 | }; |
221 | |
222 | |
223 | /* |
224 | * Macros for reading/writing TGA and RAMDAC registers |
225 | */ |
226 | |
227 | static inline void |
228 | TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r) |
229 | { |
230 | writel(val: v, addr: par->tga_regs_base +r); |
231 | } |
232 | |
233 | static inline u32 |
234 | TGA_READ_REG(struct tga_par *par, u32 r) |
235 | { |
236 | return readl(addr: par->tga_regs_base +r); |
237 | } |
238 | |
239 | static inline void |
240 | BT485_WRITE(struct tga_par *par, u8 v, u8 r) |
241 | { |
242 | TGA_WRITE_REG(par, v: r, TGA_RAMDAC_SETUP_REG); |
243 | TGA_WRITE_REG(par, v: v | (r << 8), TGA_RAMDAC_REG); |
244 | } |
245 | |
246 | static inline void |
247 | BT463_LOAD_ADDR(struct tga_par *par, u16 a) |
248 | { |
249 | TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG); |
250 | TGA_WRITE_REG(par, v: (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG); |
251 | TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG); |
252 | TGA_WRITE_REG(par, v: (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG); |
253 | } |
254 | |
255 | static inline void |
256 | BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v) |
257 | { |
258 | BT463_LOAD_ADDR(par, a); |
259 | TGA_WRITE_REG(par, v: m << 2, TGA_RAMDAC_SETUP_REG); |
260 | TGA_WRITE_REG(par, v: m << 10 | v, TGA_RAMDAC_REG); |
261 | } |
262 | |
263 | static inline void |
264 | BT459_LOAD_ADDR(struct tga_par *par, u16 a) |
265 | { |
266 | TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG); |
267 | TGA_WRITE_REG(par, v: a & 0xff, TGA_RAMDAC_REG); |
268 | TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG); |
269 | TGA_WRITE_REG(par, v: a >> 8, TGA_RAMDAC_REG); |
270 | } |
271 | |
272 | static inline void |
273 | BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v) |
274 | { |
275 | BT459_LOAD_ADDR(par, a); |
276 | TGA_WRITE_REG(par, v: m << 2, TGA_RAMDAC_SETUP_REG); |
277 | TGA_WRITE_REG(par, v, TGA_RAMDAC_REG); |
278 | } |
279 | |
280 | #endif /* TGAFB_H */ |
281 | |