| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ASM_ARCH_REGS_AC97_H |
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| 3 | #define __ASM_ARCH_REGS_AC97_H |
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| 4 | |
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| 5 | /* |
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| 6 | * AC97 Controller registers |
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| 7 | */ |
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| 8 | |
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| 9 | #define POCR (0x0000) /* PCM Out Control Register */ |
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| 10 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
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| 11 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
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| 12 | |
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| 13 | #define PICR (0x0004) /* PCM In Control Register */ |
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| 14 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
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| 15 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
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| 16 | |
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| 17 | #define MCCR (0x0008) /* Mic In Control Register */ |
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| 18 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ |
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| 19 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
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| 20 | |
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| 21 | #define GCR (0x000C) /* Global Control Register */ |
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| 22 | #ifdef CONFIG_PXA3xx |
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| 23 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ |
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| 24 | #endif |
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| 25 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ |
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| 26 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ |
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| 27 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ |
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| 28 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ |
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| 29 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ |
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| 30 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ |
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| 31 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ |
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| 32 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ |
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| 33 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ |
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| 34 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ |
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| 35 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ |
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| 36 | |
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| 37 | #define POSR (0x0010) /* PCM Out Status Register */ |
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| 38 | #define POSR_FIFOE (1 << 4) /* FIFO error */ |
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| 39 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ |
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| 40 | |
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| 41 | #define PISR (0x0014) /* PCM In Status Register */ |
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| 42 | #define PISR_FIFOE (1 << 4) /* FIFO error */ |
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| 43 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
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| 44 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ |
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| 45 | |
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| 46 | #define MCSR (0x0018) /* Mic In Status Register */ |
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| 47 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ |
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| 48 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
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| 49 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ |
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| 50 | |
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| 51 | #define GSR (0x001C) /* Global Status Register */ |
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| 52 | #define GSR_CDONE (1 << 19) /* Command Done */ |
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| 53 | #define GSR_SDONE (1 << 18) /* Status Done */ |
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| 54 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ |
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| 55 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ |
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| 56 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ |
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| 57 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ |
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| 58 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ |
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| 59 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ |
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| 60 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ |
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| 61 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ |
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| 62 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ |
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| 63 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ |
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| 64 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ |
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| 65 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ |
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| 66 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ |
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| 67 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ |
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| 68 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ |
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| 69 | |
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| 70 | #define CAR (0x0020) /* CODEC Access Register */ |
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| 71 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ |
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| 72 | |
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| 73 | #define PCDR (0x0040) /* PCM FIFO Data Register */ |
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| 74 | #define MCDR (0x0060) /* Mic-in FIFO Data Register */ |
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| 75 | |
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| 76 | #define MOCR (0x0100) /* Modem Out Control Register */ |
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| 77 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ |
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| 78 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
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| 79 | |
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| 80 | #define MICR (0x0108) /* Modem In Control Register */ |
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| 81 | #define MICR_FEIE (1 << 3) /* FIFO Error */ |
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| 82 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ |
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| 83 | |
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| 84 | #define MOSR (0x0110) /* Modem Out Status Register */ |
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| 85 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ |
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| 86 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ |
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| 87 | |
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| 88 | #define MISR (0x0118) /* Modem In Status Register */ |
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| 89 | #define MISR_FIFOE (1 << 4) /* FIFO error */ |
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| 90 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ |
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| 91 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ |
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| 92 | |
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| 93 | #define MODR (0x0140) /* Modem FIFO Data Register */ |
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| 94 | |
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| 95 | #define PAC_REG_BASE (0x0200) /* Primary Audio Codec */ |
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| 96 | #define SAC_REG_BASE (0x0300) /* Secondary Audio Codec */ |
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| 97 | #define PMC_REG_BASE (0x0400) /* Primary Modem Codec */ |
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| 98 | #define SMC_REG_BASE (0x0500) /* Secondary Modem Codec */ |
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| 99 | |
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| 100 | #endif /* __ASM_ARCH_REGS_AC97_H */ |
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| 101 | |
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