| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED |
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| 3 | #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED |
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| 4 | |
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| 5 | /* |
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| 6 | * DICE device interface definitions |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Generally, all registers can be read like memory, i.e., with quadlet read or |
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| 11 | * block read transactions with at least quadlet-aligned offset and length. |
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| 12 | * Writes are not allowed except where noted; quadlet-sized registers must be |
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| 13 | * written with a quadlet write transaction. |
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| 14 | * |
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| 15 | * All values are in big endian. The DICE firmware runs on a little-endian CPU |
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| 16 | * and just byte-swaps _all_ quadlets on the bus, so values without endianness |
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| 17 | * (e.g. strings) get scrambled and must be byte-swapped again by the driver. |
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| 18 | */ |
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| 19 | |
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| 20 | /* |
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| 21 | * Streaming is handled by the "DICE driver" interface. Its registers are |
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| 22 | * located in this private address space. |
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| 23 | */ |
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| 24 | #define DICE_PRIVATE_SPACE 0xffffe0000000uLL |
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| 25 | |
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| 26 | /* |
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| 27 | * The registers are organized in several sections, which are organized |
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| 28 | * separately to allow them to be extended individually. Whether a register is |
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| 29 | * supported can be detected by checking its offset against its section's size. |
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| 30 | * |
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| 31 | * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/ |
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| 32 | * size values are measured in quadlets. Read-only. |
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| 33 | */ |
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| 34 | #define DICE_GLOBAL_OFFSET 0x00 |
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| 35 | #define DICE_GLOBAL_SIZE 0x04 |
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| 36 | #define DICE_TX_OFFSET 0x08 |
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| 37 | #define DICE_TX_SIZE 0x0c |
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| 38 | #define DICE_RX_OFFSET 0x10 |
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| 39 | #define DICE_RX_SIZE 0x14 |
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| 40 | #define DICE_EXT_SYNC_OFFSET 0x18 |
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| 41 | #define DICE_EXT_SYNC_SIZE 0x1c |
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| 42 | #define DICE_UNUSED2_OFFSET 0x20 |
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| 43 | #define DICE_UNUSED2_SIZE 0x24 |
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| 44 | |
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| 45 | /* |
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| 46 | * Global settings. |
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| 47 | */ |
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| 48 | |
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| 49 | /* |
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| 50 | * Stores the full 64-bit address (node ID and offset in the node's address |
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| 51 | * space) where the device will send notifications. Must be changed with |
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| 52 | * a compare/swap transaction by the owner. This register is automatically |
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| 53 | * cleared on a bus reset. |
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| 54 | */ |
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| 55 | #define GLOBAL_OWNER 0x000 |
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| 56 | #define OWNER_NO_OWNER 0xffff000000000000uLL |
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| 57 | #define OWNER_NODE_SHIFT 48 |
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| 58 | |
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| 59 | /* |
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| 60 | * A bitmask with asynchronous events; read-only. When any event(s) happen, |
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| 61 | * the bits of previous events are cleared, and the value of this register is |
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| 62 | * also written to the address stored in the owner register. |
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| 63 | */ |
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| 64 | #define GLOBAL_NOTIFICATION 0x008 |
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| 65 | /* Some registers in the Rx/Tx sections may have changed. */ |
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| 66 | #define NOTIFY_RX_CFG_CHG 0x00000001 |
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| 67 | #define NOTIFY_TX_CFG_CHG 0x00000002 |
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| 68 | /* Lock status of the current clock source may have changed. */ |
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| 69 | #define NOTIFY_LOCK_CHG 0x00000010 |
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| 70 | /* Write to the clock select register has been finished. */ |
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| 71 | #define NOTIFY_CLOCK_ACCEPTED 0x00000020 |
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| 72 | /* Lock status of some clock source has changed. */ |
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| 73 | #define NOTIFY_EXT_STATUS 0x00000040 |
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| 74 | /* Other bits may be used for device-specific events. */ |
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| 75 | |
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| 76 | /* |
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| 77 | * A name that can be customized for each device; read/write. Padded with zero |
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| 78 | * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver |
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| 79 | * happens to be using. |
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| 80 | */ |
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| 81 | #define GLOBAL_NICK_NAME 0x00c |
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| 82 | #define NICK_NAME_SIZE 64 |
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| 83 | |
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| 84 | /* |
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| 85 | * The current sample rate and clock source; read/write. Whether a clock |
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| 86 | * source or sample rate is supported is device-specific; the internal clock |
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| 87 | * source is always available. Low/mid/high = up to 48/96/192 kHz. This |
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| 88 | * register can be changed even while streams are running. |
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| 89 | */ |
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| 90 | #define GLOBAL_CLOCK_SELECT 0x04c |
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| 91 | #define CLOCK_SOURCE_MASK 0x000000ff |
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| 92 | #define CLOCK_SOURCE_AES1 0x00000000 |
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| 93 | #define CLOCK_SOURCE_AES2 0x00000001 |
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| 94 | #define CLOCK_SOURCE_AES3 0x00000002 |
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| 95 | #define CLOCK_SOURCE_AES4 0x00000003 |
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| 96 | #define CLOCK_SOURCE_AES_ANY 0x00000004 |
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| 97 | #define CLOCK_SOURCE_ADAT 0x00000005 |
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| 98 | #define CLOCK_SOURCE_TDIF 0x00000006 |
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| 99 | #define CLOCK_SOURCE_WC 0x00000007 |
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| 100 | #define CLOCK_SOURCE_ARX1 0x00000008 |
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| 101 | #define CLOCK_SOURCE_ARX2 0x00000009 |
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| 102 | #define CLOCK_SOURCE_ARX3 0x0000000a |
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| 103 | #define CLOCK_SOURCE_ARX4 0x0000000b |
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| 104 | #define CLOCK_SOURCE_INTERNAL 0x0000000c |
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| 105 | #define CLOCK_RATE_MASK 0x0000ff00 |
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| 106 | #define CLOCK_RATE_32000 0x00000000 |
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| 107 | #define CLOCK_RATE_44100 0x00000100 |
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| 108 | #define CLOCK_RATE_48000 0x00000200 |
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| 109 | #define CLOCK_RATE_88200 0x00000300 |
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| 110 | #define CLOCK_RATE_96000 0x00000400 |
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| 111 | #define CLOCK_RATE_176400 0x00000500 |
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| 112 | #define CLOCK_RATE_192000 0x00000600 |
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| 113 | #define CLOCK_RATE_ANY_LOW 0x00000700 |
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| 114 | #define CLOCK_RATE_ANY_MID 0x00000800 |
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| 115 | #define CLOCK_RATE_ANY_HIGH 0x00000900 |
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| 116 | #define CLOCK_RATE_NONE 0x00000a00 |
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| 117 | #define CLOCK_RATE_SHIFT 8 |
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| 118 | |
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| 119 | /* |
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| 120 | * Enable streaming; read/write. Writing a non-zero value (re)starts all |
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| 121 | * streams that have a valid iso channel set; zero stops all streams. The |
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| 122 | * streams' parameters must be configured before starting. This register is |
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| 123 | * automatically cleared on a bus reset. |
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| 124 | */ |
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| 125 | #define GLOBAL_ENABLE 0x050 |
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| 126 | |
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| 127 | /* |
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| 128 | * Status of the sample clock; read-only. |
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| 129 | */ |
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| 130 | #define GLOBAL_STATUS 0x054 |
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| 131 | /* The current clock source is locked. */ |
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| 132 | #define STATUS_SOURCE_LOCKED 0x00000001 |
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| 133 | /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */ |
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| 134 | #define STATUS_NOMINAL_RATE_MASK 0x0000ff00 |
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| 135 | |
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| 136 | /* |
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| 137 | * Status of all clock sources; read-only. |
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| 138 | */ |
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| 139 | #define GLOBAL_EXTENDED_STATUS 0x058 |
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| 140 | /* |
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| 141 | * The _LOCKED bits always show the current status; any change generates |
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| 142 | * a notification. |
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| 143 | */ |
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| 144 | #define EXT_STATUS_AES1_LOCKED 0x00000001 |
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| 145 | #define EXT_STATUS_AES2_LOCKED 0x00000002 |
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| 146 | #define EXT_STATUS_AES3_LOCKED 0x00000004 |
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| 147 | #define EXT_STATUS_AES4_LOCKED 0x00000008 |
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| 148 | #define EXT_STATUS_ADAT_LOCKED 0x00000010 |
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| 149 | #define EXT_STATUS_TDIF_LOCKED 0x00000020 |
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| 150 | #define EXT_STATUS_ARX1_LOCKED 0x00000040 |
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| 151 | #define EXT_STATUS_ARX2_LOCKED 0x00000080 |
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| 152 | #define EXT_STATUS_ARX3_LOCKED 0x00000100 |
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| 153 | #define EXT_STATUS_ARX4_LOCKED 0x00000200 |
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| 154 | #define EXT_STATUS_WC_LOCKED 0x00000400 |
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| 155 | /* |
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| 156 | * The _SLIP bits do not generate notifications; a set bit indicates that an |
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| 157 | * error occurred since the last time when this register was read with |
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| 158 | * a quadlet read transaction. |
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| 159 | */ |
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| 160 | #define EXT_STATUS_AES1_SLIP 0x00010000 |
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| 161 | #define EXT_STATUS_AES2_SLIP 0x00020000 |
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| 162 | #define EXT_STATUS_AES3_SLIP 0x00040000 |
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| 163 | #define EXT_STATUS_AES4_SLIP 0x00080000 |
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| 164 | #define EXT_STATUS_ADAT_SLIP 0x00100000 |
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| 165 | #define EXT_STATUS_TDIF_SLIP 0x00200000 |
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| 166 | #define EXT_STATUS_ARX1_SLIP 0x00400000 |
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| 167 | #define EXT_STATUS_ARX2_SLIP 0x00800000 |
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| 168 | #define EXT_STATUS_ARX3_SLIP 0x01000000 |
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| 169 | #define EXT_STATUS_ARX4_SLIP 0x02000000 |
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| 170 | #define EXT_STATUS_WC_SLIP 0x04000000 |
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| 171 | |
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| 172 | /* |
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| 173 | * The measured rate of the current clock source, in Hz; read-only. |
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| 174 | */ |
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| 175 | #define GLOBAL_SAMPLE_RATE 0x05c |
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| 176 | |
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| 177 | /* |
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| 178 | * Some old firmware versions do not have the following global registers. |
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| 179 | * Windows drivers produced by TCAT lost backward compatibility in its |
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| 180 | * early release because they can handle firmware only which supports the |
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| 181 | * following registers. |
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| 182 | */ |
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| 183 | |
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| 184 | /* |
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| 185 | * The version of the DICE driver specification that this device conforms to; |
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| 186 | * read-only. |
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| 187 | */ |
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| 188 | #define GLOBAL_VERSION 0x060 |
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| 189 | |
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| 190 | /* |
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| 191 | * Supported sample rates and clock sources; read-only. |
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| 192 | */ |
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| 193 | #define GLOBAL_CLOCK_CAPABILITIES 0x064 |
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| 194 | #define CLOCK_CAP_RATE_32000 0x00000001 |
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| 195 | #define CLOCK_CAP_RATE_44100 0x00000002 |
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| 196 | #define CLOCK_CAP_RATE_48000 0x00000004 |
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| 197 | #define CLOCK_CAP_RATE_88200 0x00000008 |
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| 198 | #define CLOCK_CAP_RATE_96000 0x00000010 |
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| 199 | #define CLOCK_CAP_RATE_176400 0x00000020 |
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| 200 | #define CLOCK_CAP_RATE_192000 0x00000040 |
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| 201 | #define CLOCK_CAP_SOURCE_AES1 0x00010000 |
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| 202 | #define CLOCK_CAP_SOURCE_AES2 0x00020000 |
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| 203 | #define CLOCK_CAP_SOURCE_AES3 0x00040000 |
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| 204 | #define CLOCK_CAP_SOURCE_AES4 0x00080000 |
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| 205 | #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000 |
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| 206 | #define CLOCK_CAP_SOURCE_ADAT 0x00200000 |
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| 207 | #define CLOCK_CAP_SOURCE_TDIF 0x00400000 |
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| 208 | #define CLOCK_CAP_SOURCE_WC 0x00800000 |
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| 209 | #define CLOCK_CAP_SOURCE_ARX1 0x01000000 |
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| 210 | #define CLOCK_CAP_SOURCE_ARX2 0x02000000 |
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| 211 | #define CLOCK_CAP_SOURCE_ARX3 0x04000000 |
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| 212 | #define CLOCK_CAP_SOURCE_ARX4 0x08000000 |
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| 213 | #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000 |
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| 214 | |
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| 215 | /* |
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| 216 | * Names of all clock sources; read-only. Quadlets are byte-swapped. Names |
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| 217 | * are separated with one backslash, the list is terminated with two |
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| 218 | * backslashes. Unused clock sources are included. |
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| 219 | */ |
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| 220 | #define GLOBAL_CLOCK_SOURCE_NAMES 0x068 |
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| 221 | #define CLOCK_SOURCE_NAMES_SIZE 256 |
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| 222 | |
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| 223 | /* |
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| 224 | * Capture stream settings. This section includes the number/size registers |
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| 225 | * and the registers of all streams. |
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| 226 | */ |
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| 227 | |
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| 228 | /* |
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| 229 | * The number of supported capture streams; read-only. |
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| 230 | */ |
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| 231 | #define TX_NUMBER 0x000 |
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| 232 | |
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| 233 | /* |
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| 234 | * The size of one stream's register block, in quadlets; read-only. The |
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| 235 | * registers of the first stream follow immediately afterwards; the registers |
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| 236 | * of the following streams are offset by this register's value. |
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| 237 | */ |
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| 238 | #define TX_SIZE 0x004 |
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| 239 | |
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| 240 | /* |
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| 241 | * The isochronous channel number on which packets are sent, or -1 if the |
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| 242 | * stream is not to be used; read/write. |
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| 243 | */ |
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| 244 | #define TX_ISOCHRONOUS 0x008 |
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| 245 | |
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| 246 | /* |
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| 247 | * The number of audio channels; read-only. There will be one quadlet per |
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| 248 | * channel; the first channel is the first quadlet in a data block. |
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| 249 | */ |
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| 250 | #define TX_NUMBER_AUDIO 0x00c |
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| 251 | |
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| 252 | /* |
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| 253 | * The number of MIDI ports, 0-8; read-only. If > 0, there will be one |
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| 254 | * additional quadlet in each data block, following the audio quadlets. |
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| 255 | */ |
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| 256 | #define TX_NUMBER_MIDI 0x010 |
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| 257 | |
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| 258 | /* |
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| 259 | * The speed at which the packets are sent, SCODE_100-_400; read/write. |
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| 260 | * SCODE_800 is only available in Dice III. |
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| 261 | */ |
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| 262 | #define TX_SPEED 0x014 |
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| 263 | |
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| 264 | /* |
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| 265 | * Names of all audio channels; read-only. Quadlets are byte-swapped. Names |
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| 266 | * are separated with one backslash, the list is terminated with two |
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| 267 | * backslashes. |
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| 268 | */ |
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| 269 | #define TX_NAMES 0x018 |
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| 270 | #define TX_NAMES_SIZE 256 |
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| 271 | |
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| 272 | /* |
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| 273 | * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio |
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| 274 | * channel. |
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| 275 | */ |
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| 276 | #define TX_AC3_CAPABILITIES 0x118 |
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| 277 | |
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| 278 | /* |
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| 279 | * Send audio data with IEC60958 label; read/write. Bitmask with one bit per |
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| 280 | * audio channel. This register can be changed even while the stream is |
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| 281 | * running. |
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| 282 | */ |
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| 283 | #define TX_AC3_ENABLE 0x11c |
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| 284 | |
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| 285 | /* |
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| 286 | * Playback stream settings. This section includes the number/size registers |
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| 287 | * and the registers of all streams. |
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| 288 | */ |
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| 289 | |
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| 290 | /* |
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| 291 | * The number of supported playback streams; read-only. |
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| 292 | */ |
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| 293 | #define RX_NUMBER 0x000 |
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| 294 | |
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| 295 | /* |
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| 296 | * The size of one stream's register block, in quadlets; read-only. The |
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| 297 | * registers of the first stream follow immediately afterwards; the registers |
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| 298 | * of the following streams are offset by this register's value. |
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| 299 | */ |
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| 300 | #define RX_SIZE 0x004 |
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| 301 | |
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| 302 | /* |
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| 303 | * The isochronous channel number on which packets are received, or -1 if the |
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| 304 | * stream is not to be used; read/write. |
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| 305 | */ |
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| 306 | #define RX_ISOCHRONOUS 0x008 |
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| 307 | |
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| 308 | /* |
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| 309 | * Index of first quadlet to be interpreted; read/write. If > 0, that many |
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| 310 | * quadlets at the beginning of each data block will be ignored, and all the |
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| 311 | * audio and MIDI quadlets will follow. |
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| 312 | */ |
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| 313 | #define RX_SEQ_START 0x00c |
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| 314 | |
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| 315 | /* |
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| 316 | * The number of audio channels; read-only. There will be one quadlet per |
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| 317 | * channel. |
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| 318 | */ |
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| 319 | #define RX_NUMBER_AUDIO 0x010 |
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| 320 | |
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| 321 | /* |
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| 322 | * The number of MIDI ports, 0-8; read-only. If > 0, there will be one |
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| 323 | * additional quadlet in each data block, following the audio quadlets. |
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| 324 | */ |
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| 325 | #define RX_NUMBER_MIDI 0x014 |
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| 326 | |
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| 327 | /* |
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| 328 | * Names of all audio channels; read-only. Quadlets are byte-swapped. Names |
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| 329 | * are separated with one backslash, the list is terminated with two |
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| 330 | * backslashes. |
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| 331 | */ |
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| 332 | #define RX_NAMES 0x018 |
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| 333 | #define RX_NAMES_SIZE 256 |
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| 334 | |
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| 335 | /* |
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| 336 | * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio |
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| 337 | * channel. |
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| 338 | */ |
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| 339 | #define RX_AC3_CAPABILITIES 0x118 |
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| 340 | |
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| 341 | /* |
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| 342 | * Receive audio data with IEC60958 label; read/write. Bitmask with one bit |
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| 343 | * per audio channel. This register can be changed even while the stream is |
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| 344 | * running. |
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| 345 | */ |
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| 346 | #define RX_AC3_ENABLE 0x11c |
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| 347 | |
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| 348 | /* |
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| 349 | * Extended synchronization information. |
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| 350 | * This section can be read completely with a block read request. |
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| 351 | */ |
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| 352 | |
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| 353 | /* |
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| 354 | * Current clock source; read-only. |
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| 355 | */ |
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| 356 | #define EXT_SYNC_CLOCK_SOURCE 0x000 |
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| 357 | |
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| 358 | /* |
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| 359 | * Clock source is locked (boolean); read-only. |
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| 360 | */ |
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| 361 | #define EXT_SYNC_LOCKED 0x004 |
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| 362 | |
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| 363 | /* |
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| 364 | * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or |
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| 365 | * _NONE; read-only. |
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| 366 | */ |
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| 367 | #define EXT_SYNC_RATE 0x008 |
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| 368 | |
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| 369 | /* |
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| 370 | * ADAT user data bits; read-only. |
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| 371 | */ |
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| 372 | #define EXT_SYNC_ADAT_USER_DATA 0x00c |
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| 373 | /* The data bits, if available. */ |
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| 374 | #define ADAT_USER_DATA_MASK 0x0f |
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| 375 | /* The data bits are not available. */ |
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| 376 | #define ADAT_USER_DATA_NO_DATA 0x10 |
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| 377 | |
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| 378 | #endif |
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| 379 | |
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