| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | Aureal Vortex Soundcard driver. |
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| 4 | |
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| 5 | IO addr collected from asp4core.vxd: |
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| 6 | function address |
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| 7 | 0005D5A0 13004 |
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| 8 | 00080674 14004 |
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| 9 | 00080AFF 12818 |
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| 10 | |
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| 11 | */ |
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| 12 | |
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| 13 | #define CHIP_AU8820 |
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| 14 | |
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| 15 | #define CARD_NAME "Aureal Vortex" |
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| 16 | #define CARD_NAME_SHORT "au8820" |
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| 17 | |
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| 18 | /* Number of ADB and WT channels */ |
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| 19 | #define NR_ADB 0x10 |
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| 20 | #define NR_WT 0x20 |
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| 21 | #define NR_SRC 0x10 |
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| 22 | #define NR_A3D 0x00 |
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| 23 | #define NR_MIXIN 0x10 |
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| 24 | #define NR_MIXOUT 0x10 |
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| 25 | |
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| 26 | |
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| 27 | /* ADBDMA */ |
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| 28 | #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */ |
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| 29 | #define POS_MASK 0x00000fff |
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| 30 | #define POS_SHIFT 0x0 |
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| 31 | #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ |
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| 32 | #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ |
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| 33 | #define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */ |
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| 34 | #define OFFSET_MASK 0x00000fff |
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| 35 | #define OFFSET_SHIFT 0x0 |
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| 36 | #define IE_MASK 0x00001000 /* interrupt enable. */ |
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| 37 | #define IE_SHIFT 0xc |
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| 38 | #define DIR_MASK 0x00002000 /* Direction. */ |
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| 39 | #define DIR_SHIFT 0xd |
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| 40 | #define FMT_MASK 0x0003c000 |
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| 41 | #define FMT_SHIFT 0xe |
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| 42 | // The masks and shift also work for the wtdma, if not specified otherwise. |
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| 43 | #define VORTEX_ADBDMA_BUFCFG0 0x10400 |
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| 44 | #define VORTEX_ADBDMA_BUFCFG1 0x10404 |
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| 45 | #define VORTEX_ADBDMA_BUFBASE 0x10200 |
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| 46 | #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ |
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| 47 | #define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */ |
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| 48 | |
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| 49 | /* ADB */ |
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| 50 | #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ |
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| 51 | #define VORTEX_ADB_RTBASE 0x10800 |
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| 52 | #define VORTEX_ADB_RTBASE_COUNT 103 |
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| 53 | #define VORTEX_ADB_CHNBASE 0x1099c |
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| 54 | #define VORTEX_ADB_CHNBASE_COUNT 22 |
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| 55 | #define ROUTE_MASK 0x3fff |
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| 56 | #define ADB_MASK 0x7f |
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| 57 | #define ADB_SHIFT 0x7 |
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| 58 | //#define ADB_MIX_MASK 0xf |
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| 59 | /* ADB address */ |
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| 60 | #define OFFSET_ADBDMA 0x00 |
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| 61 | #define OFFSET_SRCOUT 0x10 /* on channel 0x11 */ |
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| 62 | #define OFFSET_SRCIN 0x10 /* on channel < 0x11 */ |
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| 63 | #define OFFSET_MIXOUT 0x20 /* source */ |
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| 64 | #define OFFSET_MIXIN 0x30 /* sink */ |
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| 65 | #define OFFSET_CODECIN 0x48 /* ADB source */ |
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| 66 | #define OFFSET_CODECOUT 0x58 /* ADB sink/target */ |
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| 67 | #define OFFSET_SPORTOUT 0x60 /* sink */ |
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| 68 | #define OFFSET_SPORTIN 0x50 /* source */ |
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| 69 | #define OFFSET_EFXOUT 0x50 /* sink */ |
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| 70 | #define OFFSET_EFXIN 0x40 /* source */ |
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| 71 | #define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */ |
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| 72 | #define OFFSET_A3DIN 0x00 |
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| 73 | #define OFFSET_WTOUT 0x58 /* */ |
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| 74 | |
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| 75 | /* ADB route translate helper */ |
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| 76 | #define ADB_DMA(x) (x + OFFSET_ADBDMA) |
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| 77 | #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) |
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| 78 | #define ADB_SRCIN(x) (x + OFFSET_SRCIN) |
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| 79 | #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) |
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| 80 | #define ADB_MIXIN(x) (x + OFFSET_MIXIN) |
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| 81 | #define ADB_CODECIN(x) (x + OFFSET_CODECIN) |
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| 82 | #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) |
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| 83 | #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) |
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| 84 | #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */ |
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| 85 | #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ |
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| 86 | #define ADB_A3DIN(x) (x + OFFSET_A3DIN) |
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| 87 | #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT) |
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| 88 | |
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| 89 | /* WTDMA */ |
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| 90 | #define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ |
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| 91 | #define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ |
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| 92 | #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT) |
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| 93 | #define WT_SUBBUF_SHIFT 0x15 |
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| 94 | #define VORTEX_WTDMA_BUFBASE 0x10000 |
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| 95 | #define VORTEX_WTDMA_BUFCFG0 0x10300 |
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| 96 | #define VORTEX_WTDMA_BUFCFG1 0x10304 |
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| 97 | #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ |
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| 98 | |
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| 99 | #define VORTEX_WT_BASE 0x9000 |
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| 100 | |
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| 101 | /* MIXER */ |
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| 102 | #define VORTEX_MIXER_SR 0x9f00 |
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| 103 | #define VORTEX_MIXER_CLIP 0x9f80 |
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| 104 | #define VORTEX_MIXER_CHNBASE 0x9e40 |
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| 105 | #define VORTEX_MIXER_RTBASE 0x9e00 |
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| 106 | #define MIXER_RTBASE_SIZE 0x26 |
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| 107 | #define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */ |
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| 108 | #define VORTEX_MIX_SMP 0x9c00 |
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| 109 | |
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| 110 | /* MIX */ |
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| 111 | #define VORTEX_MIX_INVOL_A 0x9000 /* in? */ |
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| 112 | #define VORTEX_MIX_INVOL_B 0x8000 /* out? */ |
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| 113 | #define VORTEX_MIX_VOL_A 0x9800 |
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| 114 | #define VORTEX_MIX_VOL_B 0x8800 |
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| 115 | |
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| 116 | #define VOL_MIN 0x80 /* Input volume when muted. */ |
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| 117 | #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ |
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| 118 | |
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| 119 | //#define MIX_OUTL 0xe |
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| 120 | //#define MIX_OUTR 0xf |
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| 121 | //#define MIX_INL 0xe |
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| 122 | //#define MIX_INR 0xf |
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| 123 | #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */ |
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| 124 | #define MIX_DEFOGAIN 0x08 |
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| 125 | |
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| 126 | /* SRC */ |
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| 127 | #define VORTEX_SRCBLOCK_SR 0xccc0 |
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| 128 | #define VORTEX_SRC_CHNBASE 0xcc40 |
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| 129 | #define VORTEX_SRC_RTBASE 0xcc00 |
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| 130 | #define VORTEX_SRC_SOURCE 0xccc4 |
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| 131 | #define VORTEX_SRC_SOURCESIZE 0xccc8 |
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| 132 | #define VORTEX_SRC_U0 0xce00 |
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| 133 | #define VORTEX_SRC_DRIFT0 0xce80 |
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| 134 | #define VORTEX_SRC_DRIFT1 0xcec0 |
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| 135 | #define VORTEX_SRC_U1 0xcf00 |
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| 136 | #define VORTEX_SRC_DRIFT2 0xcf40 |
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| 137 | #define VORTEX_SRC_U2 0xcf80 |
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| 138 | #define VORTEX_SRC_DATA 0xc800 |
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| 139 | #define VORTEX_SRC_DATA0 0xc000 |
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| 140 | #define VORTEX_SRC_CONVRATIO 0xce40 |
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| 141 | //#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ |
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| 142 | //#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ |
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| 143 | |
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| 144 | /* FIFO */ |
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| 145 | #define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ |
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| 146 | #define VORTEX_FIFO_WTCTRL 0xf840 |
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| 147 | #define FIFO_RDONLY 0x00000001 |
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| 148 | #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ |
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| 149 | #define FIFO_VALID 0x00000010 |
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| 150 | #define FIFO_EMPTY 0x00000020 |
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| 151 | #define FIFO_U0 0x00001000 /* Unknown. */ |
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| 152 | #define FIFO_U1 0x00010000 |
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| 153 | #define FIFO_SIZE_BITS 5 |
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| 154 | #define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20 |
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| 155 | #define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */ |
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| 156 | #define VORTEX_FIFO_ADBDATA 0xe000 |
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| 157 | #define VORTEX_FIFO_WTDATA 0xe800 |
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| 158 | |
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| 159 | /* CODEC */ |
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| 160 | #define VORTEX_CODEC_CTRL 0x11984 |
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| 161 | #define VORTEX_CODEC_EN 0x11990 |
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| 162 | #define EN_CODEC 0x00000300 |
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| 163 | #define EN_SPORT 0x00030000 |
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| 164 | #define EN_SPDIF 0x000c0000 |
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| 165 | #define VORTEX_CODEC_CHN 0x11880 |
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| 166 | #define VORTEX_CODEC_IO 0x11988 |
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| 167 | |
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| 168 | #define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */ |
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| 169 | #define VORTEX_SPDIF_CFG0 0x119D0 |
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| 170 | #define VORTEX_SPDIF_CFG1 0x119D4 |
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| 171 | #define VORTEX_SPDIF_SMPRATE 0x11994 |
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| 172 | |
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| 173 | /* Sample timer */ |
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| 174 | #define VORTEX_SMP_TIME 0x11998 |
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| 175 | |
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| 176 | /* IRQ */ |
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| 177 | #define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */ |
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| 178 | #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */ |
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| 179 | |
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| 180 | #define VORTEX_STAT 0x12808 /* ?? */ |
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| 181 | |
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| 182 | #define VORTEX_CTRL 0x1280c |
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| 183 | #define CTRL_MIDI_EN 0x00000001 |
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| 184 | #define CTRL_MIDI_PORT 0x00000060 |
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| 185 | #define CTRL_GAME_EN 0x00000008 |
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| 186 | #define CTRL_GAME_PORT 0x00000e00 |
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| 187 | #define CTRL_IRQ_ENABLE 0x4000 |
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| 188 | |
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| 189 | /* write: Timer period config / read: TIMER IRQ ack. */ |
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| 190 | #define VORTEX_IRQ_STAT 0x1199c |
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| 191 | |
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| 192 | /* DMA */ |
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| 193 | #define VORTEX_DMA_BUFFER 0x10200 |
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| 194 | #define VORTEX_ENGINE_CTRL 0x1060c |
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| 195 | #define ENGINE_INIT 0x0L |
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| 196 | |
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| 197 | /* MIDI *//* GAME. */ |
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| 198 | #define VORTEX_MIDI_DATA 0x11000 |
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| 199 | #define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */ |
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| 200 | #define VORTEX_GAME_LEGACY 0x11008 |
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| 201 | #define VORTEX_CTRL2 0x1100c |
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| 202 | #define CTRL2_GAME_ADCMODE 0x40 |
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| 203 | #define VORTEX_GAME_AXIS 0x11010 |
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| 204 | #define AXIS_SIZE 4 |
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| 205 | #define AXIS_RANGE 0x1fff |
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| 206 | |
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