| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | Aureal Vortex Soundcard driver. |
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| 4 | |
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| 5 | IO addr collected from asp4core.vxd: |
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| 6 | function address |
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| 7 | 0005D5A0 13004 |
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| 8 | 00080674 14004 |
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| 9 | 00080AFF 12818 |
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| 10 | |
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| 11 | */ |
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| 12 | |
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| 13 | #define CHIP_AU8830 |
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| 14 | |
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| 15 | #define CARD_NAME "Aureal Vortex 2" |
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| 16 | #define CARD_NAME_SHORT "au8830" |
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| 17 | |
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| 18 | #define NR_ADB 0x20 |
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| 19 | #define NR_SRC 0x10 |
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| 20 | #define NR_A3D 0x10 |
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| 21 | #define NR_MIXIN 0x20 |
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| 22 | #define NR_MIXOUT 0x10 |
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| 23 | #define NR_WT 0x40 |
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| 24 | |
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| 25 | /* ADBDMA */ |
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| 26 | #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ |
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| 27 | #define POS_MASK 0x00000fff |
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| 28 | #define POS_SHIFT 0x0 |
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| 29 | #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ |
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| 30 | #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ |
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| 31 | #define VORTEX_ADBDMA_CTRL 0x27a00 /* write only; format, flags, DMA pos */ |
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| 32 | #define OFFSET_MASK 0x00000fff |
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| 33 | #define OFFSET_SHIFT 0x0 |
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| 34 | #define IE_MASK 0x00001000 /* interrupt enable. */ |
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| 35 | #define IE_SHIFT 0xc |
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| 36 | #define DIR_MASK 0x00002000 /* Direction. */ |
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| 37 | #define DIR_SHIFT 0xd |
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| 38 | #define FMT_MASK 0x0003c000 |
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| 39 | #define FMT_SHIFT 0xe |
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| 40 | #define ADB_FIFO_EN_SHIFT 0x15 |
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| 41 | #define ADB_FIFO_EN (1 << 0x15) |
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| 42 | // The ADB masks and shift also are valid for the wtdma, except if specified otherwise. |
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| 43 | #define VORTEX_ADBDMA_BUFCFG0 0x27800 |
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| 44 | #define VORTEX_ADBDMA_BUFCFG1 0x27804 |
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| 45 | #define VORTEX_ADBDMA_BUFBASE 0x27400 |
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| 46 | #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ |
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| 47 | |
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| 48 | #define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */ |
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| 49 | /* Starting at the MSB, each pair of bits seem to be the current DMA page. */ |
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| 50 | /* This current page bits are consistent (same value) with VORTEX_ADBDMA_STAT) */ |
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| 51 | |
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| 52 | /* DMA */ |
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| 53 | #define VORTEX_ENGINE_CTRL 0x27ae8 |
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| 54 | #define ENGINE_INIT 0x1380000 |
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| 55 | |
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| 56 | /* WTDMA */ |
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| 57 | #define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */ |
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| 58 | #define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */ |
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| 59 | #define WT_SUBBUF_MASK 0x3 |
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| 60 | #define WT_SUBBUF_SHIFT 0xc |
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| 61 | #define VORTEX_WTDMA_BUFBASE 0x27000 |
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| 62 | #define VORTEX_WTDMA_BUFCFG0 0x27600 |
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| 63 | #define VORTEX_WTDMA_BUFCFG1 0x27604 |
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| 64 | #define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */ |
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| 65 | |
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| 66 | /* ADB */ |
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| 67 | #define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */ |
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| 68 | #define VORTEX_ADB_RTBASE 0x28000 |
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| 69 | #define VORTEX_ADB_RTBASE_COUNT 173 |
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| 70 | #define VORTEX_ADB_CHNBASE 0x282b4 |
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| 71 | #define VORTEX_ADB_CHNBASE_COUNT 24 |
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| 72 | #define ROUTE_MASK 0xffff |
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| 73 | #define SOURCE_MASK 0xff00 |
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| 74 | #define ADB_MASK 0xff |
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| 75 | #define ADB_SHIFT 0x8 |
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| 76 | /* ADB address */ |
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| 77 | #define OFFSET_ADBDMA 0x00 |
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| 78 | #define OFFSET_ADBDMAB 0x20 |
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| 79 | #define OFFSET_SRCIN 0x40 |
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| 80 | #define OFFSET_SRCOUT 0x20 /* ch 0x11 */ |
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| 81 | #define OFFSET_MIXIN 0x50 /* ch 0x11 */ |
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| 82 | #define OFFSET_MIXOUT 0x30 /* ch 0x11 */ |
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| 83 | #define OFFSET_CODECIN 0x70 /* ch 0x11 */ /* adb source */ |
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| 84 | #define OFFSET_CODECOUT 0x88 /* ch 0x11 */ /* adb target */ |
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| 85 | #define OFFSET_SPORTIN 0x78 /* ch 0x13 ADB source. 2 routes. */ |
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| 86 | #define OFFSET_SPORTOUT 0x90 /* ch 0x13 ADB sink. 2 routes. */ |
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| 87 | #define OFFSET_SPDIFIN 0x7A /* ch 0x14 ADB source. */ |
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| 88 | #define OFFSET_SPDIFOUT 0x92 /* ch 0x14 ADB sink. */ |
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| 89 | #define OFFSET_AC98IN 0x7c /* ch 0x14 ADB source. */ |
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| 90 | #define OFFSET_AC98OUT 0x94 /* ch 0x14 ADB sink. */ |
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| 91 | #define OFFSET_EQIN 0xa0 /* ch 0x11 */ |
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| 92 | #define OFFSET_EQOUT 0x7e /* ch 0x11 */ /* 2 routes on ch 0x11 */ |
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| 93 | #define OFFSET_A3DIN 0x70 /* ADB sink. */ |
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| 94 | #define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */ |
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| 95 | #define OFFSET_WT0 0x40 /* WT bank 0 output. 0x40 - 0x65 */ |
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| 96 | #define OFFSET_WT1 0x80 /* WT bank 1 output. 0x80 - 0xA5 */ |
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| 97 | /* WT sources offset : 0x00-0x1f Direct stream. */ |
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| 98 | /* WT sources offset : 0x20-0x25 Mixed Output. */ |
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| 99 | #define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) 2 routes */ |
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| 100 | #define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink). 10 routes */ |
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| 101 | #define OFFSET_EFXOUT 0x68 /* ADB source. 8 routes. */ |
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| 102 | #define OFFSET_EFXIN 0x80 /* ADB sink. 8 routes. */ |
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| 103 | |
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| 104 | /* ADB route translate helper */ |
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| 105 | #define ADB_DMA(x) (x) |
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| 106 | #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) |
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| 107 | #define ADB_SRCIN(x) (x + OFFSET_SRCIN) |
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| 108 | #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) |
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| 109 | #define ADB_MIXIN(x) (x + OFFSET_MIXIN) |
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| 110 | #define ADB_CODECIN(x) (x + OFFSET_CODECIN) |
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| 111 | #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) |
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| 112 | #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) |
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| 113 | #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) |
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| 114 | #define ADB_SPDIFIN(x) (x + OFFSET_SPDIFIN) |
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| 115 | #define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT) |
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| 116 | #define ADB_EQIN(x) (x + OFFSET_EQIN) |
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| 117 | #define ADB_EQOUT(x) (x + OFFSET_EQOUT) |
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| 118 | #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */ |
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| 119 | #define ADB_A3DIN(x) (x + OFFSET_A3DIN) |
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| 120 | //#define ADB_WTOUT(x) ((x<x20)?(x + OFFSET_WT0):(x + OFFSET_WT1)) |
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| 121 | #define ADB_WTOUT(x,y) (((x)==0)?((y) + OFFSET_WT0):((y) + OFFSET_WT1)) |
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| 122 | #define ADB_XTALKIN(x) ((x) + OFFSET_XTALKIN) |
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| 123 | #define ADB_XTALKOUT(x) ((x) + OFFSET_XTALKOUT) |
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| 124 | |
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| 125 | #define MIX_DEFIGAIN 0x08 |
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| 126 | #define MIX_DEFOGAIN 0x08 /* 0x8->6dB (6dB = x4) 16 to 18 bit conversion? */ |
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| 127 | |
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| 128 | /* MIXER */ |
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| 129 | #define VORTEX_MIXER_SR 0x21f00 |
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| 130 | #define VORTEX_MIXER_CLIP 0x21f80 |
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| 131 | #define VORTEX_MIXER_CHNBASE 0x21e40 |
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| 132 | #define VORTEX_MIXER_RTBASE 0x21e00 |
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| 133 | #define MIXER_RTBASE_SIZE 0x38 |
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| 134 | #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ |
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| 135 | #define VORTEX_MIX_SMP 0x21c00 /* wave data buffers. AU8820: 0x9c00 */ |
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| 136 | |
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| 137 | /* MIX */ |
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| 138 | #define VORTEX_MIX_INVOL_B 0x20000 /* Input volume current */ |
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| 139 | #define VORTEX_MIX_VOL_B 0x20800 /* Output Volume current */ |
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| 140 | #define VORTEX_MIX_INVOL_A 0x21000 /* Input Volume target */ |
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| 141 | #define VORTEX_MIX_VOL_A 0x21800 /* Output Volume target */ |
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| 142 | |
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| 143 | #define VOL_MIN 0x80 /* Input volume when muted. */ |
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| 144 | #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ |
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| 145 | |
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| 146 | /* SRC */ |
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| 147 | #define VORTEX_SRC_CHNBASE 0x26c40 |
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| 148 | #define VORTEX_SRC_RTBASE 0x26c00 |
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| 149 | #define VORTEX_SRCBLOCK_SR 0x26cc0 |
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| 150 | #define VORTEX_SRC_SOURCE 0x26cc4 |
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| 151 | #define VORTEX_SRC_SOURCESIZE 0x26cc8 |
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| 152 | /* Params |
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| 153 | 0x26e00 : 1 U0 |
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| 154 | 0x26e40 : 2 CR |
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| 155 | 0x26e80 : 3 U3 |
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| 156 | 0x26ec0 : 4 DRIFT1 |
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| 157 | 0x26f00 : 5 U1 |
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| 158 | 0x26f40 : 6 DRIFT2 |
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| 159 | 0x26f80 : 7 U2 : Target rate, direction |
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| 160 | */ |
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| 161 | |
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| 162 | #define VORTEX_SRC_CONVRATIO 0x26e40 |
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| 163 | #define VORTEX_SRC_DRIFT0 0x26e80 |
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| 164 | #define VORTEX_SRC_DRIFT1 0x26ec0 |
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| 165 | #define VORTEX_SRC_DRIFT2 0x26f40 |
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| 166 | #define VORTEX_SRC_U0 0x26e00 |
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| 167 | #define U0_SLOWLOCK 0x200 |
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| 168 | #define VORTEX_SRC_U1 0x26f00 |
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| 169 | #define VORTEX_SRC_U2 0x26f80 |
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| 170 | #define VORTEX_SRC_DATA 0x26800 /* 0xc800 */ |
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| 171 | #define VORTEX_SRC_DATA0 0x26000 |
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| 172 | |
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| 173 | /* FIFO */ |
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| 174 | #define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */ |
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| 175 | #define VORTEX_FIFO_WTCTRL 0x16000 |
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| 176 | #define FIFO_RDONLY 0x00000001 |
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| 177 | #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ |
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| 178 | #define FIFO_VALID 0x00000010 |
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| 179 | #define FIFO_EMPTY 0x00000020 |
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| 180 | #define FIFO_U0 0x00002000 /* Unknown. */ |
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| 181 | #define FIFO_U1 0x00040000 |
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| 182 | #define FIFO_SIZE_BITS 6 |
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| 183 | #define FIFO_SIZE (1<<(FIFO_SIZE_BITS)) // 0x40 |
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| 184 | #define FIFO_MASK (FIFO_SIZE-1) //0x3f /* at shift left 0xc */ |
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| 185 | #define FIFO_BITS 0x1c400000 |
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| 186 | #define VORTEX_FIFO_ADBDATA 0x14000 |
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| 187 | #define VORTEX_FIFO_WTDATA 0x10000 |
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| 188 | |
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| 189 | #define VORTEX_FIFO_GIRT 0x17000 /* wt0, wt1, adb */ |
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| 190 | #define GIRT_COUNT 3 |
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| 191 | |
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| 192 | /* CODEC */ |
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| 193 | |
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| 194 | #define VORTEX_CODEC_CHN 0x29080 /* The name "CHN" is wrong. */ |
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| 195 | |
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| 196 | #define VORTEX_CODEC_CTRL 0x29184 |
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| 197 | #define VORTEX_CODEC_IO 0x29188 |
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| 198 | |
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| 199 | #define VORTEX_CODEC_SPORTCTRL 0x2918c |
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| 200 | |
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| 201 | #define VORTEX_CODEC_EN 0x29190 |
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| 202 | #define EN_AUDIO0 0x00000300 |
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| 203 | #define EN_MODEM 0x00000c00 |
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| 204 | #define EN_AUDIO1 0x00003000 |
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| 205 | #define EN_SPORT 0x00030000 |
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| 206 | #define EN_SPDIF 0x000c0000 |
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| 207 | #define EN_CODEC (EN_AUDIO1 | EN_AUDIO0) |
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| 208 | |
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| 209 | #define VORTEX_SPDIF_SMPRATE 0x29194 |
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| 210 | |
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| 211 | #define VORTEX_SPDIF_FLAGS 0x2205c |
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| 212 | #define VORTEX_SPDIF_CFG0 0x291D0 /* status data */ |
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| 213 | #define VORTEX_SPDIF_CFG1 0x291D4 |
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| 214 | |
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| 215 | #define VORTEX_SMP_TIME 0x29198 /* Sample counter/timer */ |
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| 216 | #define VORTEX_SMP_TIMER 0x2919c |
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| 217 | #define VORTEX_CODEC2_CTRL 0x291a0 |
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| 218 | |
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| 219 | #define VORTEX_MODEM_CTRL 0x291ac |
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| 220 | |
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| 221 | /* IRQ */ |
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| 222 | #define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */ |
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| 223 | #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */ |
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| 224 | |
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| 225 | //#define VORTEX_IRQ_U0 0x2a008 /* ?? */ |
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| 226 | #define VORTEX_STAT 0x2a008 /* Some sort of status */ |
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| 227 | #define STAT_IRQ 0x00000001 /* This bitis set if the IRQ is valid. */ |
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| 228 | |
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| 229 | #define VORTEX_CTRL 0x2a00c |
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| 230 | #define CTRL_MIDI_EN 0x00000001 |
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| 231 | #define CTRL_MIDI_PORT 0x00000060 |
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| 232 | #define CTRL_GAME_EN 0x00000008 |
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| 233 | #define CTRL_GAME_PORT 0x00000e00 |
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| 234 | #define CTRL_IRQ_ENABLE 0x00004000 |
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| 235 | #define CTRL_SPDIF 0x00000000 /* unknown. Please find this value */ |
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| 236 | #define CTRL_SPORT 0x00200000 |
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| 237 | #define CTRL_RST 0x00800000 |
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| 238 | #define CTRL_UNKNOWN 0x01000000 |
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| 239 | |
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| 240 | /* write: Timer period config / read: TIMER IRQ ack. */ |
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| 241 | #define VORTEX_IRQ_STAT 0x2919c |
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| 242 | |
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| 243 | /* MIDI *//* GAME. */ |
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| 244 | #define VORTEX_MIDI_DATA 0x28800 |
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| 245 | #define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */ |
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| 246 | |
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| 247 | #define VORTEX_GAME_LEGACY 0x28808 |
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| 248 | #define VORTEX_CTRL2 0x2880c |
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| 249 | #define CTRL2_GAME_ADCMODE 0x40 |
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| 250 | #define VORTEX_GAME_AXIS 0x28810 /* Axis base register. 4 axis's */ |
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| 251 | #define AXIS_SIZE 4 |
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| 252 | #define AXIS_RANGE 0x1fff |
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| 253 | |
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