| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _20K2REGISTERS_H_ |
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| 7 | #define _20K2REGISTERS_H_ |
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| 8 | |
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| 9 | |
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| 10 | /* Timer Registers */ |
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| 11 | #define WC 0x1b7000 |
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| 12 | #define TIMR 0x1b7004 |
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| 13 | # define TIMR_IE (1<<15) |
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| 14 | # define TIMR_IP (1<<14) |
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| 15 | #define GIP 0x1b7010 |
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| 16 | #define GIE 0x1b7014 |
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| 17 | |
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| 18 | /* I2C Registers */ |
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| 19 | #define I2C_IF_ADDRESS 0x1B9000 |
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| 20 | #define I2C_IF_WDATA 0x1B9004 |
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| 21 | #define I2C_IF_RDATA 0x1B9008 |
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| 22 | #define I2C_IF_STATUS 0x1B900C |
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| 23 | #define I2C_IF_WLOCK 0x1B9010 |
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| 24 | |
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| 25 | /* Global Control Registers */ |
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| 26 | #define GLOBAL_CNTL_GCTL 0x1B7090 |
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| 27 | |
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| 28 | /* PLL Registers */ |
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| 29 | #define PLL_CTL 0x1B7080 |
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| 30 | #define PLL_STAT 0x1B7084 |
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| 31 | #define PLL_ENB 0x1B7088 |
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| 32 | |
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| 33 | /* SRC Registers */ |
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| 34 | #define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */ |
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| 35 | #define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */ |
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| 36 | #define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */ |
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| 37 | #define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */ |
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| 38 | #define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */ |
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| 39 | #define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */ |
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| 40 | #define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */ |
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| 41 | #define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */ |
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| 42 | #define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */ |
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| 43 | #define SRC_MCTL 0x1A012C |
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| 44 | #define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */ |
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| 45 | #define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */ |
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| 46 | #define SRC_ENBSTAT 0x1A202C |
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| 47 | #define SRC_ENBSA 0x1A232C |
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| 48 | #define SRC_DN0Z 0x1A0030 |
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| 49 | #define SRC_DN1Z 0x1A0040 |
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| 50 | #define SRC_UPZ 0x1A0060 |
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| 51 | |
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| 52 | /* GPIO Registers */ |
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| 53 | #define GPIO_DATA 0x1B7020 |
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| 54 | #define GPIO_CTRL 0x1B7024 |
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| 55 | #define GPIO_EXT_DATA 0x1B70A0 |
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| 56 | |
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| 57 | /* Virtual memory registers */ |
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| 58 | #define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */ |
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| 59 | #define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */ |
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| 60 | #define VMEM_CTL 0x1C7000 |
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| 61 | |
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| 62 | /* Transport Registers */ |
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| 63 | #define TRANSPORT_ENB 0x1B6000 |
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| 64 | #define TRANSPORT_CTL 0x1B6004 |
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| 65 | #define TRANSPORT_INT 0x1B6008 |
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| 66 | |
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| 67 | /* Audio IO */ |
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| 68 | #define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */ |
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| 69 | #define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */ |
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| 70 | #define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */ |
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| 71 | #define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */ |
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| 72 | #define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */ |
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| 73 | #define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */ |
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| 74 | #define AUDIO_IO_MCLK 0x1B5600 |
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| 75 | #define AUDIO_IO_TX_BLRCLK 0x1B5604 |
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| 76 | #define AUDIO_IO_RX_BLRCLK 0x1B5608 |
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| 77 | |
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| 78 | /* Mixer */ |
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| 79 | #define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */ |
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| 80 | #define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */ |
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| 81 | #define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */ |
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| 82 | #define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */ |
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| 83 | #define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */ |
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| 84 | #define MIXER_AR_ENABLE 0x19000C |
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| 85 | |
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| 86 | #endif |
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| 87 | |
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