1 | /**************************************************************************** |
2 | |
3 | Copyright Echo Digital Audio Corporation (c) 1998 - 2004 |
4 | All rights reserved |
5 | www.echoaudio.com |
6 | |
7 | This file is part of Echo Digital Audio's generic driver library. |
8 | |
9 | Echo Digital Audio's generic driver library is free software; |
10 | you can redistribute it and/or modify it under the terms of |
11 | the GNU General Public License as published by the Free Software |
12 | Foundation. |
13 | |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | GNU General Public License for more details. |
18 | |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
22 | MA 02111-1307, USA. |
23 | |
24 | ************************************************************************* |
25 | |
26 | Translation from C++ and adaptation for use in ALSA-Driver |
27 | were made by Giuliano Pochini <pochini@shiny.it> |
28 | |
29 | ****************************************************************************/ |
30 | |
31 | #ifndef _ECHO_DSP_ |
32 | #define _ECHO_DSP_ |
33 | |
34 | |
35 | /**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/ |
36 | #if defined(ECHOGALS_FAMILY) |
37 | |
38 | #define NUM_ASIC_TESTS 5 |
39 | #define READ_DSP_TIMEOUT 1000000L /* one second */ |
40 | |
41 | /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/ |
42 | #elif defined(ECHO24_FAMILY) |
43 | |
44 | #define DSP_56361 /* Some Echo24 cards use the 56361 DSP */ |
45 | #define READ_DSP_TIMEOUT 100000L /* .1 second */ |
46 | |
47 | /**** 3G: Gina3G, Layla3G ****/ |
48 | #elif defined(ECHO3G_FAMILY) |
49 | |
50 | #define DSP_56361 |
51 | #define READ_DSP_TIMEOUT 100000L /* .1 second */ |
52 | #define MIN_MTC_1X_RATE 32000 |
53 | |
54 | /**** Indigo: Indigo, Indigo IO, Indigo DJ ****/ |
55 | #elif defined(INDIGO_FAMILY) |
56 | |
57 | #define DSP_56361 |
58 | #define READ_DSP_TIMEOUT 100000L /* .1 second */ |
59 | |
60 | #else |
61 | |
62 | #error No family is defined |
63 | |
64 | #endif |
65 | |
66 | |
67 | |
68 | /* |
69 | * |
70 | * Max inputs and outputs |
71 | * |
72 | */ |
73 | |
74 | #define DSP_MAXAUDIOINPUTS 16 /* Max audio input channels */ |
75 | #define DSP_MAXAUDIOOUTPUTS 16 /* Max audio output channels */ |
76 | #define DSP_MAXPIPES 32 /* Max total pipes (input + output) */ |
77 | |
78 | |
79 | /* |
80 | * |
81 | * These are the offsets for the memory-mapped DSP registers; the DSP base |
82 | * address is treated as the start of a u32 array. |
83 | */ |
84 | |
85 | #define CHI32_CONTROL_REG 4 |
86 | #define CHI32_STATUS_REG 5 |
87 | #define CHI32_VECTOR_REG 6 |
88 | #define CHI32_DATA_REG 7 |
89 | |
90 | |
91 | /* |
92 | * |
93 | * Interesting bits within the DSP registers |
94 | * |
95 | */ |
96 | |
97 | #define CHI32_VECTOR_BUSY 0x00000001 |
98 | #define CHI32_STATUS_REG_HF3 0x00000008 |
99 | #define CHI32_STATUS_REG_HF4 0x00000010 |
100 | #define CHI32_STATUS_REG_HF5 0x00000020 |
101 | #define CHI32_STATUS_HOST_READ_FULL 0x00000004 |
102 | #define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002 |
103 | #define CHI32_STATUS_IRQ 0x00000040 |
104 | |
105 | |
106 | /* |
107 | * |
108 | * DSP commands sent via slave mode; these are sent to the DSP by write_dsp() |
109 | * |
110 | */ |
111 | |
112 | #define DSP_FNC_SET_COMMPAGE_ADDR 0x02 |
113 | #define DSP_FNC_LOAD_LAYLA_ASIC 0xa0 |
114 | #define DSP_FNC_LOAD_GINA24_ASIC 0xa0 |
115 | #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0 |
116 | #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0 |
117 | #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1 |
118 | #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1 |
119 | #define DSP_FNC_LOAD_3G_ASIC 0xa0 |
120 | |
121 | |
122 | /* |
123 | * |
124 | * Defines to handle the MIDI input state engine; these are used to properly |
125 | * extract MIDI time code bytes and their timestamps from the MIDI input stream. |
126 | * |
127 | */ |
128 | |
129 | #define MIDI_IN_STATE_NORMAL 0 |
130 | #define MIDI_IN_STATE_TS_HIGH 1 |
131 | #define MIDI_IN_STATE_TS_LOW 2 |
132 | #define MIDI_IN_STATE_F1_DATA 3 |
133 | #define MIDI_IN_SKIP_DATA (-1) |
134 | |
135 | |
136 | /*---------------------------------------------------------------------------- |
137 | |
138 | Setting the sample rates on Layla24 is somewhat schizophrenic. |
139 | |
140 | For standard rates, it works exactly like Mona and Gina24. That is, for |
141 | 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the |
142 | appropriate bits in the control register and write the control register. |
143 | |
144 | In order to support MIDI time code sync (and possibly SMPTE LTC sync in |
145 | the future), Layla24 also has "continuous sample rate mode". In this mode, |
146 | Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or |
147 | 50 to 100 kHz inclusive for double speed mode. |
148 | |
149 | To use continuous mode: |
150 | |
151 | -Set the clock select bits in the control register to 0xe (see the #define |
152 | below) |
153 | |
154 | -Set double-speed mode if you want to use sample rates above 50 kHz |
155 | |
156 | -Write the control register as you would normally |
157 | |
158 | -Now, you need to set the frequency register. First, you need to determine the |
159 | value for the frequency register. This is given by the following formula: |
160 | |
161 | frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2 |
162 | |
163 | Note the #define below for the magic number |
164 | |
165 | -Wait for the DSP handshake |
166 | -Write the frequency_reg value to the .SampleRate field of the comm page |
167 | -Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h) |
168 | |
169 | Once you have set the control register up for continuous mode, you can just |
170 | write the frequency register to change the sample rate. This could be |
171 | used for MIDI time code sync. For MTC sync, the control register is set for |
172 | continuous mode. The driver then just keeps writing the |
173 | SET_LAYLA24_FREQUENCY_REG command. |
174 | |
175 | -----------------------------------------------------------------------------*/ |
176 | |
177 | #define LAYLA24_MAGIC_NUMBER 677376000 |
178 | #define LAYLA24_CONTINUOUS_CLOCK 0x000e |
179 | |
180 | |
181 | /* |
182 | * |
183 | * DSP vector commands |
184 | * |
185 | */ |
186 | |
187 | #define DSP_VC_RESET 0x80ff |
188 | |
189 | #ifndef DSP_56361 |
190 | |
191 | #define DSP_VC_ACK_INT 0x8073 |
192 | #define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */ |
193 | #define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */ |
194 | #define DSP_VC_METERS_ON 0x0079 |
195 | #define DSP_VC_METERS_OFF 0x007b |
196 | #define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */ |
197 | #define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */ |
198 | #define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */ |
199 | #define DSP_VC_TEST_ASIC 0x00eb |
200 | #define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */ |
201 | #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */ |
202 | #define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */ |
203 | #define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */ |
204 | #define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */ |
205 | #define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */ |
206 | #define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */ |
207 | #define DSP_VC_GO_COMATOSE 0x00f9 |
208 | |
209 | #else /* !DSP_56361 */ |
210 | |
211 | /* Vector commands for families that use either the 56301 or 56361 */ |
212 | #define DSP_VC_ACK_INT 0x80F5 |
213 | #define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */ |
214 | #define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */ |
215 | #define DSP_VC_METERS_ON 0x00EF |
216 | #define DSP_VC_METERS_OFF 0x00F1 |
217 | #define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */ |
218 | #define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */ |
219 | #define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */ |
220 | #define DSP_VC_TEST_ASIC 0x00ED |
221 | #define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */ |
222 | #define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */ |
223 | #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */ |
224 | #define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */ |
225 | #define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */ |
226 | #define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */ |
227 | #define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */ |
228 | #define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */ |
229 | #define DSP_VC_GO_COMATOSE 0x00d9 |
230 | |
231 | #endif /* !DSP_56361 */ |
232 | |
233 | |
234 | /* |
235 | * |
236 | * Timeouts |
237 | * |
238 | */ |
239 | |
240 | #define HANDSHAKE_TIMEOUT 20000 /* send_vector command timeout (20ms) */ |
241 | #define VECTOR_BUSY_TIMEOUT 100000 /* 100ms */ |
242 | #define MIDI_OUT_DELAY_USEC 2000 /* How long to wait after MIDI fills up */ |
243 | |
244 | |
245 | /* |
246 | * |
247 | * Flags for .Flags field in the comm page |
248 | * |
249 | */ |
250 | |
251 | #define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */ |
252 | #define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit |
253 | * in the S/PDIF out status |
254 | * bits. Clear this flag for |
255 | * audio data; |
256 | * set it for AC3 or WMA or |
257 | * some such */ |
258 | #define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */ |
259 | |
260 | |
261 | /* |
262 | * |
263 | * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia |
264 | * |
265 | */ |
266 | |
267 | #define GLDM_CLOCK_DETECT_BIT_WORD 0x0002 |
268 | #define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004 |
269 | #define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008 |
270 | #define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010 |
271 | |
272 | |
273 | /* |
274 | * |
275 | * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24 |
276 | * |
277 | */ |
278 | |
279 | #define GML_CLOCK_DETECT_BIT_WORD96 0x0002 |
280 | #define GML_CLOCK_DETECT_BIT_WORD48 0x0004 |
281 | #define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008 |
282 | #define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010 |
283 | #define GML_CLOCK_DETECT_BIT_WORD (GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48) |
284 | #define GML_CLOCK_DETECT_BIT_SPDIF (GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96) |
285 | #define GML_CLOCK_DETECT_BIT_ESYNC 0x0020 |
286 | #define GML_CLOCK_DETECT_BIT_ADAT 0x0040 |
287 | |
288 | |
289 | /* |
290 | * |
291 | * Layla clock numbers to send to DSP |
292 | * |
293 | */ |
294 | |
295 | #define LAYLA20_CLOCK_INTERNAL 0 |
296 | #define LAYLA20_CLOCK_SPDIF 1 |
297 | #define LAYLA20_CLOCK_WORD 2 |
298 | #define LAYLA20_CLOCK_SUPER 3 |
299 | |
300 | |
301 | /* |
302 | * |
303 | * Gina/Darla clock states |
304 | * |
305 | */ |
306 | |
307 | #define GD_CLOCK_NOCHANGE 0 |
308 | #define GD_CLOCK_44 1 |
309 | #define GD_CLOCK_48 2 |
310 | #define GD_CLOCK_SPDIFIN 3 |
311 | #define GD_CLOCK_UNDEF 0xff |
312 | |
313 | |
314 | /* |
315 | * |
316 | * Gina/Darla S/PDIF status bits |
317 | * |
318 | */ |
319 | |
320 | #define GD_SPDIF_STATUS_NOCHANGE 0 |
321 | #define GD_SPDIF_STATUS_44 1 |
322 | #define GD_SPDIF_STATUS_48 2 |
323 | #define GD_SPDIF_STATUS_UNDEF 0xff |
324 | |
325 | |
326 | /* |
327 | * |
328 | * Layla20 output clocks |
329 | * |
330 | */ |
331 | |
332 | #define LAYLA20_OUTPUT_CLOCK_SUPER 0 |
333 | #define LAYLA20_OUTPUT_CLOCK_WORD 1 |
334 | |
335 | |
336 | /**************************************************************************** |
337 | |
338 | Magic constants for the Darla24 hardware |
339 | |
340 | ****************************************************************************/ |
341 | |
342 | #define GD24_96000 0x0 |
343 | #define GD24_48000 0x1 |
344 | #define GD24_44100 0x2 |
345 | #define GD24_32000 0x3 |
346 | #define GD24_22050 0x4 |
347 | #define GD24_16000 0x5 |
348 | #define GD24_11025 0x6 |
349 | #define GD24_8000 0x7 |
350 | #define GD24_88200 0x8 |
351 | #define GD24_EXT_SYNC 0x9 |
352 | |
353 | |
354 | /* |
355 | * |
356 | * Return values from the DSP when ASIC is loaded |
357 | * |
358 | */ |
359 | |
360 | #define ASIC_ALREADY_LOADED 0x1 |
361 | #define ASIC_NOT_LOADED 0x0 |
362 | |
363 | |
364 | /* |
365 | * |
366 | * DSP Audio formats |
367 | * |
368 | * These are the audio formats that the DSP can transfer |
369 | * via input and output pipes. LE means little-endian, |
370 | * BE means big-endian. |
371 | * |
372 | * DSP_AUDIOFORM_MS_8 |
373 | * |
374 | * 8-bit mono unsigned samples. For playback, |
375 | * mono data is duplicated out the left and right channels |
376 | * of the output bus. The "MS" part of the name |
377 | * means mono->stereo. |
378 | * |
379 | * DSP_AUDIOFORM_MS_16LE |
380 | * |
381 | * 16-bit signed little-endian mono samples. Playback works |
382 | * like the previous code. |
383 | * |
384 | * DSP_AUDIOFORM_MS_24LE |
385 | * |
386 | * 24-bit signed little-endian mono samples. Data is packed |
387 | * three bytes per sample; if you had two samples 0x112233 and 0x445566 |
388 | * they would be stored in memory like this: 33 22 11 66 55 44. |
389 | * |
390 | * DSP_AUDIOFORM_MS_32LE |
391 | * |
392 | * 24-bit signed little-endian mono samples in a 32-bit |
393 | * container. In other words, each sample is a 32-bit signed |
394 | * integer, where the actual audio data is left-justified |
395 | * in the 32 bits and only the 24 most significant bits are valid. |
396 | * |
397 | * DSP_AUDIOFORM_SS_8 |
398 | * DSP_AUDIOFORM_SS_16LE |
399 | * DSP_AUDIOFORM_SS_24LE |
400 | * DSP_AUDIOFORM_SS_32LE |
401 | * |
402 | * Like the previous ones, except now with stereo interleaved |
403 | * data. "SS" means stereo->stereo. |
404 | * |
405 | * DSP_AUDIOFORM_MM_32LE |
406 | * |
407 | * Similar to DSP_AUDIOFORM_MS_32LE, except that the mono |
408 | * data is not duplicated out both the left and right outputs. |
409 | * This mode is used by the ASIO driver. Here, "MM" means |
410 | * mono->mono. |
411 | * |
412 | * DSP_AUDIOFORM_MM_32BE |
413 | * |
414 | * Just like DSP_AUDIOFORM_MM_32LE, but now the data is |
415 | * in big-endian format. |
416 | * |
417 | */ |
418 | |
419 | #define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */ |
420 | #define DSP_AUDIOFORM_MS_16LE 1 /* 16 bit mono */ |
421 | #define DSP_AUDIOFORM_MS_24LE 2 /* 24 bit mono */ |
422 | #define DSP_AUDIOFORM_MS_32LE 3 /* 32 bit mono */ |
423 | #define DSP_AUDIOFORM_SS_8 4 /* 8 bit stereo */ |
424 | #define DSP_AUDIOFORM_SS_16LE 5 /* 16 bit stereo */ |
425 | #define DSP_AUDIOFORM_SS_24LE 6 /* 24 bit stereo */ |
426 | #define DSP_AUDIOFORM_SS_32LE 7 /* 32 bit stereo */ |
427 | #define DSP_AUDIOFORM_MM_32LE 8 /* 32 bit mono->mono little-endian */ |
428 | #define DSP_AUDIOFORM_MM_32BE 9 /* 32 bit mono->mono big-endian */ |
429 | #define DSP_AUDIOFORM_SS_32BE 10 /* 32 bit stereo big endian */ |
430 | #define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */ |
431 | |
432 | |
433 | /* |
434 | * |
435 | * Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20 |
436 | * do not support super interleave. |
437 | * |
438 | * 16 bit, 24 bit, and 32 bit little endian samples are supported for super |
439 | * interleave. The interleave factor must be even. 16 - way interleave is the |
440 | * current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16. |
441 | * |
442 | * The actual format code is derived by taking the define below and or-ing with |
443 | * the interleave factor. So, 32 bit interleave by 6 is 0x86 and |
444 | * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50. |
445 | * |
446 | */ |
447 | |
448 | #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40 |
449 | #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0 |
450 | #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80 |
451 | |
452 | |
453 | /* |
454 | * |
455 | * Gina24, Mona, and Layla24 control register defines |
456 | * |
457 | */ |
458 | |
459 | #define GML_CONVERTER_ENABLE 0x0010 |
460 | #define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, |
461 | consumer == 0 */ |
462 | #define GML_SPDIF_SAMPLE_RATE0 0x0040 |
463 | #define GML_SPDIF_SAMPLE_RATE1 0x0080 |
464 | #define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, |
465 | 0 == one channel */ |
466 | #define GML_SPDIF_NOT_AUDIO 0x0200 |
467 | #define GML_SPDIF_COPY_PERMIT 0x0400 |
468 | #define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ |
469 | #define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */ |
470 | #define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */ |
471 | #define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode, |
472 | * 0 == RCA or optical mode */ |
473 | #define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, |
474 | 0 == single speed */ |
475 | |
476 | #define GML_DIGITAL_IN_AUTO_MUTE 0x800000 |
477 | |
478 | #define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE) |
479 | #define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE) |
480 | #define GML_48KHZ 0x2 |
481 | #define GML_44KHZ 0x3 |
482 | #define GML_32KHZ 0x4 |
483 | #define GML_22KHZ 0x5 |
484 | #define GML_16KHZ 0x6 |
485 | #define GML_11KHZ 0x7 |
486 | #define GML_8KHZ 0x8 |
487 | #define GML_SPDIF_CLOCK 0x9 |
488 | #define GML_ADAT_CLOCK 0xA |
489 | #define GML_WORD_CLOCK 0xB |
490 | #define GML_ESYNC_CLOCK 0xC |
491 | #define GML_ESYNCx2_CLOCK 0xD |
492 | |
493 | #define GML_CLOCK_CLEAR_MASK 0xffffbff0 |
494 | #define GML_SPDIF_RATE_CLEAR_MASK (~(GML_SPDIF_SAMPLE_RATE0|GML_SPDIF_SAMPLE_RATE1)) |
495 | #define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff |
496 | #define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f |
497 | |
498 | |
499 | /* |
500 | * |
501 | * Mia sample rate and clock setting constants |
502 | * |
503 | */ |
504 | |
505 | #define MIA_32000 0x0040 |
506 | #define MIA_44100 0x0042 |
507 | #define MIA_48000 0x0041 |
508 | #define MIA_88200 0x0142 |
509 | #define MIA_96000 0x0141 |
510 | |
511 | #define MIA_SPDIF 0x00000044 |
512 | #define MIA_SPDIF96 0x00000144 |
513 | |
514 | #define MIA_MIDI_REV 1 /* Must be Mia rev 1 for MIDI support */ |
515 | |
516 | |
517 | /* |
518 | * |
519 | * 3G register bits |
520 | * |
521 | */ |
522 | |
523 | #define E3G_CONVERTER_ENABLE 0x0010 |
524 | #define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, |
525 | consumer == 0 */ |
526 | #define E3G_SPDIF_SAMPLE_RATE0 0x0040 |
527 | #define E3G_SPDIF_SAMPLE_RATE1 0x0080 |
528 | #define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, |
529 | 0 == one channel */ |
530 | #define E3G_SPDIF_NOT_AUDIO 0x0200 |
531 | #define E3G_SPDIF_COPY_PERMIT 0x0400 |
532 | #define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ |
533 | #define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, |
534 | 0 == single speed */ |
535 | #define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on, |
536 | 0 == phantom power off */ |
537 | |
538 | #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE) |
539 | #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE) |
540 | #define E3G_48KHZ 0x2 |
541 | #define E3G_44KHZ 0x3 |
542 | #define E3G_32KHZ 0x4 |
543 | #define E3G_22KHZ 0x5 |
544 | #define E3G_16KHZ 0x6 |
545 | #define E3G_11KHZ 0x7 |
546 | #define E3G_8KHZ 0x8 |
547 | #define E3G_SPDIF_CLOCK 0x9 |
548 | #define E3G_ADAT_CLOCK 0xA |
549 | #define E3G_WORD_CLOCK 0xB |
550 | #define E3G_CONTINUOUS_CLOCK 0xE |
551 | |
552 | #define E3G_ADAT_MODE 0x1000 |
553 | #define E3G_SPDIF_OPTICAL_MODE 0x2000 |
554 | |
555 | #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0 |
556 | #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff |
557 | #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f |
558 | |
559 | /* Clock detect bits reported by the DSP */ |
560 | #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001 |
561 | #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002 |
562 | #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004 |
563 | #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004 |
564 | #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008 |
565 | #define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48) |
566 | #define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96) |
567 | |
568 | /* Frequency control register */ |
569 | #define E3G_MAGIC_NUMBER 677376000 |
570 | #define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2) |
571 | #define E3G_FREQ_REG_MAX 0xffff |
572 | |
573 | /* 3G external box types */ |
574 | #define E3G_GINA3G_BOX_TYPE 0x00 |
575 | #define E3G_LAYLA3G_BOX_TYPE 0x10 |
576 | #define E3G_ASIC_NOT_LOADED 0xffff |
577 | #define E3G_BOX_TYPE_MASK 0xf0 |
578 | |
579 | /* Indigo express control register values */ |
580 | #define INDIGO_EXPRESS_32000 0x02 |
581 | #define INDIGO_EXPRESS_44100 0x01 |
582 | #define INDIGO_EXPRESS_48000 0x00 |
583 | #define INDIGO_EXPRESS_DOUBLE_SPEED 0x10 |
584 | #define INDIGO_EXPRESS_QUAD_SPEED 0x04 |
585 | #define INDIGO_EXPRESS_CLOCK_MASK 0x17 |
586 | |
587 | |
588 | /* |
589 | * |
590 | * Gina20 & Layla20 have input gain controls for the analog inputs; |
591 | * this is the magic number for the hardware that gives you 0 dB at -10. |
592 | * |
593 | */ |
594 | |
595 | #define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8 |
596 | |
597 | |
598 | /* |
599 | * |
600 | * Defines how much time must pass between DSP load attempts |
601 | * |
602 | */ |
603 | |
604 | #define DSP_LOAD_ATTEMPT_PERIOD 1000000L /* One second */ |
605 | |
606 | |
607 | /* |
608 | * |
609 | * Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are |
610 | * no longer used, but the sizes must still be right for the DSP to see |
611 | * the comm page correctly. |
612 | * |
613 | */ |
614 | |
615 | #define MONITOR_ARRAY_SIZE 0x180 |
616 | #define VMIXER_ARRAY_SIZE 0x40 |
617 | #define MIDI_OUT_BUFFER_SIZE 32 |
618 | #define MIDI_IN_BUFFER_SIZE 256 |
619 | #define MAX_PLAY_TAPS 168 |
620 | #define MAX_REC_TAPS 192 |
621 | #define DSP_MIDI_OUT_FIFO_SIZE 64 |
622 | |
623 | |
624 | /* sg_entry is a single entry for the scatter-gather list. The array of struct |
625 | sg_entry struct is read by the DSP, so all values must be little-endian. */ |
626 | |
627 | #define MAX_SGLIST_ENTRIES 512 |
628 | |
629 | struct sg_entry { |
630 | __le32 addr; |
631 | __le32 size; |
632 | }; |
633 | |
634 | |
635 | /**************************************************************************** |
636 | |
637 | The comm page. This structure is read and written by the DSP; the |
638 | DSP code is a firm believer in the byte offsets written in the comments |
639 | at the end of each line. This structure should not be changed. |
640 | |
641 | Any reads from or writes to this structure should be in little-endian format. |
642 | |
643 | ****************************************************************************/ |
644 | |
645 | struct comm_page { /* Base Length*/ |
646 | __le32 comm_size; /* size of this object 0x000 4 */ |
647 | __le32 flags; /* See Appendix A below 0x004 4 */ |
648 | __le32 unused; /* Unused entry 0x008 4 */ |
649 | __le32 sample_rate; /* Card sample rate in Hz 0x00c 4 */ |
650 | __le32 handshake; /* DSP command handshake 0x010 4 */ |
651 | __le32 cmd_start; /* Chs. to start mask 0x014 4 */ |
652 | __le32 cmd_stop; /* Chs. to stop mask 0x018 4 */ |
653 | __le32 cmd_reset; /* Chs. to reset mask 0x01c 4 */ |
654 | __le16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */ |
655 | struct sg_entry sglist_addr[DSP_MAXPIPES]; |
656 | /* Chs. Physical sglist addrs 0x060 32*8 */ |
657 | __le32 position[DSP_MAXPIPES]; |
658 | /* Positions for ea. ch. 0x160 32*4 */ |
659 | s8 vu_meter[DSP_MAXPIPES]; |
660 | /* VU meters 0x1e0 32*1 */ |
661 | s8 peak_meter[DSP_MAXPIPES]; |
662 | /* Peak meters 0x200 32*1 */ |
663 | s8 line_out_level[DSP_MAXAUDIOOUTPUTS]; |
664 | /* Output gain 0x220 16*1 */ |
665 | s8 line_in_level[DSP_MAXAUDIOINPUTS]; |
666 | /* Input gain 0x230 16*1 */ |
667 | s8 monitors[MONITOR_ARRAY_SIZE]; |
668 | /* Monitor map 0x240 0x180 */ |
669 | __le32 play_coeff[MAX_PLAY_TAPS]; |
670 | /* Gina/Darla play filters - obsolete 0x3c0 168*4 */ |
671 | __le32 rec_coeff[MAX_REC_TAPS]; |
672 | /* Gina/Darla record filters - obsolete 0x660 192*4 */ |
673 | __le16 midi_input[MIDI_IN_BUFFER_SIZE]; |
674 | /* MIDI input data transfer buffer 0x960 256*2 */ |
675 | u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */ |
676 | u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */ |
677 | u8 gd_resampler_state; /* Should always be 3 0xb62 1 */ |
678 | u8 filler2; /* 0xb63 1 */ |
679 | __le32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */ |
680 | __le16 input_clock; /* Chg. Input clock state 0xb68 2 */ |
681 | __le16 output_clock; /* Chg. Output clock state 0xb6a 2 */ |
682 | __le32 status_clocks; /* Current Input clock state 0xb6c 4 */ |
683 | __le32 ext_box_status; /* External box status 0xb70 4 */ |
684 | __le32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */ |
685 | __le32 midi_out_free_count; |
686 | /* # of bytes free in MIDI output FIFO 0xb78 4 */ |
687 | __le32 unused2; /* Cyclic pipes 0xb7c 4 */ |
688 | __le32 control_register; |
689 | /* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */ |
690 | __le32 e3g_frq_register; /* 3G frequency register 0xb84 4 */ |
691 | u8 filler[24]; /* filler 0xb88 24*1 */ |
692 | s8 vmixer[VMIXER_ARRAY_SIZE]; |
693 | /* Vmixer levels 0xba0 64*1 */ |
694 | u8 midi_output[MIDI_OUT_BUFFER_SIZE]; |
695 | /* MIDI output data 0xbe0 32*1 */ |
696 | }; |
697 | |
698 | #endif /* _ECHO_DSP_ */ |
699 | |