| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef AK4396_H_INCLUDED |
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| 3 | #define AK4396_H_INCLUDED |
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| 4 | |
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| 5 | #define AK4396_WRITE 0x2000 |
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| 6 | |
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| 7 | #define AK4396_CONTROL_1 0 |
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| 8 | #define AK4396_CONTROL_2 1 |
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| 9 | #define AK4396_CONTROL_3 2 |
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| 10 | #define AK4396_LCH_ATT 3 |
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| 11 | #define AK4396_RCH_ATT 4 |
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| 12 | |
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| 13 | /* control 1 */ |
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| 14 | #define AK4396_RSTN 0x01 |
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| 15 | #define AK4396_DIF_MASK 0x0e |
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| 16 | #define AK4396_DIF_16_LSB 0x00 |
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| 17 | #define AK4396_DIF_20_LSB 0x02 |
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| 18 | #define AK4396_DIF_24_MSB 0x04 |
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| 19 | #define AK4396_DIF_24_I2S 0x06 |
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| 20 | #define AK4396_DIF_24_LSB 0x08 |
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| 21 | #define AK4396_ACKS 0x80 |
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| 22 | /* control 2 */ |
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| 23 | #define AK4396_SMUTE 0x01 |
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| 24 | #define AK4396_DEM_MASK 0x06 |
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| 25 | #define AK4396_DEM_441 0x00 |
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| 26 | #define AK4396_DEM_OFF 0x02 |
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| 27 | #define AK4396_DEM_48 0x04 |
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| 28 | #define AK4396_DEM_32 0x06 |
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| 29 | #define AK4396_DFS_MASK 0x18 |
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| 30 | #define AK4396_DFS_NORMAL 0x00 |
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| 31 | #define AK4396_DFS_DOUBLE 0x08 |
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| 32 | #define AK4396_DFS_QUAD 0x10 |
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| 33 | #define AK4396_SLOW 0x20 |
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| 34 | #define AK4396_DZFM 0x40 |
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| 35 | #define AK4396_DZFE 0x80 |
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| 36 | /* control 3 */ |
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| 37 | #define AK4396_DZFB 0x04 |
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| 38 | #define AK4396_DCKB 0x10 |
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| 39 | #define AK4396_DCKS 0x20 |
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| 40 | #define AK4396_DSDM 0x40 |
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| 41 | #define AK4396_D_P_MASK 0x80 |
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| 42 | #define AK4396_PCM 0x00 |
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| 43 | #define AK4396_DSD 0x80 |
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| 44 | |
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| 45 | #endif |
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| 46 | |
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