| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #define CS4245_CHIP_ID 0x01 |
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| 3 | #define CS4245_POWER_CTRL 0x02 |
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| 4 | #define CS4245_DAC_CTRL_1 0x03 |
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| 5 | #define CS4245_ADC_CTRL 0x04 |
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| 6 | #define CS4245_MCLK_FREQ 0x05 |
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| 7 | #define CS4245_SIGNAL_SEL 0x06 |
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| 8 | #define CS4245_PGA_B_CTRL 0x07 |
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| 9 | #define CS4245_PGA_A_CTRL 0x08 |
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| 10 | #define CS4245_ANALOG_IN 0x09 |
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| 11 | #define CS4245_DAC_A_CTRL 0x0a |
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| 12 | #define CS4245_DAC_B_CTRL 0x0b |
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| 13 | #define CS4245_DAC_CTRL_2 0x0c |
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| 14 | #define CS4245_INT_STATUS 0x0d |
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| 15 | #define CS4245_INT_MASK 0x0e |
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| 16 | #define CS4245_INT_MODE_MSB 0x0f |
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| 17 | #define CS4245_INT_MODE_LSB 0x10 |
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| 18 | |
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| 19 | /* Chip ID */ |
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| 20 | #define CS4245_CHIP_PART_MASK 0xf0 |
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| 21 | #define CS4245_CHIP_REV_MASK 0x0f |
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| 22 | |
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| 23 | /* Power Control */ |
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| 24 | #define CS4245_FREEZE 0x80 |
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| 25 | #define CS4245_PDN_MIC 0x08 |
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| 26 | #define CS4245_PDN_ADC 0x04 |
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| 27 | #define CS4245_PDN_DAC 0x02 |
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| 28 | #define CS4245_PDN 0x01 |
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| 29 | |
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| 30 | /* DAC Control */ |
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| 31 | #define CS4245_DAC_FM_MASK 0xc0 |
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| 32 | #define CS4245_DAC_FM_SINGLE 0x00 |
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| 33 | #define CS4245_DAC_FM_DOUBLE 0x40 |
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| 34 | #define CS4245_DAC_FM_QUAD 0x80 |
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| 35 | #define CS4245_DAC_DIF_MASK 0x30 |
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| 36 | #define CS4245_DAC_DIF_LJUST 0x00 |
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| 37 | #define CS4245_DAC_DIF_I2S 0x10 |
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| 38 | #define CS4245_DAC_DIF_RJUST_16 0x20 |
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| 39 | #define CS4245_DAC_DIF_RJUST_24 0x30 |
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| 40 | #define CS4245_RESERVED_1 0x08 |
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| 41 | #define CS4245_MUTE_DAC 0x04 |
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| 42 | #define CS4245_DEEMPH 0x02 |
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| 43 | #define CS4245_DAC_MASTER 0x01 |
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| 44 | |
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| 45 | /* ADC Control */ |
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| 46 | #define CS4245_ADC_FM_MASK 0xc0 |
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| 47 | #define CS4245_ADC_FM_SINGLE 0x00 |
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| 48 | #define CS4245_ADC_FM_DOUBLE 0x40 |
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| 49 | #define CS4245_ADC_FM_QUAD 0x80 |
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| 50 | #define CS4245_ADC_DIF_MASK 0x10 |
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| 51 | #define CS4245_ADC_DIF_LJUST 0x00 |
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| 52 | #define CS4245_ADC_DIF_I2S 0x10 |
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| 53 | #define CS4245_MUTE_ADC 0x04 |
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| 54 | #define CS4245_HPF_FREEZE 0x02 |
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| 55 | #define CS4245_ADC_MASTER 0x01 |
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| 56 | |
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| 57 | /* MCLK Frequency */ |
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| 58 | #define CS4245_MCLK1_MASK 0x70 |
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| 59 | #define CS4245_MCLK1_SHIFT 4 |
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| 60 | #define CS4245_MCLK2_MASK 0x07 |
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| 61 | #define CS4245_MCLK2_SHIFT 0 |
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| 62 | #define CS4245_MCLK_1 0 |
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| 63 | #define CS4245_MCLK_1_5 1 |
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| 64 | #define CS4245_MCLK_2 2 |
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| 65 | #define CS4245_MCLK_3 3 |
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| 66 | #define CS4245_MCLK_4 4 |
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| 67 | |
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| 68 | /* Signal Selection */ |
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| 69 | #define CS4245_A_OUT_SEL_MASK 0x60 |
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| 70 | #define CS4245_A_OUT_SEL_HIZ 0x00 |
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| 71 | #define CS4245_A_OUT_SEL_DAC 0x20 |
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| 72 | #define CS4245_A_OUT_SEL_PGA 0x40 |
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| 73 | #define CS4245_LOOP 0x02 |
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| 74 | #define CS4245_ASYNCH 0x01 |
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| 75 | |
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| 76 | /* Channel B/A PGA Control */ |
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| 77 | #define CS4245_PGA_GAIN_MASK 0x3f |
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| 78 | |
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| 79 | /* ADC Input Control */ |
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| 80 | #define CS4245_PGA_SOFT 0x10 |
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| 81 | #define CS4245_PGA_ZERO 0x08 |
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| 82 | #define CS4245_SEL_MASK 0x07 |
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| 83 | #define CS4245_SEL_MIC 0x00 |
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| 84 | #define CS4245_SEL_INPUT_1 0x01 |
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| 85 | #define CS4245_SEL_INPUT_2 0x02 |
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| 86 | #define CS4245_SEL_INPUT_3 0x03 |
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| 87 | #define CS4245_SEL_INPUT_4 0x04 |
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| 88 | #define CS4245_SEL_INPUT_5 0x05 |
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| 89 | #define CS4245_SEL_INPUT_6 0x06 |
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| 90 | |
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| 91 | /* DAC Channel A/B Volume Control */ |
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| 92 | #define CS4245_VOL_MASK 0xff |
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| 93 | |
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| 94 | /* DAC Control 2 */ |
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| 95 | #define CS4245_DAC_SOFT 0x80 |
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| 96 | #define CS4245_DAC_ZERO 0x40 |
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| 97 | #define CS4245_INVERT_DAC 0x20 |
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| 98 | #define CS4245_INT_ACTIVE_HIGH 0x01 |
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| 99 | |
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| 100 | /* Interrupt Status/Mask/Mode */ |
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| 101 | #define CS4245_ADC_CLK_ERR 0x08 |
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| 102 | #define CS4245_DAC_CLK_ERR 0x04 |
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| 103 | #define CS4245_ADC_OVFL 0x02 |
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| 104 | #define CS4245_ADC_UNDRFL 0x01 |
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| 105 | |
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| 106 | #define CS4245_SPI_ADDRESS_S (0x9e << 16) |
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| 107 | #define CS4245_SPI_WRITE_S (0 << 16) |
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| 108 | |
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| 109 | #define CS4245_SPI_ADDRESS 0x9e |
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| 110 | #define CS4245_SPI_WRITE 0 |
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| 111 | #define CS4245_SPI_READ 1 |
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| 112 | |
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