| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef OXYGEN_REGS_H_INCLUDED |
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| 3 | #define OXYGEN_REGS_H_INCLUDED |
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| 4 | |
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| 5 | /* recording channel A */ |
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| 6 | #define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */ |
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| 7 | #define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */ |
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| 8 | #define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */ |
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| 9 | |
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| 10 | /* recording channel B */ |
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| 11 | #define OXYGEN_DMA_B_ADDRESS 0x08 |
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| 12 | #define OXYGEN_DMA_B_COUNT 0x0c |
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| 13 | #define OXYGEN_DMA_B_TCOUNT 0x0e |
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| 14 | |
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| 15 | /* recording channel C */ |
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| 16 | #define OXYGEN_DMA_C_ADDRESS 0x10 |
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| 17 | #define OXYGEN_DMA_C_COUNT 0x14 |
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| 18 | #define OXYGEN_DMA_C_TCOUNT 0x16 |
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| 19 | |
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| 20 | /* SPDIF playback channel */ |
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| 21 | #define OXYGEN_DMA_SPDIF_ADDRESS 0x18 |
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| 22 | #define OXYGEN_DMA_SPDIF_COUNT 0x1c |
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| 23 | #define OXYGEN_DMA_SPDIF_TCOUNT 0x1e |
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| 24 | |
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| 25 | /* multichannel playback channel */ |
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| 26 | #define OXYGEN_DMA_MULTICH_ADDRESS 0x20 |
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| 27 | #define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 24 bits */ |
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| 28 | #define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 24 bits */ |
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| 29 | |
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| 30 | /* AC'97 (front panel) playback channel */ |
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| 31 | #define OXYGEN_DMA_AC97_ADDRESS 0x30 |
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| 32 | #define OXYGEN_DMA_AC97_COUNT 0x34 |
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| 33 | #define OXYGEN_DMA_AC97_TCOUNT 0x36 |
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| 34 | |
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| 35 | /* all registers 0x00..0x36 return current position on read */ |
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| 36 | |
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| 37 | #define OXYGEN_DMA_STATUS 0x40 /* 1 = running, 0 = stop */ |
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| 38 | #define OXYGEN_CHANNEL_A 0x01 |
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| 39 | #define OXYGEN_CHANNEL_B 0x02 |
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| 40 | #define OXYGEN_CHANNEL_C 0x04 |
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| 41 | #define OXYGEN_CHANNEL_SPDIF 0x08 |
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| 42 | #define OXYGEN_CHANNEL_MULTICH 0x10 |
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| 43 | #define OXYGEN_CHANNEL_AC97 0x20 |
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| 44 | |
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| 45 | #define OXYGEN_DMA_PAUSE 0x41 /* 1 = pause */ |
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| 46 | /* OXYGEN_CHANNEL_* */ |
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| 47 | |
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| 48 | #define OXYGEN_DMA_RESET 0x42 |
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| 49 | /* OXYGEN_CHANNEL_* */ |
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| 50 | |
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| 51 | #define OXYGEN_PLAY_CHANNELS 0x43 |
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| 52 | #define OXYGEN_PLAY_CHANNELS_MASK 0x03 |
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| 53 | #define OXYGEN_PLAY_CHANNELS_2 0x00 |
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| 54 | #define OXYGEN_PLAY_CHANNELS_4 0x01 |
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| 55 | #define OXYGEN_PLAY_CHANNELS_6 0x02 |
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| 56 | #define OXYGEN_PLAY_CHANNELS_8 0x03 |
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| 57 | #define OXYGEN_DMA_A_BURST_MASK 0x04 |
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| 58 | #define OXYGEN_DMA_A_BURST_8 0x00 /* dwords */ |
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| 59 | #define OXYGEN_DMA_A_BURST_16 0x04 |
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| 60 | #define OXYGEN_DMA_MULTICH_BURST_MASK 0x08 |
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| 61 | #define OXYGEN_DMA_MULTICH_BURST_8 0x00 |
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| 62 | #define OXYGEN_DMA_MULTICH_BURST_16 0x08 |
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| 63 | |
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| 64 | #define OXYGEN_INTERRUPT_MASK 0x44 |
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| 65 | /* OXYGEN_CHANNEL_* */ |
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| 66 | #define OXYGEN_INT_SPDIF_IN_DETECT 0x0100 |
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| 67 | #define OXYGEN_INT_MCU 0x0200 |
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| 68 | #define OXYGEN_INT_2WIRE 0x0400 |
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| 69 | #define OXYGEN_INT_GPIO 0x0800 |
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| 70 | #define OXYGEN_INT_MCB 0x2000 |
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| 71 | #define OXYGEN_INT_AC97 0x4000 |
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| 72 | |
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| 73 | #define OXYGEN_INTERRUPT_STATUS 0x46 |
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| 74 | /* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */ |
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| 75 | #define OXYGEN_INT_MIDI 0x1000 |
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| 76 | |
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| 77 | #define OXYGEN_MISC 0x48 |
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| 78 | #define OXYGEN_MISC_WRITE_PCI_SUBID 0x01 |
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| 79 | #define OXYGEN_MISC_LATENCY_3F 0x02 |
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| 80 | #define OXYGEN_MISC_REC_C_FROM_SPDIF 0x04 |
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| 81 | #define OXYGEN_MISC_REC_B_FROM_AC97 0x08 |
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| 82 | #define OXYGEN_MISC_REC_A_FROM_MULTICH 0x10 |
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| 83 | #define OXYGEN_MISC_PCI_MEM_W_1_CLOCK 0x20 |
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| 84 | #define OXYGEN_MISC_MIDI 0x40 |
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| 85 | #define OXYGEN_MISC_CRYSTAL_MASK 0x80 |
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| 86 | #define OXYGEN_MISC_CRYSTAL_24576 0x00 |
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| 87 | #define OXYGEN_MISC_CRYSTAL_27 0x80 /* MHz */ |
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| 88 | |
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| 89 | #define OXYGEN_REC_FORMAT 0x4a |
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| 90 | #define OXYGEN_REC_FORMAT_A_MASK 0x03 |
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| 91 | #define OXYGEN_REC_FORMAT_A_SHIFT 0 |
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| 92 | #define OXYGEN_REC_FORMAT_B_MASK 0x0c |
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| 93 | #define OXYGEN_REC_FORMAT_B_SHIFT 2 |
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| 94 | #define OXYGEN_REC_FORMAT_C_MASK 0x30 |
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| 95 | #define OXYGEN_REC_FORMAT_C_SHIFT 4 |
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| 96 | #define OXYGEN_FORMAT_16 0x00 |
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| 97 | #define OXYGEN_FORMAT_24 0x01 |
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| 98 | #define OXYGEN_FORMAT_32 0x02 |
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| 99 | |
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| 100 | #define OXYGEN_PLAY_FORMAT 0x4b |
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| 101 | #define OXYGEN_SPDIF_FORMAT_MASK 0x03 |
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| 102 | #define OXYGEN_SPDIF_FORMAT_SHIFT 0 |
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| 103 | #define OXYGEN_MULTICH_FORMAT_MASK 0x0c |
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| 104 | #define OXYGEN_MULTICH_FORMAT_SHIFT 2 |
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| 105 | /* OXYGEN_FORMAT_* */ |
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| 106 | |
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| 107 | #define OXYGEN_REC_CHANNELS 0x4c |
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| 108 | #define OXYGEN_REC_CHANNELS_MASK 0x07 |
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| 109 | #define OXYGEN_REC_CHANNELS_2_2_2 0x00 /* DMA A, B, C */ |
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| 110 | #define OXYGEN_REC_CHANNELS_4_2_2 0x01 |
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| 111 | #define OXYGEN_REC_CHANNELS_6_0_2 0x02 |
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| 112 | #define OXYGEN_REC_CHANNELS_6_2_0 0x03 |
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| 113 | #define OXYGEN_REC_CHANNELS_8_0_0 0x04 |
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| 114 | |
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| 115 | #define OXYGEN_FUNCTION 0x50 |
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| 116 | #define OXYGEN_FUNCTION_CLOCK_MASK 0x01 |
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| 117 | #define OXYGEN_FUNCTION_CLOCK_PLL 0x00 |
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| 118 | #define OXYGEN_FUNCTION_CLOCK_CRYSTAL 0x01 |
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| 119 | #define OXYGEN_FUNCTION_RESET_CODEC 0x02 |
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| 120 | #define OXYGEN_FUNCTION_RESET_POL 0x04 |
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| 121 | #define OXYGEN_FUNCTION_PWDN 0x08 |
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| 122 | #define OXYGEN_FUNCTION_PWDN_EN 0x10 |
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| 123 | #define OXYGEN_FUNCTION_PWDN_POL 0x20 |
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| 124 | #define OXYGEN_FUNCTION_2WIRE_SPI_MASK 0x40 |
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| 125 | #define OXYGEN_FUNCTION_SPI 0x00 |
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| 126 | #define OXYGEN_FUNCTION_2WIRE 0x40 |
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| 127 | #define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 /* 0 = EEPROM */ |
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| 128 | |
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| 129 | #define OXYGEN_I2S_MULTICH_FORMAT 0x60 |
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| 130 | #define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */ |
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| 131 | #define OXYGEN_RATE_32000 0x0000 |
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| 132 | #define OXYGEN_RATE_44100 0x0001 |
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| 133 | #define OXYGEN_RATE_48000 0x0002 |
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| 134 | #define OXYGEN_RATE_64000 0x0003 |
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| 135 | #define OXYGEN_RATE_88200 0x0004 |
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| 136 | #define OXYGEN_RATE_96000 0x0005 |
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| 137 | #define OXYGEN_RATE_176400 0x0006 |
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| 138 | #define OXYGEN_RATE_192000 0x0007 |
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| 139 | #define OXYGEN_I2S_FORMAT_MASK 0x0008 |
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| 140 | #define OXYGEN_I2S_FORMAT_I2S 0x0000 |
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| 141 | #define OXYGEN_I2S_FORMAT_LJUST 0x0008 |
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| 142 | #define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */ |
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| 143 | #define OXYGEN_I2S_MCLK_SHIFT 4 |
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| 144 | #define MCLK_128 0 |
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| 145 | #define MCLK_256 1 |
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| 146 | #define MCLK_512 2 |
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| 147 | #define OXYGEN_I2S_MCLK(f) (((f) & 3) << OXYGEN_I2S_MCLK_SHIFT) |
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| 148 | #define OXYGEN_I2S_BITS_MASK 0x00c0 |
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| 149 | #define OXYGEN_I2S_BITS_16 0x0000 |
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| 150 | #define OXYGEN_I2S_BITS_20 0x0040 |
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| 151 | #define OXYGEN_I2S_BITS_24 0x0080 |
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| 152 | #define OXYGEN_I2S_BITS_32 0x00c0 |
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| 153 | #define OXYGEN_I2S_MASTER 0x0100 |
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| 154 | #define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */ |
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| 155 | #define OXYGEN_I2S_BCLK_64 0x0000 |
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| 156 | #define OXYGEN_I2S_BCLK_128 0x0200 |
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| 157 | #define OXYGEN_I2S_BCLK_256 0x0400 |
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| 158 | #define OXYGEN_I2S_MUTE_MCLK 0x0800 |
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| 159 | |
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| 160 | #define OXYGEN_I2S_A_FORMAT 0x62 |
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| 161 | #define OXYGEN_I2S_B_FORMAT 0x64 |
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| 162 | #define OXYGEN_I2S_C_FORMAT 0x66 |
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| 163 | /* like OXYGEN_I2S_MULTICH_FORMAT */ |
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| 164 | |
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| 165 | #define OXYGEN_SPDIF_CONTROL 0x70 |
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| 166 | #define OXYGEN_SPDIF_OUT_ENABLE 0x00000002 |
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| 167 | #define OXYGEN_SPDIF_LOOPBACK 0x00000004 /* in to out */ |
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| 168 | #define OXYGEN_SPDIF_SENSE_MASK 0x00000008 |
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| 169 | #define OXYGEN_SPDIF_LOCK_MASK 0x00000010 |
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| 170 | #define OXYGEN_SPDIF_RATE_MASK 0x00000020 |
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| 171 | #define OXYGEN_SPDIF_SPDVALID 0x00000040 |
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| 172 | #define OXYGEN_SPDIF_SENSE_PAR 0x00000200 |
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| 173 | #define OXYGEN_SPDIF_LOCK_PAR 0x00000400 |
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| 174 | #define OXYGEN_SPDIF_SENSE_STATUS 0x00000800 |
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| 175 | #define OXYGEN_SPDIF_LOCK_STATUS 0x00001000 |
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| 176 | #define OXYGEN_SPDIF_SENSE_INT 0x00002000 /* r/wc */ |
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| 177 | #define OXYGEN_SPDIF_LOCK_INT 0x00004000 /* r/wc */ |
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| 178 | #define OXYGEN_SPDIF_RATE_INT 0x00008000 /* r/wc */ |
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| 179 | #define OXYGEN_SPDIF_IN_CLOCK_MASK 0x00010000 |
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| 180 | #define OXYGEN_SPDIF_IN_CLOCK_96 0x00000000 /* <= 96 kHz */ |
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| 181 | #define OXYGEN_SPDIF_IN_CLOCK_192 0x00010000 /* > 96 kHz */ |
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| 182 | #define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000 |
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| 183 | #define OXYGEN_SPDIF_OUT_RATE_SHIFT 24 |
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| 184 | /* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */ |
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| 185 | |
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| 186 | #define OXYGEN_SPDIF_OUTPUT_BITS 0x74 |
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| 187 | #define OXYGEN_SPDIF_NONAUDIO 0x00000002 |
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| 188 | #define OXYGEN_SPDIF_C 0x00000004 |
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| 189 | #define OXYGEN_SPDIF_PREEMPHASIS 0x00000008 |
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| 190 | #define OXYGEN_SPDIF_CATEGORY_MASK 0x000007f0 |
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| 191 | #define OXYGEN_SPDIF_CATEGORY_SHIFT 4 |
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| 192 | #define OXYGEN_SPDIF_ORIGINAL 0x00000800 |
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| 193 | #define OXYGEN_SPDIF_CS_RATE_MASK 0x0000f000 |
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| 194 | #define OXYGEN_SPDIF_CS_RATE_SHIFT 12 |
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| 195 | #define OXYGEN_SPDIF_V 0x00010000 /* 0 = valid */ |
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| 196 | |
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| 197 | #define OXYGEN_SPDIF_INPUT_BITS 0x78 |
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| 198 | /* 32 bits, IEC958_AES_* */ |
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| 199 | |
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| 200 | #define OXYGEN_EEPROM_CONTROL 0x80 |
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| 201 | #define OXYGEN_EEPROM_ADDRESS_MASK 0x7f |
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| 202 | #define OXYGEN_EEPROM_DIR_MASK 0x80 |
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| 203 | #define OXYGEN_EEPROM_DIR_READ 0x00 |
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| 204 | #define OXYGEN_EEPROM_DIR_WRITE 0x80 |
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| 205 | |
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| 206 | #define OXYGEN_EEPROM_STATUS 0x81 |
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| 207 | #define OXYGEN_EEPROM_VALID 0x40 |
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| 208 | #define OXYGEN_EEPROM_BUSY 0x80 |
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| 209 | |
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| 210 | #define OXYGEN_EEPROM_DATA 0x82 /* 16 bits */ |
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| 211 | |
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| 212 | #define OXYGEN_2WIRE_CONTROL 0x90 |
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| 213 | #define OXYGEN_2WIRE_DIR_MASK 0x01 |
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| 214 | #define OXYGEN_2WIRE_DIR_WRITE 0x00 |
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| 215 | #define OXYGEN_2WIRE_DIR_READ 0x01 |
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| 216 | #define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */ |
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| 217 | #define OXYGEN_2WIRE_ADDRESS_SHIFT 1 |
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| 218 | |
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| 219 | #define OXYGEN_2WIRE_MAP 0x91 /* address, 8 bits */ |
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| 220 | #define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */ |
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| 221 | |
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| 222 | #define OXYGEN_2WIRE_BUS_STATUS 0x94 |
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| 223 | #define OXYGEN_2WIRE_BUSY 0x0001 |
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| 224 | #define OXYGEN_2WIRE_LENGTH_MASK 0x0002 |
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| 225 | #define OXYGEN_2WIRE_LENGTH_8 0x0000 |
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| 226 | #define OXYGEN_2WIRE_LENGTH_16 0x0002 |
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| 227 | #define OXYGEN_2WIRE_MANUAL_READ 0x0004 /* 0 = auto read */ |
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| 228 | #define OXYGEN_2WIRE_WRITE_MAP_ONLY 0x0008 |
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| 229 | #define OXYGEN_2WIRE_SLAVE_AD_MASK 0x0030 /* AD0, AD1 */ |
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| 230 | #define OXYGEN_2WIRE_INTERRUPT_MASK 0x0040 /* 0 = int. if not responding */ |
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| 231 | #define OXYGEN_2WIRE_SLAVE_NO_RESPONSE 0x0080 |
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| 232 | #define OXYGEN_2WIRE_SPEED_MASK 0x0100 |
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| 233 | #define OXYGEN_2WIRE_SPEED_STANDARD 0x0000 |
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| 234 | #define OXYGEN_2WIRE_SPEED_FAST 0x0100 |
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| 235 | #define OXYGEN_2WIRE_CLOCK_SYNC 0x0200 |
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| 236 | #define OXYGEN_2WIRE_BUS_RESET 0x0400 |
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| 237 | |
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| 238 | #define OXYGEN_SPI_CONTROL 0x98 |
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| 239 | #define OXYGEN_SPI_BUSY 0x01 /* read */ |
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| 240 | #define OXYGEN_SPI_TRIGGER 0x01 /* write */ |
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| 241 | #define OXYGEN_SPI_DATA_LENGTH_MASK 0x02 |
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| 242 | #define OXYGEN_SPI_DATA_LENGTH_2 0x00 |
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| 243 | #define OXYGEN_SPI_DATA_LENGTH_3 0x02 |
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| 244 | #define OXYGEN_SPI_CLOCK_MASK 0x0c |
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| 245 | #define OXYGEN_SPI_CLOCK_160 0x00 /* ns */ |
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| 246 | #define OXYGEN_SPI_CLOCK_320 0x04 |
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| 247 | #define OXYGEN_SPI_CLOCK_640 0x08 |
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| 248 | #define OXYGEN_SPI_CLOCK_1280 0x0c |
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| 249 | #define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */ |
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| 250 | #define OXYGEN_SPI_CODEC_SHIFT 4 |
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| 251 | #define OXYGEN_SPI_CEN_MASK 0x80 |
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| 252 | #define OXYGEN_SPI_CEN_LATCH_CLOCK_LO 0x00 |
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| 253 | #define OXYGEN_SPI_CEN_LATCH_CLOCK_HI 0x80 |
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| 254 | |
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| 255 | #define OXYGEN_SPI_DATA1 0x99 |
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| 256 | #define OXYGEN_SPI_DATA2 0x9a |
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| 257 | #define OXYGEN_SPI_DATA3 0x9b |
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| 258 | |
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| 259 | #define OXYGEN_MPU401 0xa0 |
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| 260 | |
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| 261 | #define OXYGEN_MPU401_CONTROL 0xa2 |
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| 262 | #define OXYGEN_MPU401_LOOPBACK 0x01 /* TXD to RXD */ |
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| 263 | |
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| 264 | #define OXYGEN_GPI_DATA 0xa4 |
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| 265 | /* bits 0..5 = pin XGPI0..XGPI5 */ |
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| 266 | |
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| 267 | #define OXYGEN_GPI_INTERRUPT_MASK 0xa5 |
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| 268 | /* bits 0..5, 1 = enable */ |
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| 269 | |
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| 270 | #define OXYGEN_GPIO_DATA 0xa6 |
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| 271 | /* bits 0..9 */ |
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| 272 | |
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| 273 | #define OXYGEN_GPIO_CONTROL 0xa8 |
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| 274 | /* bits 0..9, 0 = input, 1 = output */ |
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| 275 | #define OXYGEN_GPIO1_XSLAVE_RDY 0x8000 |
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| 276 | |
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| 277 | #define OXYGEN_GPIO_INTERRUPT_MASK 0xaa |
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| 278 | /* bits 0..9, 1 = enable */ |
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| 279 | |
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| 280 | #define OXYGEN_DEVICE_SENSE 0xac |
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| 281 | #define OXYGEN_HEAD_PHONE_DETECT 0x01 |
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| 282 | #define OXYGEN_HEAD_PHONE_MASK 0x06 |
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| 283 | #define OXYGEN_HEAD_PHONE_PASSIVE_SPK 0x00 |
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| 284 | #define OXYGEN_HEAD_PHONE_HP 0x02 |
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| 285 | #define OXYGEN_HEAD_PHONE_ACTIVE_SPK 0x04 |
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| 286 | |
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| 287 | #define OXYGEN_MCU_2WIRE_DATA 0xb0 |
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| 288 | |
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| 289 | #define OXYGEN_MCU_2WIRE_MAP 0xb2 |
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| 290 | |
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| 291 | #define OXYGEN_MCU_2WIRE_STATUS 0xb3 |
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| 292 | #define OXYGEN_MCU_2WIRE_BUSY 0x01 |
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| 293 | #define OXYGEN_MCU_2WIRE_LENGTH_MASK 0x06 |
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| 294 | #define OXYGEN_MCU_2WIRE_LENGTH_1 0x00 |
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| 295 | #define OXYGEN_MCU_2WIRE_LENGTH_2 0x02 |
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| 296 | #define OXYGEN_MCU_2WIRE_LENGTH_3 0x04 |
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| 297 | #define OXYGEN_MCU_2WIRE_WRITE 0x08 /* r/wc */ |
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| 298 | #define OXYGEN_MCU_2WIRE_READ 0x10 /* r/wc */ |
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| 299 | #define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL 0x20 /* r/wc */ |
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| 300 | #define OXYGEN_MCU_2WIRE_RESET 0x40 |
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| 301 | |
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| 302 | #define OXYGEN_MCU_2WIRE_CONTROL 0xb4 |
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| 303 | #define OXYGEN_MCU_2WIRE_DRV_ACK 0x01 |
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| 304 | #define OXYGEN_MCU_2WIRE_DRV_XACT 0x02 |
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| 305 | #define OXYGEN_MCU_2WIRE_INT_MASK 0x04 |
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| 306 | #define OXYGEN_MCU_2WIRE_SYNC_MASK 0x08 |
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| 307 | #define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN 0x00 |
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| 308 | #define OXYGEN_MCU_2WIRE_SYNC_DATA 0x08 |
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| 309 | #define OXYGEN_MCU_2WIRE_ADDRESS_MASK 0x30 |
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| 310 | #define OXYGEN_MCU_2WIRE_ADDRESS_10 0x00 |
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| 311 | #define OXYGEN_MCU_2WIRE_ADDRESS_12 0x10 |
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| 312 | #define OXYGEN_MCU_2WIRE_ADDRESS_14 0x20 |
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| 313 | #define OXYGEN_MCU_2WIRE_ADDRESS_16 0x30 |
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| 314 | #define OXYGEN_MCU_2WIRE_INT_POL 0x40 |
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| 315 | #define OXYGEN_MCU_2WIRE_SYNC_ENABLE 0x80 |
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| 316 | |
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| 317 | #define OXYGEN_PLAY_ROUTING 0xc0 |
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| 318 | #define OXYGEN_PLAY_MUTE01 0x0001 |
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| 319 | #define OXYGEN_PLAY_MUTE23 0x0002 |
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| 320 | #define OXYGEN_PLAY_MUTE45 0x0004 |
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| 321 | #define OXYGEN_PLAY_MUTE67 0x0008 |
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| 322 | #define OXYGEN_PLAY_MUTE_MASK 0x000f |
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| 323 | #define OXYGEN_PLAY_MULTICH_MASK 0x0010 |
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| 324 | #define OXYGEN_PLAY_MULTICH_I2S_DAC 0x0000 |
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| 325 | #define OXYGEN_PLAY_MULTICH_AC97 0x0010 |
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| 326 | #define OXYGEN_PLAY_SPDIF_MASK 0x00e0 |
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| 327 | #define OXYGEN_PLAY_SPDIF_SPDIF 0x0000 |
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| 328 | #define OXYGEN_PLAY_SPDIF_MULTICH_01 0x0020 |
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| 329 | #define OXYGEN_PLAY_SPDIF_MULTICH_23 0x0040 |
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| 330 | #define OXYGEN_PLAY_SPDIF_MULTICH_45 0x0060 |
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| 331 | #define OXYGEN_PLAY_SPDIF_MULTICH_67 0x0080 |
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| 332 | #define OXYGEN_PLAY_SPDIF_REC_A 0x00a0 |
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| 333 | #define OXYGEN_PLAY_SPDIF_REC_B 0x00c0 |
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| 334 | #define OXYGEN_PLAY_SPDIF_I2S_ADC_3 0x00e0 |
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| 335 | #define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300 |
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| 336 | #define OXYGEN_PLAY_DAC0_SOURCE_SHIFT 8 |
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| 337 | #define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0c00 |
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| 338 | #define OXYGEN_PLAY_DAC1_SOURCE_SHIFT 10 |
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| 339 | #define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000 |
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| 340 | #define OXYGEN_PLAY_DAC2_SOURCE_SHIFT 12 |
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| 341 | #define OXYGEN_PLAY_DAC3_SOURCE_MASK 0xc000 |
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| 342 | #define OXYGEN_PLAY_DAC3_SOURCE_SHIFT 14 |
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| 343 | |
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| 344 | #define OXYGEN_REC_ROUTING 0xc2 |
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| 345 | #define OXYGEN_MUTE_I2S_ADC_1 0x01 |
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| 346 | #define OXYGEN_MUTE_I2S_ADC_2 0x02 |
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| 347 | #define OXYGEN_MUTE_I2S_ADC_3 0x04 |
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| 348 | #define OXYGEN_REC_A_ROUTE_MASK 0x08 |
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| 349 | #define OXYGEN_REC_A_ROUTE_I2S_ADC_1 0x00 |
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| 350 | #define OXYGEN_REC_A_ROUTE_AC97_0 0x08 |
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| 351 | #define OXYGEN_REC_B_ROUTE_MASK 0x10 |
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| 352 | #define OXYGEN_REC_B_ROUTE_I2S_ADC_2 0x00 |
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| 353 | #define OXYGEN_REC_B_ROUTE_AC97_1 0x10 |
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| 354 | #define OXYGEN_REC_C_ROUTE_MASK 0x20 |
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| 355 | #define OXYGEN_REC_C_ROUTE_SPDIF 0x00 |
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| 356 | #define OXYGEN_REC_C_ROUTE_I2S_ADC_3 0x20 |
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| 357 | |
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| 358 | #define OXYGEN_ADC_MONITOR 0xc3 |
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| 359 | #define OXYGEN_ADC_MONITOR_A 0x01 |
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| 360 | #define OXYGEN_ADC_MONITOR_A_HALF_VOL 0x02 |
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| 361 | #define OXYGEN_ADC_MONITOR_B 0x04 |
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| 362 | #define OXYGEN_ADC_MONITOR_B_HALF_VOL 0x08 |
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| 363 | #define OXYGEN_ADC_MONITOR_C 0x10 |
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| 364 | #define OXYGEN_ADC_MONITOR_C_HALF_VOL 0x20 |
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| 365 | |
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| 366 | #define OXYGEN_A_MONITOR_ROUTING 0xc4 |
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| 367 | #define OXYGEN_A_MONITOR_ROUTE_0_MASK 0x03 |
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| 368 | #define OXYGEN_A_MONITOR_ROUTE_0_SHIFT 0 |
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| 369 | #define OXYGEN_A_MONITOR_ROUTE_1_MASK 0x0c |
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| 370 | #define OXYGEN_A_MONITOR_ROUTE_1_SHIFT 2 |
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| 371 | #define OXYGEN_A_MONITOR_ROUTE_2_MASK 0x30 |
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| 372 | #define OXYGEN_A_MONITOR_ROUTE_2_SHIFT 4 |
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| 373 | #define OXYGEN_A_MONITOR_ROUTE_3_MASK 0xc0 |
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| 374 | #define OXYGEN_A_MONITOR_ROUTE_3_SHIFT 6 |
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| 375 | |
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| 376 | #define OXYGEN_AC97_CONTROL 0xd0 |
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| 377 | #define OXYGEN_AC97_COLD_RESET 0x0001 |
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| 378 | #define OXYGEN_AC97_SUSPENDED 0x0002 /* read */ |
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| 379 | #define OXYGEN_AC97_RESUME 0x0002 /* write */ |
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| 380 | #define OXYGEN_AC97_CLOCK_DISABLE 0x0004 |
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| 381 | #define OXYGEN_AC97_NO_CODEC_0 0x0008 |
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| 382 | #define OXYGEN_AC97_CODEC_0 0x0010 |
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| 383 | #define OXYGEN_AC97_CODEC_1 0x0020 |
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| 384 | |
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| 385 | #define OXYGEN_AC97_INTERRUPT_MASK 0xd2 |
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| 386 | #define OXYGEN_AC97_INT_READ_DONE 0x01 |
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| 387 | #define OXYGEN_AC97_INT_WRITE_DONE 0x02 |
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| 388 | #define OXYGEN_AC97_INT_CODEC_0 0x10 |
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| 389 | #define OXYGEN_AC97_INT_CODEC_1 0x20 |
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| 390 | |
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| 391 | #define OXYGEN_AC97_INTERRUPT_STATUS 0xd3 |
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| 392 | /* OXYGEN_AC97_INT_* */ |
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| 393 | |
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| 394 | #define OXYGEN_AC97_OUT_CONFIG 0xd4 |
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| 395 | #define OXYGEN_AC97_CODEC1_SLOT3 0x00000001 |
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| 396 | #define OXYGEN_AC97_CODEC1_SLOT3_VSR 0x00000002 |
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| 397 | #define OXYGEN_AC97_CODEC1_SLOT4 0x00000010 |
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| 398 | #define OXYGEN_AC97_CODEC1_SLOT4_VSR 0x00000020 |
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| 399 | #define OXYGEN_AC97_CODEC0_FRONTL 0x00000100 |
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| 400 | #define OXYGEN_AC97_CODEC0_FRONTR 0x00000200 |
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| 401 | #define OXYGEN_AC97_CODEC0_SIDEL 0x00000400 |
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| 402 | #define OXYGEN_AC97_CODEC0_SIDER 0x00000800 |
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| 403 | #define OXYGEN_AC97_CODEC0_CENTER 0x00001000 |
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| 404 | #define OXYGEN_AC97_CODEC0_BASE 0x00002000 |
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| 405 | #define OXYGEN_AC97_CODEC0_REARL 0x00004000 |
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| 406 | #define OXYGEN_AC97_CODEC0_REARR 0x00008000 |
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| 407 | |
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| 408 | #define OXYGEN_AC97_IN_CONFIG 0xd8 |
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| 409 | #define OXYGEN_AC97_CODEC1_LINEL 0x00000001 |
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| 410 | #define OXYGEN_AC97_CODEC1_LINEL_VSR 0x00000002 |
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| 411 | #define OXYGEN_AC97_CODEC1_LINEL_16 0x00000000 |
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| 412 | #define OXYGEN_AC97_CODEC1_LINEL_18 0x00000004 |
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| 413 | #define OXYGEN_AC97_CODEC1_LINEL_20 0x00000008 |
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| 414 | #define OXYGEN_AC97_CODEC1_LINER 0x00000010 |
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| 415 | #define OXYGEN_AC97_CODEC1_LINER_VSR 0x00000020 |
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| 416 | #define OXYGEN_AC97_CODEC1_LINER_16 0x00000000 |
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| 417 | #define OXYGEN_AC97_CODEC1_LINER_18 0x00000040 |
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| 418 | #define OXYGEN_AC97_CODEC1_LINER_20 0x00000080 |
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| 419 | #define OXYGEN_AC97_CODEC0_LINEL 0x00000100 |
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| 420 | #define OXYGEN_AC97_CODEC0_LINER 0x00000200 |
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| 421 | |
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| 422 | #define OXYGEN_AC97_REGS 0xdc |
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| 423 | #define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff |
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| 424 | #define OXYGEN_AC97_REG_ADDR_MASK 0x007f0000 |
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| 425 | #define OXYGEN_AC97_REG_ADDR_SHIFT 16 |
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| 426 | #define OXYGEN_AC97_REG_DIR_MASK 0x00800000 |
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| 427 | #define OXYGEN_AC97_REG_DIR_WRITE 0x00000000 |
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| 428 | #define OXYGEN_AC97_REG_DIR_READ 0x00800000 |
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| 429 | #define OXYGEN_AC97_REG_CODEC_MASK 0x01000000 |
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| 430 | #define OXYGEN_AC97_REG_CODEC_SHIFT 24 |
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| 431 | |
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| 432 | #define OXYGEN_TEST 0xe0 |
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| 433 | #define OXYGEN_TEST_RAM_SUCCEEDED 0x01 |
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| 434 | #define OXYGEN_TEST_PLAYBACK_RAM 0x02 |
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| 435 | #define OXYGEN_TEST_RECORD_RAM 0x04 |
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| 436 | #define OXYGEN_TEST_PLL 0x08 |
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| 437 | #define OXYGEN_TEST_2WIRE_LOOPBACK 0x10 |
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| 438 | |
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| 439 | #define OXYGEN_DMA_FLUSH 0xe1 |
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| 440 | /* OXYGEN_CHANNEL_* */ |
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| 441 | |
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| 442 | #define OXYGEN_CODEC_VERSION 0xe4 |
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| 443 | #define OXYGEN_CODEC_ID_MASK 0x07 |
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| 444 | |
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| 445 | #define OXYGEN_REVISION 0xe6 |
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| 446 | #define OXYGEN_PACKAGE_ID_MASK 0x0007 |
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| 447 | #define OXYGEN_PACKAGE_ID_8786 0x0004 |
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| 448 | #define OXYGEN_PACKAGE_ID_8787 0x0006 |
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| 449 | #define OXYGEN_PACKAGE_ID_8788 0x0007 |
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| 450 | #define OXYGEN_REVISION_MASK 0xfff8 |
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| 451 | #define OXYGEN_REVISION_2 0x0008 |
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| 452 | |
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| 453 | #define OXYGEN_OFFSIN_48K 0xe8 |
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| 454 | #define OXYGEN_OFFSBASE_48K 0xe9 |
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| 455 | #define OXYGEN_OFFSBASE_MASK 0x0fff |
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| 456 | #define OXYGEN_OFFSIN_44K 0xec |
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| 457 | #define OXYGEN_OFFSBASE_44K 0xed |
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| 458 | |
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| 459 | #endif |
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| 460 | |
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