1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * AMD ACP Driver |
4 | * |
5 | * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved. |
6 | */ |
7 | |
8 | #include "rpl_acp6x_chip_offset_byte.h" |
9 | |
10 | #define ACP_DEVICE_ID 0x15E2 |
11 | #define ACP6x_PHY_BASE_ADDRESS 0x1240000 |
12 | |
13 | #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 |
14 | #define ACP_PGFSM_CNTL_POWER_ON_MASK 1 |
15 | #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 |
16 | #define ACP_PGFSM_STATUS_MASK 3 |
17 | #define ACP_POWERED_ON 0 |
18 | #define ACP_POWER_ON_IN_PROGRESS 1 |
19 | #define ACP_POWERED_OFF 2 |
20 | #define ACP_POWER_OFF_IN_PROGRESS 3 |
21 | |
22 | #define DELAY_US 5 |
23 | #define ACP_COUNTER 20000 |
24 | |
25 | /* time in ms for runtime suspend delay */ |
26 | #define ACP_SUSPEND_DELAY_MS 2000 |
27 | |
28 | static inline u32 rpl_acp_readl(void __iomem *base_addr) |
29 | { |
30 | return readl(addr: base_addr - ACP6x_PHY_BASE_ADDRESS); |
31 | } |
32 | |
33 | static inline void rpl_acp_writel(u32 val, void __iomem *base_addr) |
34 | { |
35 | writel(val, addr: base_addr - ACP6x_PHY_BASE_ADDRESS); |
36 | } |
37 | |