| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * AMD ACP 6.x Register Documentation |
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| 4 | * |
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| 5 | * Copyright 2021 Advanced Micro Devices, Inc. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _acp6x_OFFSET_HEADER |
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| 9 | #define |
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| 10 | |
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| 11 | /* Registers from ACP_DMA block */ |
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| 12 | #define ACP_DMA_CNTL_0 0x1240000 |
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| 13 | #define ACP_DMA_CNTL_1 0x1240004 |
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| 14 | #define ACP_DMA_CNTL_2 0x1240008 |
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| 15 | #define ACP_DMA_CNTL_3 0x124000C |
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| 16 | #define ACP_DMA_CNTL_4 0x1240010 |
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| 17 | #define ACP_DMA_CNTL_5 0x1240014 |
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| 18 | #define ACP_DMA_CNTL_6 0x1240018 |
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| 19 | #define ACP_DMA_CNTL_7 0x124001C |
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| 20 | #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 |
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| 21 | #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024 |
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| 22 | #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028 |
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| 23 | #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C |
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| 24 | #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030 |
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| 25 | #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034 |
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| 26 | #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038 |
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| 27 | #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C |
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| 28 | #define ACP_DMA_DSCR_CNT_0 0x1240040 |
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| 29 | #define ACP_DMA_DSCR_CNT_1 0x1240044 |
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| 30 | #define ACP_DMA_DSCR_CNT_2 0x1240048 |
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| 31 | #define ACP_DMA_DSCR_CNT_3 0x124004C |
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| 32 | #define ACP_DMA_DSCR_CNT_4 0x1240050 |
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| 33 | #define ACP_DMA_DSCR_CNT_5 0x1240054 |
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| 34 | #define ACP_DMA_DSCR_CNT_6 0x1240058 |
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| 35 | #define ACP_DMA_DSCR_CNT_7 0x124005C |
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| 36 | #define ACP_DMA_PRIO_0 0x1240060 |
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| 37 | #define ACP_DMA_PRIO_1 0x1240064 |
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| 38 | #define ACP_DMA_PRIO_2 0x1240068 |
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| 39 | #define ACP_DMA_PRIO_3 0x124006C |
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| 40 | #define ACP_DMA_PRIO_4 0x1240070 |
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| 41 | #define ACP_DMA_PRIO_5 0x1240074 |
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| 42 | #define ACP_DMA_PRIO_6 0x1240078 |
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| 43 | #define ACP_DMA_PRIO_7 0x124007C |
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| 44 | #define ACP_DMA_CUR_DSCR_0 0x1240080 |
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| 45 | #define ACP_DMA_CUR_DSCR_1 0x1240084 |
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| 46 | #define ACP_DMA_CUR_DSCR_2 0x1240088 |
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| 47 | #define ACP_DMA_CUR_DSCR_3 0x124008C |
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| 48 | #define ACP_DMA_CUR_DSCR_4 0x1240090 |
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| 49 | #define ACP_DMA_CUR_DSCR_5 0x1240094 |
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| 50 | #define ACP_DMA_CUR_DSCR_6 0x1240098 |
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| 51 | #define ACP_DMA_CUR_DSCR_7 0x124009C |
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| 52 | #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 |
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| 53 | #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4 |
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| 54 | #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8 |
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| 55 | #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC |
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| 56 | #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0 |
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| 57 | #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4 |
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| 58 | #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8 |
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| 59 | #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC |
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| 60 | #define ACP_DMA_ERR_STS_0 0x12400C0 |
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| 61 | #define ACP_DMA_ERR_STS_1 0x12400C4 |
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| 62 | #define ACP_DMA_ERR_STS_2 0x12400C8 |
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| 63 | #define ACP_DMA_ERR_STS_3 0x12400CC |
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| 64 | #define ACP_DMA_ERR_STS_4 0x12400D0 |
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| 65 | #define ACP_DMA_ERR_STS_5 0x12400D4 |
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| 66 | #define ACP_DMA_ERR_STS_6 0x12400D8 |
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| 67 | #define ACP_DMA_ERR_STS_7 0x12400DC |
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| 68 | #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 |
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| 69 | #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 |
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| 70 | #define ACP_DMA_CH_STS 0x12400E8 |
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| 71 | #define ACP_DMA_CH_GROUP 0x12400EC |
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| 72 | #define ACP_DMA_CH_RST_STS 0x12400F0 |
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| 73 | |
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| 74 | /* Registers from ACP_AXI2AXIATU block */ |
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| 75 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 |
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| 76 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 |
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| 77 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 |
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| 78 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C |
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| 79 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 |
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| 80 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 |
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| 81 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 |
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| 82 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C |
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| 83 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 |
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| 84 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 |
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| 85 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 |
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| 86 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C |
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| 87 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 |
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| 88 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 |
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| 89 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 |
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| 90 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C |
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| 91 | #define ACPAXI2AXI_ATU_CTRL 0x1240C40 |
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| 92 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x1240C44 |
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| 93 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x1240C48 |
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| 94 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x1240C4C |
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| 95 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x1240C50 |
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| 96 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x1240C54 |
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| 97 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x1240C58 |
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| 98 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x1240C5C |
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| 99 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x1240C60 |
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| 100 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x1240C64 |
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| 101 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x1240C68 |
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| 102 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x1240C6C |
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| 103 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x1240C70 |
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| 104 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x1240C74 |
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| 105 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x1240C78 |
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| 106 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x1240C7C |
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| 107 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x1240C80 |
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| 108 | |
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| 109 | /* Registers from ACP_CLKRST block */ |
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| 110 | #define ACP_SOFT_RESET 0x1241000 |
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| 111 | #define ACP_CONTROL 0x1241004 |
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| 112 | #define ACP_STATUS 0x1241008 |
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| 113 | #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 |
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| 114 | #define ACP_ZSC_DSP_CTRL 0x1241014 |
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| 115 | #define ACP_ZSC_STS 0x1241018 |
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| 116 | #define ACP_PGFSM_CONTROL 0x1241024 |
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| 117 | #define ACP_PGFSM_STATUS 0x1241028 |
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| 118 | #define ACP_CLKMUX_SEL 0x124102C |
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| 119 | |
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| 120 | /* Registers from ACP_AON block */ |
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| 121 | #define ACP_PME_EN 0x1241400 |
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| 122 | #define ACP_DEVICE_STATE 0x1241404 |
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| 123 | #define AZ_DEVICE_STATE 0x1241408 |
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| 124 | #define ACP_PIN_CONFIG 0x1241440 |
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| 125 | #define ACP_PAD_PULLUP_CTRL 0x1241444 |
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| 126 | #define ACP_PAD_PULLDOWN_CTRL 0x1241448 |
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| 127 | #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C |
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| 128 | #define ACP_PAD_SCHMEN_CTRL 0x1241450 |
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| 129 | #define ACP_SW_PAD_KEEPER_EN 0x1241454 |
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| 130 | #define ACP_SW_WAKE_EN 0x1241458 |
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| 131 | #define ACP_I2S_WAKE_EN 0x124145C |
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| 132 | #define ACP_SW1_WAKE_EN 0x1241460 |
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| 133 | |
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| 134 | /* Registers from ACP_P1_MISC block */ |
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| 135 | #define ACP_EXTERNAL_INTR_ENB 0x1241A00 |
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| 136 | #define ACP_EXTERNAL_INTR_CNTL 0x1241A04 |
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| 137 | #define ACP_EXTERNAL_INTR_CNTL1 0x1241A08 |
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| 138 | #define ACP_EXTERNAL_INTR_STAT 0x1241A0C |
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| 139 | #define ACP_EXTERNAL_INTR_STAT1 0x1241A10 |
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| 140 | #define ACP_ERROR_STATUS 0x1241A4C |
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| 141 | #define ACP_P1_SW_I2S_ERROR_REASON 0x1241A50 |
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| 142 | #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x1241A6C |
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| 143 | #define ACP_P1_SW_I2S_TX_DMA_POS 0x1241A70 |
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| 144 | #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x1241A74 |
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| 145 | #define ACP_P1_SW_I2S_RX_DMA_POS 0x1241A78 |
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| 146 | #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x1241A7C |
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| 147 | #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x1241A80 |
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| 148 | #define ACP_SCRATCH_REG_BASE_ADDR 0x1241A84 |
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| 149 | #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x1241A88 |
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| 150 | #define ACP_P1_SW_BT_TX_DMA_POS 0x1241A8C |
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| 151 | #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x1241A90 |
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| 152 | #define ACP_P1_SW_HS_TX_DMA_POS 0x1241A94 |
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| 153 | #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x1241A98 |
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| 154 | #define ACP_P1_SW_BT_RX_DMA_POS 0x1241A9C |
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| 155 | #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x1241AA0 |
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| 156 | #define ACP_P1_SW_HS_RX_DMA_POS 0x1241AA4 |
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| 157 | |
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| 158 | /* Registers from ACP_AUDIO_BUFFERS block */ |
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| 159 | #define ACP_I2S_RX_RINGBUFADDR 0x1242000 |
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| 160 | #define ACP_I2S_RX_RINGBUFSIZE 0x1242004 |
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| 161 | #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 |
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| 162 | #define ACP_I2S_RX_FIFOADDR 0x124200C |
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| 163 | #define ACP_I2S_RX_FIFOSIZE 0x1242010 |
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| 164 | #define ACP_I2S_RX_DMA_SIZE 0x1242014 |
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| 165 | #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018 |
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| 166 | #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C |
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| 167 | #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 |
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| 168 | #define ACP_I2S_TX_RINGBUFADDR 0x1242024 |
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| 169 | #define ACP_I2S_TX_RINGBUFSIZE 0x1242028 |
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| 170 | #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C |
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| 171 | #define ACP_I2S_TX_FIFOADDR 0x1242030 |
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| 172 | #define ACP_I2S_TX_FIFOSIZE 0x1242034 |
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| 173 | #define ACP_I2S_TX_DMA_SIZE 0x1242038 |
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| 174 | #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C |
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| 175 | #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040 |
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| 176 | #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 |
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| 177 | #define ACP_BT_RX_RINGBUFADDR 0x1242048 |
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| 178 | #define ACP_BT_RX_RINGBUFSIZE 0x124204C |
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| 179 | #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050 |
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| 180 | #define ACP_BT_RX_FIFOADDR 0x1242054 |
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| 181 | #define ACP_BT_RX_FIFOSIZE 0x1242058 |
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| 182 | #define ACP_BT_RX_DMA_SIZE 0x124205C |
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| 183 | #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060 |
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| 184 | #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064 |
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| 185 | #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 |
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| 186 | #define ACP_BT_TX_RINGBUFADDR 0x124206C |
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| 187 | #define ACP_BT_TX_RINGBUFSIZE 0x1242070 |
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| 188 | #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074 |
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| 189 | #define ACP_BT_TX_FIFOADDR 0x1242078 |
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| 190 | #define ACP_BT_TX_FIFOSIZE 0x124207C |
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| 191 | #define ACP_BT_TX_DMA_SIZE 0x1242080 |
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| 192 | #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084 |
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| 193 | #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088 |
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| 194 | #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C |
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| 195 | #define ACP_HS_RX_RINGBUFADDR 0x1242090 |
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| 196 | #define ACP_HS_RX_RINGBUFSIZE 0x1242094 |
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| 197 | #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098 |
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| 198 | #define ACP_HS_RX_FIFOADDR 0x124209C |
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| 199 | #define ACP_HS_RX_FIFOSIZE 0x12420A0 |
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| 200 | #define ACP_HS_RX_DMA_SIZE 0x12420A4 |
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| 201 | #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8 |
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| 202 | #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC |
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| 203 | #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 |
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| 204 | #define ACP_HS_TX_RINGBUFADDR 0x12420B4 |
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| 205 | #define ACP_HS_TX_RINGBUFSIZE 0x12420B8 |
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| 206 | #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC |
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| 207 | #define ACP_HS_TX_FIFOADDR 0x12420C0 |
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| 208 | #define ACP_HS_TX_FIFOSIZE 0x12420C4 |
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| 209 | #define ACP_HS_TX_DMA_SIZE 0x12420C8 |
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| 210 | #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC |
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| 211 | #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0 |
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| 212 | #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 |
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| 213 | |
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| 214 | /* Registers from ACP_I2S_TDM block */ |
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| 215 | #define ACP_I2STDM_IER 0x1242400 |
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| 216 | #define ACP_I2STDM_IRER 0x1242404 |
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| 217 | #define ACP_I2STDM_RXFRMT 0x1242408 |
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| 218 | #define ACP_I2STDM_ITER 0x124240C |
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| 219 | #define ACP_I2STDM_TXFRMT 0x1242410 |
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| 220 | #define ACP_I2STDM0_MSTRCLKGEN 0x1242414 |
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| 221 | #define ACP_I2STDM1_MSTRCLKGEN 0x1242418 |
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| 222 | #define ACP_I2STDM2_MSTRCLKGEN 0x124241C |
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| 223 | #define ACP_I2STDM_REFCLKGEN 0x1242420 |
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| 224 | |
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| 225 | /* Registers from ACP_BT_TDM block */ |
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| 226 | #define ACP_BTTDM_IER 0x1242800 |
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| 227 | #define ACP_BTTDM_IRER 0x1242804 |
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| 228 | #define ACP_BTTDM_RXFRMT 0x1242808 |
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| 229 | #define ACP_BTTDM_ITER 0x124280C |
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| 230 | #define ACP_BTTDM_TXFRMT 0x1242810 |
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| 231 | #define ACP_HSTDM_IER 0x1242814 |
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| 232 | #define ACP_HSTDM_IRER 0x1242818 |
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| 233 | #define ACP_HSTDM_RXFRMT 0x124281C |
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| 234 | #define ACP_HSTDM_ITER 0x1242820 |
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| 235 | #define ACP_HSTDM_TXFRMT 0x1242824 |
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| 236 | |
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| 237 | /* Registers from ACP_WOV block */ |
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| 238 | #define ACP_WOV_PDM_ENABLE 0x1242C04 |
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| 239 | #define ACP_WOV_PDM_DMA_ENABLE 0x1242C08 |
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| 240 | #define ACP_WOV_RX_RINGBUFADDR 0x1242C0C |
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| 241 | #define ACP_WOV_RX_RINGBUFSIZE 0x1242C10 |
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| 242 | #define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14 |
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| 243 | #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18 |
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| 244 | #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C |
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| 245 | #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20 |
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| 246 | #define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24 |
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| 247 | #define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28 |
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| 248 | #define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C |
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| 249 | #define ACP_WOV_PDM_VAD_CTRL 0x1242C30 |
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| 250 | #define ACP_WOV_WAKE 0x1242C54 |
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| 251 | #define ACP_WOV_BUFFER_STATUS 0x1242C58 |
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| 252 | #define ACP_WOV_MISC_CTRL 0x1242C5C |
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| 253 | #define ACP_WOV_CLK_CTRL 0x1242C60 |
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| 254 | #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64 |
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| 255 | #define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68 |
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| 256 | #define ACP_PDM_CLKDIV 0x1242C6C |
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| 257 | |
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| 258 | /* Registers from ACP_P1_AUDIO_BUFFERS block */ |
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| 259 | #define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00 |
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| 260 | #define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04 |
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| 261 | #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x1243A08 |
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| 262 | #define ACP_P1_I2S_RX_FIFOADDR 0x1243A0C |
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| 263 | #define ACP_P1_I2S_RX_FIFOSIZE 0x1243A10 |
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| 264 | #define ACP_P1_I2S_RX_DMA_SIZE 0x1243A14 |
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| 265 | #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18 |
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| 266 | #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C |
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| 267 | #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x1243A20 |
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| 268 | #define ACP_P1_I2S_TX_RINGBUFADDR 0x1243A24 |
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| 269 | #define ACP_P1_I2S_TX_RINGBUFSIZE 0x1243A28 |
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| 270 | #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x1243A2C |
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| 271 | #define ACP_P1_I2S_TX_FIFOADDR 0x1243A30 |
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| 272 | #define ACP_P1_I2S_TX_FIFOSIZE 0x1243A34 |
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| 273 | #define ACP_P1_I2S_TX_DMA_SIZE 0x1243A38 |
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| 274 | #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C |
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| 275 | #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 |
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| 276 | #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44 |
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| 277 | #define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48 |
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| 278 | #define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C |
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| 279 | #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x1243A50 |
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| 280 | #define ACP_P1_BT_RX_FIFOADDR 0x1243A54 |
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| 281 | #define ACP_P1_BT_RX_FIFOSIZE 0x1243A58 |
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| 282 | #define ACP_P1_BT_RX_DMA_SIZE 0x1243A5C |
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| 283 | #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1243A60 |
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| 284 | #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x1243A64 |
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| 285 | #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x1243A68 |
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| 286 | #define ACP_P1_BT_TX_RINGBUFADDR 0x1243A6C |
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| 287 | #define ACP_P1_BT_TX_RINGBUFSIZE 0x1243A70 |
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| 288 | #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x1243A74 |
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| 289 | #define ACP_P1_BT_TX_FIFOADDR 0x1243A78 |
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| 290 | #define ACP_P1_BT_TX_FIFOSIZE 0x1243A7C |
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| 291 | #define ACP_P1_BT_TX_DMA_SIZE 0x1243A80 |
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| 292 | #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1243A84 |
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| 293 | #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x1243A88 |
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| 294 | #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x1243A8C |
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| 295 | #define ACP_P1_HS_RX_RINGBUFADDR 0x1243A90 |
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| 296 | #define ACP_P1_HS_RX_RINGBUFSIZE 0x1243A94 |
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| 297 | #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x1243A98 |
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| 298 | #define ACP_P1_HS_RX_FIFOADDR 0x1243A9C |
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| 299 | #define ACP_P1_HS_RX_FIFOSIZE 0x1243AA0 |
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| 300 | #define ACP_P1_HS_RX_DMA_SIZE 0x1243AA4 |
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| 301 | #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x1243AA8 |
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| 302 | #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x1243AAC |
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| 303 | #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x1243AB0 |
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| 304 | #define ACP_P1_HS_TX_RINGBUFADDR 0x1243AB4 |
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| 305 | #define ACP_P1_HS_TX_RINGBUFSIZE 0x1243AB8 |
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| 306 | #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x1243ABC |
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| 307 | #define ACP_P1_HS_TX_FIFOADDR 0x1243AC0 |
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| 308 | #define ACP_P1_HS_TX_FIFOSIZE 0x1243AC4 |
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| 309 | #define ACP_P1_HS_TX_DMA_SIZE 0x1243AC8 |
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| 310 | #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x1243ACC |
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| 311 | #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0 |
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| 312 | #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4 |
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| 313 | |
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| 314 | /* Registers from ACP_SCRATCH block */ |
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| 315 | #define ACP_SCRATCH_REG_0 0x1250000 |
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| 316 | #define ACP_SCRATCH_REG_1 0x1250004 |
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| 317 | #define ACP_SCRATCH_REG_2 0x1250008 |
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| 318 | #define ACP_SCRATCH_REG_3 0x125000C |
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| 319 | #define ACP_SCRATCH_REG_4 0x1250010 |
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| 320 | #define ACP_SCRATCH_REG_5 0x1250014 |
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| 321 | #define ACP_SCRATCH_REG_6 0x1250018 |
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| 322 | #define ACP_SCRATCH_REG_7 0x125001C |
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| 323 | #define ACP_SCRATCH_REG_8 0x1250020 |
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| 324 | #define ACP_SCRATCH_REG_9 0x1250024 |
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| 325 | #define ACP_SCRATCH_REG_10 0x1250028 |
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| 326 | #define ACP_SCRATCH_REG_11 0x125002C |
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| 327 | #define ACP_SCRATCH_REG_12 0x1250030 |
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| 328 | #define ACP_SCRATCH_REG_13 0x1250034 |
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| 329 | #define ACP_SCRATCH_REG_14 0x1250038 |
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| 330 | #define ACP_SCRATCH_REG_15 0x125003C |
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| 331 | #define ACP_SCRATCH_REG_16 0x1250040 |
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| 332 | #define ACP_SCRATCH_REG_17 0x1250044 |
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| 333 | #define ACP_SCRATCH_REG_18 0x1250048 |
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| 334 | #define ACP_SCRATCH_REG_19 0x125004C |
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| 335 | #define ACP_SCRATCH_REG_20 0x1250050 |
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| 336 | #define ACP_SCRATCH_REG_21 0x1250054 |
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| 337 | #define ACP_SCRATCH_REG_22 0x1250058 |
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| 338 | #define ACP_SCRATCH_REG_23 0x125005C |
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| 339 | #define ACP_SCRATCH_REG_24 0x1250060 |
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| 340 | #define ACP_SCRATCH_REG_25 0x1250064 |
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| 341 | #define ACP_SCRATCH_REG_26 0x1250068 |
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| 342 | #define ACP_SCRATCH_REG_27 0x125006C |
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| 343 | #define ACP_SCRATCH_REG_28 0x1250070 |
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| 344 | #define ACP_SCRATCH_REG_29 0x1250074 |
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| 345 | #define ACP_SCRATCH_REG_30 0x1250078 |
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| 346 | #define ACP_SCRATCH_REG_31 0x125007C |
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| 347 | #define ACP_SCRATCH_REG_32 0x1250080 |
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| 348 | #define ACP_SCRATCH_REG_33 0x1250084 |
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| 349 | #define ACP_SCRATCH_REG_34 0x1250088 |
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| 350 | #define ACP_SCRATCH_REG_35 0x125008C |
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| 351 | #define ACP_SCRATCH_REG_36 0x1250090 |
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| 352 | #define ACP_SCRATCH_REG_37 0x1250094 |
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| 353 | #define ACP_SCRATCH_REG_38 0x1250098 |
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| 354 | #define ACP_SCRATCH_REG_39 0x125009C |
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| 355 | #define ACP_SCRATCH_REG_40 0x12500A0 |
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| 356 | #define ACP_SCRATCH_REG_41 0x12500A4 |
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| 357 | #define ACP_SCRATCH_REG_42 0x12500A8 |
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| 358 | #define ACP_SCRATCH_REG_43 0x12500AC |
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| 359 | #define ACP_SCRATCH_REG_44 0x12500B0 |
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| 360 | #define ACP_SCRATCH_REG_45 0x12500B4 |
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| 361 | #define ACP_SCRATCH_REG_46 0x12500B8 |
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| 362 | #define ACP_SCRATCH_REG_47 0x12500BC |
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| 363 | #define ACP_SCRATCH_REG_48 0x12500C0 |
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| 364 | #define ACP_SCRATCH_REG_49 0x12500C4 |
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| 365 | #define ACP_SCRATCH_REG_50 0x12500C8 |
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| 366 | #define ACP_SCRATCH_REG_51 0x12500CC |
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| 367 | #define ACP_SCRATCH_REG_52 0x12500D0 |
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| 368 | #define ACP_SCRATCH_REG_53 0x12500D4 |
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| 369 | #define ACP_SCRATCH_REG_54 0x12500D8 |
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| 370 | #define ACP_SCRATCH_REG_55 0x12500DC |
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| 371 | #define ACP_SCRATCH_REG_56 0x12500E0 |
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| 372 | #define ACP_SCRATCH_REG_57 0x12500E4 |
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| 373 | #define ACP_SCRATCH_REG_58 0x12500E8 |
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| 374 | #define ACP_SCRATCH_REG_59 0x12500EC |
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| 375 | #define ACP_SCRATCH_REG_60 0x12500F0 |
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| 376 | #define ACP_SCRATCH_REG_61 0x12500F4 |
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| 377 | #define ACP_SCRATCH_REG_62 0x12500F8 |
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| 378 | #define ACP_SCRATCH_REG_63 0x12500FC |
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| 379 | #define ACP_SCRATCH_REG_64 0x1250100 |
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| 380 | #define ACP_SCRATCH_REG_65 0x1250104 |
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| 381 | #define ACP_SCRATCH_REG_66 0x1250108 |
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| 382 | #define ACP_SCRATCH_REG_67 0x125010C |
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| 383 | #define ACP_SCRATCH_REG_68 0x1250110 |
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| 384 | #define ACP_SCRATCH_REG_69 0x1250114 |
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| 385 | #define ACP_SCRATCH_REG_70 0x1250118 |
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| 386 | #define ACP_SCRATCH_REG_71 0x125011C |
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| 387 | #define ACP_SCRATCH_REG_72 0x1250120 |
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| 388 | #define ACP_SCRATCH_REG_73 0x1250124 |
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| 389 | #define ACP_SCRATCH_REG_74 0x1250128 |
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| 390 | #define ACP_SCRATCH_REG_75 0x125012C |
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| 391 | #define ACP_SCRATCH_REG_76 0x1250130 |
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| 392 | #define ACP_SCRATCH_REG_77 0x1250134 |
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| 393 | #define ACP_SCRATCH_REG_78 0x1250138 |
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| 394 | #define ACP_SCRATCH_REG_79 0x125013C |
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| 395 | #define ACP_SCRATCH_REG_80 0x1250140 |
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| 396 | #define ACP_SCRATCH_REG_81 0x1250144 |
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| 397 | #define ACP_SCRATCH_REG_82 0x1250148 |
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| 398 | #define ACP_SCRATCH_REG_83 0x125014C |
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| 399 | #define ACP_SCRATCH_REG_84 0x1250150 |
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| 400 | #define ACP_SCRATCH_REG_85 0x1250154 |
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| 401 | #define ACP_SCRATCH_REG_86 0x1250158 |
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| 402 | #define ACP_SCRATCH_REG_87 0x125015C |
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| 403 | #define ACP_SCRATCH_REG_88 0x1250160 |
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| 404 | #define ACP_SCRATCH_REG_89 0x1250164 |
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| 405 | #define ACP_SCRATCH_REG_90 0x1250168 |
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| 406 | #define ACP_SCRATCH_REG_91 0x125016C |
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| 407 | #define ACP_SCRATCH_REG_92 0x1250170 |
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| 408 | #define ACP_SCRATCH_REG_93 0x1250174 |
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| 409 | #define ACP_SCRATCH_REG_94 0x1250178 |
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| 410 | #define ACP_SCRATCH_REG_95 0x125017C |
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| 411 | #define ACP_SCRATCH_REG_96 0x1250180 |
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| 412 | #define ACP_SCRATCH_REG_97 0x1250184 |
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| 413 | #define ACP_SCRATCH_REG_98 0x1250188 |
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| 414 | #define ACP_SCRATCH_REG_99 0x125018C |
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| 415 | #define ACP_SCRATCH_REG_100 0x1250190 |
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| 416 | #define ACP_SCRATCH_REG_101 0x1250194 |
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| 417 | #define ACP_SCRATCH_REG_102 0x1250198 |
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| 418 | #define ACP_SCRATCH_REG_103 0x125019C |
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| 419 | #define ACP_SCRATCH_REG_104 0x12501A0 |
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| 420 | #define ACP_SCRATCH_REG_105 0x12501A4 |
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| 421 | #define ACP_SCRATCH_REG_106 0x12501A8 |
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| 422 | #define ACP_SCRATCH_REG_107 0x12501AC |
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| 423 | #define ACP_SCRATCH_REG_108 0x12501B0 |
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| 424 | #define ACP_SCRATCH_REG_109 0x12501B4 |
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| 425 | #define ACP_SCRATCH_REG_110 0x12501B8 |
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| 426 | #define ACP_SCRATCH_REG_111 0x12501BC |
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| 427 | #define ACP_SCRATCH_REG_112 0x12501C0 |
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| 428 | #define ACP_SCRATCH_REG_113 0x12501C4 |
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| 429 | #define ACP_SCRATCH_REG_114 0x12501C8 |
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| 430 | #define ACP_SCRATCH_REG_115 0x12501CC |
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| 431 | #define ACP_SCRATCH_REG_116 0x12501D0 |
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| 432 | #define ACP_SCRATCH_REG_117 0x12501D4 |
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| 433 | #define ACP_SCRATCH_REG_118 0x12501D8 |
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| 434 | #define ACP_SCRATCH_REG_119 0x12501DC |
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| 435 | #define ACP_SCRATCH_REG_120 0x12501E0 |
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| 436 | #define ACP_SCRATCH_REG_121 0x12501E4 |
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| 437 | #define ACP_SCRATCH_REG_122 0x12501E8 |
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| 438 | #define ACP_SCRATCH_REG_123 0x12501EC |
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| 439 | #define ACP_SCRATCH_REG_124 0x12501F0 |
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| 440 | #define ACP_SCRATCH_REG_125 0x12501F4 |
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| 441 | #define ACP_SCRATCH_REG_126 0x12501F8 |
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| 442 | #define ACP_SCRATCH_REG_127 0x12501FC |
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| 443 | #define ACP_SCRATCH_REG_128 0x1250200 |
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| 444 | #endif |
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| 445 | |
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