| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ATMEL_CLASSD_H_ |
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| 3 | #define __ATMEL_CLASSD_H_ |
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| 4 | |
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| 5 | #define CLASSD_CR 0x00000000 |
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| 6 | #define CLASSD_CR_RESET 0x1 |
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| 7 | |
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| 8 | #define CLASSD_MR 0x00000004 |
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| 9 | |
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| 10 | #define CLASSD_MR_LEN_DIS 0x0 |
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| 11 | #define CLASSD_MR_LEN_EN 0x1 |
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| 12 | #define CLASSD_MR_LEN_MASK (0x1 << 0) |
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| 13 | #define CLASSD_MR_LEN_SHIFT (0) |
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| 14 | |
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| 15 | #define CLASSD_MR_LMUTE_DIS 0x0 |
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| 16 | #define CLASSD_MR_LMUTE_EN 0x1 |
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| 17 | #define CLASSD_MR_LMUTE_SHIFT (0x1) |
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| 18 | #define CLASSD_MR_LMUTE_MASK (0x1 << 1) |
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| 19 | |
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| 20 | #define CLASSD_MR_REN_DIS 0x0 |
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| 21 | #define CLASSD_MR_REN_EN 0x1 |
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| 22 | #define CLASSD_MR_REN_MASK (0x1 << 4) |
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| 23 | #define CLASSD_MR_REN_SHIFT (4) |
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| 24 | |
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| 25 | #define CLASSD_MR_RMUTE_DIS 0x0 |
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| 26 | #define CLASSD_MR_RMUTE_EN 0x1 |
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| 27 | #define CLASSD_MR_RMUTE_SHIFT (0x5) |
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| 28 | #define CLASSD_MR_RMUTE_MASK (0x1 << 5) |
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| 29 | |
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| 30 | #define CLASSD_MR_PWMTYP_SINGLE 0x0 |
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| 31 | #define CLASSD_MR_PWMTYP_DIFF 0x1 |
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| 32 | #define CLASSD_MR_PWMTYP_MASK (0x1 << 8) |
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| 33 | #define CLASSD_MR_PWMTYP_SHIFT (8) |
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| 34 | |
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| 35 | #define CLASSD_MR_NON_OVERLAP_DIS 0x0 |
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| 36 | #define CLASSD_MR_NON_OVERLAP_EN 0x1 |
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| 37 | #define CLASSD_MR_NON_OVERLAP_MASK (0x1 << 16) |
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| 38 | #define CLASSD_MR_NON_OVERLAP_SHIFT (16) |
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| 39 | |
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| 40 | #define CLASSD_MR_NOVR_VAL_5NS 0x0 |
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| 41 | #define CLASSD_MR_NOVR_VAL_10NS 0x1 |
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| 42 | #define CLASSD_MR_NOVR_VAL_15NS 0x2 |
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| 43 | #define CLASSD_MR_NOVR_VAL_20NS 0x3 |
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| 44 | #define CLASSD_MR_NOVR_VAL_MASK (0x3 << 20) |
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| 45 | #define CLASSD_MR_NOVR_VAL_SHIFT (20) |
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| 46 | |
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| 47 | #define CLASSD_INTPMR 0x00000008 |
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| 48 | |
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| 49 | #define CLASSD_INTPMR_ATTL_MASK (0x3f << 0) |
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| 50 | #define CLASSD_INTPMR_ATTL_SHIFT (0) |
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| 51 | #define CLASSD_INTPMR_ATTR_MASK (0x3f << 8) |
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| 52 | #define CLASSD_INTPMR_ATTR_SHIFT (8) |
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| 53 | |
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| 54 | #define CLASSD_INTPMR_DSP_CLK_FREQ_12M288 0x0 |
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| 55 | #define CLASSD_INTPMR_DSP_CLK_FREQ_11M2896 0x1 |
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| 56 | #define CLASSD_INTPMR_DSP_CLK_FREQ_MASK (0x1 << 16) |
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| 57 | #define CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT (16) |
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| 58 | |
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| 59 | #define CLASSD_INTPMR_DEEMP_DIS 0x0 |
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| 60 | #define CLASSD_INTPMR_DEEMP_EN 0x1 |
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| 61 | #define CLASSD_INTPMR_DEEMP_MASK (0x1 << 18) |
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| 62 | #define CLASSD_INTPMR_DEEMP_SHIFT (18) |
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| 63 | |
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| 64 | #define CLASSD_INTPMR_SWAP_LEFT_ON_LSB 0x0 |
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| 65 | #define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB 0x1 |
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| 66 | #define CLASSD_INTPMR_SWAP_MASK (0x1 << 19) |
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| 67 | #define CLASSD_INTPMR_SWAP_SHIFT (19) |
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| 68 | |
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| 69 | #define CLASSD_INTPMR_FRAME_8K 0x0 |
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| 70 | #define CLASSD_INTPMR_FRAME_16K 0x1 |
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| 71 | #define CLASSD_INTPMR_FRAME_32K 0x2 |
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| 72 | #define CLASSD_INTPMR_FRAME_48K 0x3 |
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| 73 | #define CLASSD_INTPMR_FRAME_96K 0x4 |
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| 74 | #define CLASSD_INTPMR_FRAME_22K 0x5 |
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| 75 | #define CLASSD_INTPMR_FRAME_44K 0x6 |
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| 76 | #define CLASSD_INTPMR_FRAME_88K 0x7 |
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| 77 | #define CLASSD_INTPMR_FRAME_MASK (0x7 << 20) |
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| 78 | #define CLASSD_INTPMR_FRAME_SHIFT (20) |
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| 79 | |
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| 80 | #define CLASSD_INTPMR_EQCFG_FLAT 0x0 |
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| 81 | #define CLASSD_INTPMR_EQCFG_B_BOOST_12 0x1 |
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| 82 | #define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2 |
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| 83 | #define CLASSD_INTPMR_EQCFG_B_CUT_12 0x3 |
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| 84 | #define CLASSD_INTPMR_EQCFG_B_CUT_6 0x4 |
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| 85 | #define CLASSD_INTPMR_EQCFG_M_BOOST_3 0x5 |
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| 86 | #define CLASSD_INTPMR_EQCFG_M_BOOST_8 0x6 |
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| 87 | #define CLASSD_INTPMR_EQCFG_M_CUT_3 0x7 |
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| 88 | #define CLASSD_INTPMR_EQCFG_M_CUT_8 0x8 |
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| 89 | #define CLASSD_INTPMR_EQCFG_T_BOOST_12 0x9 |
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| 90 | #define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa |
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| 91 | #define CLASSD_INTPMR_EQCFG_T_CUT_12 0xb |
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| 92 | #define CLASSD_INTPMR_EQCFG_T_CUT_6 0xc |
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| 93 | #define CLASSD_INTPMR_EQCFG_SHIFT (24) |
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| 94 | |
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| 95 | #define CLASSD_INTPMR_MONO_DIS 0x0 |
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| 96 | #define CLASSD_INTPMR_MONO_EN 0x1 |
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| 97 | #define CLASSD_INTPMR_MONO_MASK (0x1 << 28) |
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| 98 | #define CLASSD_INTPMR_MONO_SHIFT (28) |
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| 99 | |
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| 100 | #define CLASSD_INTPMR_MONO_MODE_MIX 0x0 |
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| 101 | #define CLASSD_INTPMR_MONO_MODE_SAT 0x1 |
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| 102 | #define CLASSD_INTPMR_MONO_MODE_LEFT 0x2 |
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| 103 | #define CLASSD_INTPMR_MONO_MODE_RIGHT 0x3 |
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| 104 | #define CLASSD_INTPMR_MONO_MODE_MASK (0x3 << 29) |
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| 105 | #define CLASSD_INTPMR_MONO_MODE_SHIFT (29) |
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| 106 | |
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| 107 | #define CLASSD_INTSR 0x0000000c |
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| 108 | |
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| 109 | #define CLASSD_THR 0x00000010 |
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| 110 | |
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| 111 | #define CLASSD_IER 0x00000014 |
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| 112 | |
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| 113 | #define CLASSD_IDR 0x00000018 |
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| 114 | |
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| 115 | #define CLASSD_IMR 0x0000001c |
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| 116 | |
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| 117 | #define CLASSD_ISR 0x00000020 |
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| 118 | |
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| 119 | #define CLASSD_WPMR 0x000000e4 |
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| 120 | |
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| 121 | #endif |
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| 122 | |
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