| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ATMEL_PDMIC_H_ |
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| 3 | #define __ATMEL_PDMIC_H_ |
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| 4 | |
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| 5 | #include <linux/bitops.h> |
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| 6 | |
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| 7 | #define PDMIC_CR 0x00000000 |
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| 8 | |
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| 9 | #define PDMIC_CR_SWRST 0x1 |
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| 10 | #define PDMIC_CR_SWRST_MASK BIT(0) |
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| 11 | #define PDMIC_CR_SWRST_SHIFT (0) |
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| 12 | |
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| 13 | #define PDMIC_CR_ENPDM_DIS 0x0 |
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| 14 | #define PDMIC_CR_ENPDM_EN 0x1 |
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| 15 | #define PDMIC_CR_ENPDM_MASK BIT(4) |
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| 16 | #define PDMIC_CR_ENPDM_SHIFT (4) |
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| 17 | |
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| 18 | #define PDMIC_MR 0x00000004 |
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| 19 | |
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| 20 | #define PDMIC_MR_CLKS_PCK 0x0 |
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| 21 | #define PDMIC_MR_CLKS_GCK 0x1 |
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| 22 | #define PDMIC_MR_CLKS_MASK BIT(4) |
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| 23 | #define PDMIC_MR_CLKS_SHIFT (4) |
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| 24 | |
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| 25 | #define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8) |
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| 26 | #define PDMIC_MR_PRESCAL_SHIFT (8) |
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| 27 | |
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| 28 | #define PDMIC_CDR 0x00000014 |
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| 29 | |
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| 30 | #define PDMIC_IER 0x00000018 |
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| 31 | #define PDMIC_IER_OVRE BIT(25) |
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| 32 | |
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| 33 | #define PDMIC_IDR 0x0000001c |
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| 34 | #define PDMIC_IDR_OVRE BIT(25) |
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| 35 | |
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| 36 | #define PDMIC_IMR 0x00000020 |
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| 37 | |
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| 38 | #define PDMIC_ISR 0x00000024 |
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| 39 | #define PDMIC_ISR_OVRE BIT(25) |
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| 40 | |
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| 41 | #define PDMIC_DSPR0 0x00000058 |
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| 42 | |
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| 43 | #define PDMIC_DSPR0_HPFBYP_DIS 0x1 |
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| 44 | #define PDMIC_DSPR0_HPFBYP_EN 0x0 |
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| 45 | #define PDMIC_DSPR0_HPFBYP_MASK BIT(1) |
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| 46 | #define PDMIC_DSPR0_HPFBYP_SHIFT (1) |
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| 47 | |
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| 48 | #define PDMIC_DSPR0_SINBYP_DIS 0x1 |
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| 49 | #define PDMIC_DSPR0_SINBYP_EN 0x0 |
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| 50 | #define PDMIC_DSPR0_SINBYP_MASK BIT(2) |
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| 51 | #define PDMIC_DSPR0_SINBYP_SHIFT (2) |
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| 52 | |
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| 53 | #define PDMIC_DSPR0_SIZE_16_BITS 0x0 |
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| 54 | #define PDMIC_DSPR0_SIZE_32_BITS 0x1 |
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| 55 | #define PDMIC_DSPR0_SIZE_MASK BIT(3) |
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| 56 | #define PDMIC_DSPR0_SIZE_SHIFT (3) |
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| 57 | |
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| 58 | #define PDMIC_DSPR0_OSR_128 0x0 |
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| 59 | #define PDMIC_DSPR0_OSR_64 0x1 |
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| 60 | #define PDMIC_DSPR0_OSR_MASK GENMASK(6, 4) |
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| 61 | #define PDMIC_DSPR0_OSR_SHIFT (4) |
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| 62 | |
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| 63 | #define PDMIC_DSPR0_SCALE_MASK GENMASK(11, 8) |
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| 64 | #define PDMIC_DSPR0_SCALE_SHIFT (8) |
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| 65 | |
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| 66 | #define PDMIC_DSPR0_SHIFT_MASK GENMASK(15, 12) |
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| 67 | #define PDMIC_DSPR0_SHIFT_SHIFT (12) |
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| 68 | |
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| 69 | #define PDMIC_DSPR1 0x0000005c |
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| 70 | |
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| 71 | #define PDMIC_DSPR1_DGAIN_MASK GENMASK(14, 0) |
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| 72 | #define PDMIC_DSPR1_DGAIN_SHIFT (0) |
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| 73 | |
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| 74 | #define PDMIC_DSPR1_OFFSET_MASK GENMASK(31, 16) |
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| 75 | #define PDMIC_DSPR1_OFFSET_SHIFT (16) |
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| 76 | |
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| 77 | #define PDMIC_WPMR 0x000000e4 |
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| 78 | |
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| 79 | #define PDMIC_WPSR 0x000000e8 |
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| 80 | |
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| 81 | #endif |
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| 82 | |
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