| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
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| 2 | // linux/sound/soc/bcm/bcm63xx-i2s.h |
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| 3 | // Copyright (c) 2020 Broadcom Corporation |
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| 4 | // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com> |
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| 5 | |
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| 6 | #ifndef __BCM63XX_I2S_H |
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| 7 | #define __BCM63XX_I2S_H |
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| 8 | |
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| 9 | #define I2S_DESC_FIFO_DEPTH 8 |
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| 10 | #define I2S_MISC_CFG (0x003C) |
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| 11 | #define I2S_PAD_LVL_LOOP_DIS_MASK (1 << 2) |
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| 12 | #define I2S_PAD_LVL_LOOP_DIS_ENABLE I2S_PAD_LVL_LOOP_DIS_MASK |
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| 13 | |
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| 14 | #define I2S_TX_ENABLE_MASK (1 << 31) |
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| 15 | #define I2S_TX_ENABLE I2S_TX_ENABLE_MASK |
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| 16 | #define I2S_TX_OUT_R (1 << 19) |
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| 17 | #define I2S_TX_DATA_ALIGNMENT (1 << 2) |
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| 18 | #define I2S_TX_DATA_ENABLE (1 << 1) |
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| 19 | #define I2S_TX_CLOCK_ENABLE (1 << 0) |
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| 20 | |
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| 21 | #define I2S_TX_DESC_OFF_LEVEL_SHIFT 12 |
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| 22 | #define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT) |
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| 23 | #define I2S_TX_DESC_IFF_LEVEL_SHIFT 8 |
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| 24 | #define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT) |
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| 25 | #define I2S_TX_DESC_OFF_INTR_EN_MSK (1 << 1) |
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| 26 | #define I2S_TX_DESC_OFF_INTR_EN I2S_TX_DESC_OFF_INTR_EN_MSK |
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| 27 | |
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| 28 | #define I2S_TX_CFG (0x0000) |
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| 29 | #define I2S_TX_IRQ_CTL (0x0004) |
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| 30 | #define I2S_TX_IRQ_EN (0x0008) |
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| 31 | #define I2S_TX_IRQ_IFF_THLD (0x000c) |
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| 32 | #define I2S_TX_IRQ_OFF_THLD (0x0010) |
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| 33 | #define I2S_TX_DESC_IFF_ADDR (0x0014) |
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| 34 | #define I2S_TX_DESC_IFF_LEN (0x0018) |
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| 35 | #define I2S_TX_DESC_OFF_ADDR (0x001C) |
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| 36 | #define I2S_TX_DESC_OFF_LEN (0x0020) |
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| 37 | #define I2S_TX_CFG_2 (0x0024) |
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| 38 | #define I2S_TX_SLAVE_MODE_SHIFT 13 |
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| 39 | #define I2S_TX_SLAVE_MODE_MASK (1 << I2S_TX_SLAVE_MODE_SHIFT) |
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| 40 | #define I2S_TX_SLAVE_MODE I2S_TX_SLAVE_MODE_MASK |
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| 41 | #define I2S_TX_MASTER_MODE 0 |
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| 42 | #define I2S_TX_INTR_MASK 0x0F |
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| 43 | |
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| 44 | #define I2S_RX_ENABLE_MASK (1 << 31) |
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| 45 | #define I2S_RX_ENABLE I2S_RX_ENABLE_MASK |
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| 46 | #define I2S_RX_IN_R (1 << 19) |
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| 47 | #define I2S_RX_DATA_ALIGNMENT (1 << 2) |
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| 48 | #define I2S_RX_CLOCK_ENABLE (1 << 0) |
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| 49 | |
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| 50 | #define I2S_RX_DESC_OFF_LEVEL_SHIFT 12 |
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| 51 | #define I2S_RX_DESC_OFF_LEVEL_MASK (0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT) |
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| 52 | #define I2S_RX_DESC_IFF_LEVEL_SHIFT 8 |
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| 53 | #define I2S_RX_DESC_IFF_LEVEL_MASK (0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT) |
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| 54 | #define I2S_RX_DESC_OFF_INTR_EN_MSK (1 << 1) |
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| 55 | #define I2S_RX_DESC_OFF_INTR_EN I2S_RX_DESC_OFF_INTR_EN_MSK |
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| 56 | |
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| 57 | #define I2S_RX_CFG (0x0040) /* 20c0 */ |
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| 58 | #define I2S_RX_IRQ_CTL (0x0044) |
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| 59 | #define I2S_RX_IRQ_EN (0x0048) |
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| 60 | #define I2S_RX_IRQ_IFF_THLD (0x004C) |
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| 61 | #define I2S_RX_IRQ_OFF_THLD (0x0050) |
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| 62 | #define I2S_RX_DESC_IFF_ADDR (0x0054) |
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| 63 | #define I2S_RX_DESC_IFF_LEN (0x0058) |
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| 64 | #define I2S_RX_DESC_OFF_ADDR (0x005C) |
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| 65 | #define I2S_RX_DESC_OFF_LEN (0x0060) |
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| 66 | #define I2S_RX_CFG_2 (0x0064) |
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| 67 | #define I2S_RX_SLAVE_MODE_SHIFT 13 |
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| 68 | #define I2S_RX_SLAVE_MODE_MASK (1 << I2S_RX_SLAVE_MODE_SHIFT) |
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| 69 | #define I2S_RX_SLAVE_MODE I2S_RX_SLAVE_MODE_MASK |
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| 70 | #define I2S_RX_MASTER_MODE 0 |
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| 71 | #define I2S_RX_INTR_MASK 0x0F |
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| 72 | |
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| 73 | #define I2S_REG_MAX 0x007C |
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| 74 | |
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| 75 | struct bcm_i2s_priv { |
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| 76 | struct device *dev; |
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| 77 | struct regmap *regmap_i2s; |
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| 78 | struct clk *i2s_clk; |
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| 79 | struct snd_pcm_substream *play_substream; |
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| 80 | struct snd_pcm_substream *capture_substream; |
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| 81 | struct i2s_dma_desc *play_dma_desc; |
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| 82 | struct i2s_dma_desc *capture_dma_desc; |
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| 83 | }; |
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| 84 | |
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| 85 | extern int bcm63xx_soc_platform_probe(struct platform_device *pdev, |
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| 86 | struct bcm_i2s_priv *i2s_priv); |
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| 87 | extern int bcm63xx_soc_platform_remove(struct platform_device *pdev); |
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| 88 | |
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| 89 | #endif |
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| 90 | |
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