| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ADAU1373_H__ |
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| 3 | #define __ADAU1373_H__ |
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| 4 | |
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| 5 | enum adau1373_pll_src { |
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| 6 | ADAU1373_PLL_SRC_MCLK1 = 0, |
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| 7 | ADAU1373_PLL_SRC_BCLK1 = 1, |
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| 8 | ADAU1373_PLL_SRC_BCLK2 = 2, |
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| 9 | ADAU1373_PLL_SRC_BCLK3 = 3, |
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| 10 | ADAU1373_PLL_SRC_LRCLK1 = 4, |
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| 11 | ADAU1373_PLL_SRC_LRCLK2 = 5, |
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| 12 | ADAU1373_PLL_SRC_LRCLK3 = 6, |
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| 13 | ADAU1373_PLL_SRC_GPIO1 = 7, |
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| 14 | ADAU1373_PLL_SRC_GPIO2 = 8, |
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| 15 | ADAU1373_PLL_SRC_GPIO3 = 9, |
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| 16 | ADAU1373_PLL_SRC_GPIO4 = 10, |
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| 17 | ADAU1373_PLL_SRC_MCLK2 = 11, |
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| 18 | }; |
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| 19 | |
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| 20 | enum adau1373_pll { |
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| 21 | ADAU1373_PLL1 = 0, |
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| 22 | ADAU1373_PLL2 = 1, |
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| 23 | }; |
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| 24 | |
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| 25 | enum adau1373_clk_src { |
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| 26 | ADAU1373_CLK_SRC_PLL1 = 0, |
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| 27 | ADAU1373_CLK_SRC_PLL2 = 1, |
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| 28 | }; |
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| 29 | |
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| 30 | #endif |
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| 31 | |
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