| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Audio driver for AK4458 |
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| 4 | * |
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| 5 | * Copyright (C) 2016 Asahi Kasei Microdevices Corporation |
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| 6 | * Copyright 2018 NXP |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _AK4458_H |
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| 10 | #define _AK4458_H |
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| 11 | |
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| 12 | #include <linux/regmap.h> |
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| 13 | |
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| 14 | /* Settings */ |
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| 15 | |
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| 16 | #define AK4458_00_CONTROL1 0x00 |
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| 17 | #define AK4458_01_CONTROL2 0x01 |
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| 18 | #define AK4458_02_CONTROL3 0x02 |
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| 19 | #define AK4458_03_LCHATT 0x03 |
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| 20 | #define AK4458_04_RCHATT 0x04 |
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| 21 | #define AK4458_05_CONTROL4 0x05 |
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| 22 | #define AK4458_06_DSD1 0x06 |
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| 23 | #define AK4458_07_CONTROL5 0x07 |
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| 24 | #define AK4458_08_SOUND_CONTROL 0x08 |
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| 25 | #define AK4458_09_DSD2 0x09 |
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| 26 | #define AK4458_0A_CONTROL6 0x0A |
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| 27 | #define AK4458_0B_CONTROL7 0x0B |
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| 28 | #define AK4458_0C_CONTROL8 0x0C |
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| 29 | #define AK4458_0D_CONTROL9 0x0D |
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| 30 | #define AK4458_0E_CONTROL10 0x0E |
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| 31 | #define AK4458_0F_L2CHATT 0x0F |
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| 32 | #define AK4458_10_R2CHATT 0x10 |
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| 33 | #define AK4458_11_L3CHATT 0x11 |
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| 34 | #define AK4458_12_R3CHATT 0x12 |
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| 35 | #define AK4458_13_L4CHATT 0x13 |
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| 36 | #define AK4458_14_R4CHATT 0x14 |
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| 37 | |
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| 38 | /* Bitfield Definitions */ |
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| 39 | |
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| 40 | /* AK4458_00_CONTROL1 (0x00) Fields |
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| 41 | * Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 |
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| 42 | * 00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN |
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| 43 | */ |
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| 44 | |
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| 45 | /* Digital Filter (SD, SLOW, SSLOW) */ |
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| 46 | #define AK4458_SD_MASK GENMASK(5, 5) |
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| 47 | #define AK4458_SLOW_MASK GENMASK(0, 0) |
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| 48 | #define AK4458_SSLOW_MASK GENMASK(0, 0) |
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| 49 | |
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| 50 | /* DIF2 1 0 |
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| 51 | * x 1 0 MSB justified Figure 3 (default) |
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| 52 | * x 1 1 I2S Compliment Figure 4 |
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| 53 | */ |
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| 54 | #define AK4458_DIF_SHIFT 1 |
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| 55 | #define AK4458_DIF_MASK GENMASK(3, 1) |
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| 56 | |
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| 57 | #define AK4458_DIF_16BIT_LSB (0 << 1) |
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| 58 | #define AK4458_DIF_24BIT_I2S (3 << 1) |
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| 59 | #define AK4458_DIF_32BIT_LSB (5 << 1) |
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| 60 | #define AK4458_DIF_32BIT_MSB (6 << 1) |
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| 61 | #define AK4458_DIF_32BIT_I2S (7 << 1) |
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| 62 | |
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| 63 | /* AK4458_00_CONTROL1 (0x00) D0 bit */ |
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| 64 | #define AK4458_RSTN_MASK GENMASK(0, 0) |
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| 65 | #define AK4458_RSTN (0x1 << 0) |
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| 66 | |
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| 67 | /* AK4458_0A_CONTROL6 Mode bits */ |
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| 68 | #define AK4458_MODE_SHIFT 6 |
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| 69 | #define AK4458_MODE_MASK GENMASK(7, 6) |
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| 70 | #define AK4458_MODE_NORMAL (0 << AK4458_MODE_SHIFT) |
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| 71 | #define AK4458_MODE_TDM128 (1 << AK4458_MODE_SHIFT) |
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| 72 | #define AK4458_MODE_TDM256 (2 << AK4458_MODE_SHIFT) |
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| 73 | #define AK4458_MODE_TDM512 (3 << AK4458_MODE_SHIFT) |
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| 74 | |
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| 75 | /* DAC Digital attenuator transition time setting |
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| 76 | * Table 19 |
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| 77 | * Mode ATS1 ATS2 ATT speed |
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| 78 | * 0 0 0 4080/fs |
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| 79 | * 1 0 1 2040/fs |
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| 80 | * 2 1 0 510/fs |
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| 81 | * 3 1 1 255/fs |
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| 82 | * */ |
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| 83 | #define AK4458_ATS_SHIFT 6 |
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| 84 | #define AK4458_ATS_MASK GENMASK(7, 6) |
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| 85 | #define AK4458_DCHAIN_MASK (0x1 << 1) |
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| 86 | |
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| 87 | #define AK4458_DSDSEL_MASK (0x1 << 0) |
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| 88 | #define AK4458_DP_MASK (0x1 << 7) |
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| 89 | |
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| 90 | #endif |
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| 91 | |
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