| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * cs35l33.h -- CS35L33 ALSA SoC audio driver |
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| 4 | * |
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| 5 | * Copyright 2016 Cirrus Logic, Inc. |
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| 6 | * |
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| 7 | * Author: Paul Handrigan <paul.handrigan@cirrus.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __CS35L33_H__ |
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| 11 | #define __CS35L33_H__ |
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| 12 | |
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| 13 | #define CS35L33_CHIP_ID 0x00035A33 |
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| 14 | #define CS35L33_DEVID_AB 0x01 /* Device ID A & B [RO] */ |
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| 15 | #define CS35L33_DEVID_CD 0x02 /* Device ID C & D [RO] */ |
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| 16 | #define CS35L33_DEVID_E 0x03 /* Device ID E [RO] */ |
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| 17 | #define CS35L33_FAB_ID 0x04 /* Fab ID [RO] */ |
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| 18 | #define CS35L33_REV_ID 0x05 /* Revision ID [RO] */ |
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| 19 | #define CS35L33_PWRCTL1 0x06 /* Power Ctl 1 */ |
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| 20 | #define CS35L33_PWRCTL2 0x07 /* Power Ctl 2 */ |
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| 21 | #define CS35L33_CLK_CTL 0x08 /* Clock Ctl */ |
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| 22 | #define CS35L33_BST_PEAK_CTL 0x09 /* Max Current for Boost */ |
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| 23 | #define CS35L33_PROTECT_CTL 0x0A /* Amp Protection Parameters */ |
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| 24 | #define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */ |
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| 25 | #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */ |
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| 26 | #define CS35L33_ADSP_CTL 0x0D /* Serial Port Control */ |
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| 27 | #define CS35L33_ADC_CTL 0x0E /* ADC Control */ |
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| 28 | #define CS35L33_DAC_CTL 0x0F /* DAC Control */ |
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| 29 | #define CS35L33_DIG_VOL_CTL 0x10 /* Digital Volume CTL */ |
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| 30 | #define CS35L33_CLASSD_CTL 0x11 /* Class D Amp CTL */ |
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| 31 | #define CS35L33_AMP_CTL 0x12 /* Amp Gain/Protecton Release CTL */ |
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| 32 | #define CS35L33_INT_MASK_1 0x13 /* Interrupt Mask 1 */ |
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| 33 | #define CS35L33_INT_MASK_2 0x14 /* Interrupt Mask 2 */ |
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| 34 | #define CS35L33_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */ |
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| 35 | #define CS35L33_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */ |
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| 36 | #define CS35L33_DIAG_LOCK 0x17 /* Diagnostic Mode Register Lock */ |
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| 37 | #define CS35L33_DIAG_CTRL_1 0x18 /* Diagnostic Mode Register Control */ |
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| 38 | #define CS35L33_DIAG_CTRL_2 0x19 /* Diagnostic Mode Register Control 2 */ |
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| 39 | #define CS35L33_HG_MEMLDO_CTL 0x23 /* H/G Memory/LDO CTL */ |
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| 40 | #define CS35L33_HG_REL_RATE 0x24 /* H/G Release Rate */ |
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| 41 | #define CS35L33_LDO_DEL 0x25 /* LDO Entry Delay/VPhg Control 1 */ |
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| 42 | #define CS35L33_HG_HEAD 0x29 /* H/G Headroom */ |
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| 43 | #define CS35L33_HG_EN 0x2A /* H/G Enable/VPhg CNT2 */ |
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| 44 | #define CS35L33_TX_VMON 0x2D /* TDM TX Control 1 (VMON) */ |
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| 45 | #define CS35L33_TX_IMON 0x2E /* TDM TX Control 2 (IMON) */ |
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| 46 | #define CS35L33_TX_VPMON 0x2F /* TDM TX Control 3 (VPMON) */ |
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| 47 | #define CS35L33_TX_VBSTMON 0x30 /* TDM TX Control 4 (VBSTMON) */ |
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| 48 | #define CS35L33_TX_FLAG 0x31 /* TDM TX Control 5 (FLAG) */ |
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| 49 | #define CS35L33_TX_EN1 0x32 /* TDM TX Enable 1 */ |
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| 50 | #define CS35L33_TX_EN2 0x33 /* TDM TX Enable 2 */ |
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| 51 | #define CS35L33_TX_EN3 0x34 /* TDM TX Enable 3 */ |
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| 52 | #define CS35L33_TX_EN4 0x35 /* TDM TX Enable 4 */ |
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| 53 | #define CS35L33_RX_AUD 0x36 /* TDM RX Control 1 */ |
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| 54 | #define CS35L33_RX_SPLY 0x37 /* TDM RX Control 2 */ |
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| 55 | #define CS35L33_RX_ALIVE 0x38 /* TDM RX Control 3 */ |
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| 56 | #define CS35L33_BST_CTL4 0x39 /* Boost Converter Control 4 */ |
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| 57 | #define CS35L33_HG_STATUS 0x3F /* H/G Status */ |
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| 58 | #define CS35L33_MAX_REGISTER 0x59 |
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| 59 | |
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| 60 | #define CS35L33_MCLK_5644 5644800 |
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| 61 | #define CS35L33_MCLK_6144 6144000 |
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| 62 | #define CS35L33_MCLK_6 6000000 |
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| 63 | #define CS35L33_MCLK_11289 11289600 |
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| 64 | #define CS35L33_MCLK_12 12000000 |
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| 65 | #define CS35L33_MCLK_12288 12288000 |
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| 66 | |
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| 67 | /* CS35L33_PWRCTL1 */ |
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| 68 | #define CS35L33_PDN_AMP (1 << 7) |
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| 69 | #define CS35L33_PDN_BST (1 << 2) |
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| 70 | #define CS35L33_PDN_ALL 1 |
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| 71 | |
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| 72 | /* CS35L33_PWRCTL2 */ |
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| 73 | #define CS35L33_PDN_VMON_SHIFT 7 |
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| 74 | #define CS35L33_PDN_VMON (1 << CS35L33_PDN_VMON_SHIFT) |
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| 75 | #define CS35L33_PDN_IMON_SHIFT 6 |
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| 76 | #define CS35L33_PDN_IMON (1 << CS35L33_PDN_IMON_SHIFT) |
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| 77 | #define CS35L33_PDN_VPMON_SHIFT 5 |
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| 78 | #define CS35L33_PDN_VPMON (1 << CS35L33_PDN_VPMON_SHIFT) |
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| 79 | #define CS35L33_PDN_VBSTMON_SHIFT 4 |
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| 80 | #define CS35L33_PDN_VBSTMON (1 << CS35L33_PDN_VBSTMON_SHIFT) |
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| 81 | #define CS35L33_SDOUT_3ST_I2S_SHIFT 3 |
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| 82 | #define CS35L33_SDOUT_3ST_I2S (1 << CS35L33_SDOUT_3ST_I2S_SHIFT) |
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| 83 | #define CS35L33_PDN_SDIN_SHIFT 2 |
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| 84 | #define CS35L33_PDN_SDIN (1 << CS35L33_PDN_SDIN_SHIFT) |
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| 85 | #define CS35L33_PDN_TDM_SHIFT 1 |
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| 86 | #define CS35L33_PDN_TDM (1 << CS35L33_PDN_TDM_SHIFT) |
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| 87 | |
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| 88 | /* CS35L33_CLK_CTL */ |
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| 89 | #define CS35L33_MCLKDIS (1 << 7) |
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| 90 | #define CS35L33_MCLKDIV2 (1 << 6) |
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| 91 | #define CS35L33_SDOUT_3ST_TDM (1 << 5) |
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| 92 | #define CS35L33_INT_FS_RATE (1 << 4) |
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| 93 | #define CS35L33_ADSP_FS 0xF |
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| 94 | |
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| 95 | /* CS35L33_PROTECT_CTL */ |
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| 96 | #define CS35L33_ALIVE_WD_DIS (3 << 2) |
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| 97 | |
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| 98 | /* CS35L33_BST_CTL1 */ |
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| 99 | #define CS35L33_BST_CTL_SRC (1 << 6) |
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| 100 | #define CS35L33_BST_CTL_SHIFT (1 << 5) |
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| 101 | #define CS35L33_BST_CTL_MASK 0x3F |
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| 102 | |
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| 103 | /* CS35L33_BST_CTL2 */ |
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| 104 | #define CS35L33_TDM_WD_SEL (1 << 4) |
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| 105 | #define CS35L33_ALIVE_WD_DIS2 (1 << 3) |
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| 106 | #define CS35L33_VBST_SR_STEP 0x3 |
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| 107 | |
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| 108 | /* CS35L33_ADSP_CTL */ |
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| 109 | #define CS35L33_ADSP_DRIVE (1 << 7) |
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| 110 | #define CS35L33_MS_MASK (1 << 6) |
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| 111 | #define CS35L33_SDIN_LOC (3 << 4) |
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| 112 | #define CS35L33_ALIVE_RATE 0x3 |
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| 113 | |
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| 114 | /* CS35L33_ADC_CTL */ |
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| 115 | #define CS35L33_INV_VMON (1 << 7) |
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| 116 | #define CS35L33_INV_IMON (1 << 6) |
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| 117 | #define CS35L33_ADC_NOTCH_DIS (1 << 5) |
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| 118 | #define CS35L33_IMON_SCALE 0xF |
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| 119 | |
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| 120 | /* CS35L33_DAC_CTL */ |
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| 121 | #define CS35L33_INV_DAC (1 << 7) |
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| 122 | #define CS35L33_DAC_NOTCH_DIS (1 << 5) |
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| 123 | #define CS35L33_DIGSFT (1 << 4) |
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| 124 | #define CS35L33_DSR_RATE 0xF |
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| 125 | |
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| 126 | /* CS35L33_CLASSD_CTL */ |
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| 127 | #define CS35L33_AMP_SD (1 << 6) |
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| 128 | #define CS35L33_AMP_DRV_SEL_SRC (1 << 5) |
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| 129 | #define CS35L33_AMP_DRV_SEL_MASK 0x10 |
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| 130 | #define CS35L33_AMP_DRV_SEL_SHIFT 4 |
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| 131 | #define CS35L33_AMP_CAL (1 << 3) |
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| 132 | #define CS35L33_GAIN_CHG_ZC_MASK 0x04 |
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| 133 | #define CS35L33_GAIN_CHG_ZC_SHIFT 2 |
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| 134 | #define CS35L33_CLASS_D_CTL_MASK 0x3F |
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| 135 | |
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| 136 | /* CS35L33_AMP_CTL */ |
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| 137 | #define CS35L33_AMP_GAIN 0xF0 |
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| 138 | #define CS35L33_CAL_ERR_RLS (1 << 3) |
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| 139 | #define CS35L33_AMP_SHORT_RLS (1 << 2) |
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| 140 | #define CS35L33_OTW_RLS (1 << 1) |
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| 141 | #define CS35L33_OTE_RLS 1 |
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| 142 | |
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| 143 | /* CS35L33_INT_MASK_1 */ |
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| 144 | #define CS35L33_M_CAL_ERR_SHIFT 6 |
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| 145 | #define CS35L33_M_CAL_ERR (1 << CS35L33_M_CAL_ERR_SHIFT) |
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| 146 | #define CS35L33_M_ALIVE_ERR_SHIFT 5 |
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| 147 | #define CS35L33_M_ALIVE_ERR (1 << CS35L33_M_ALIVE_ERR_SHIFT) |
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| 148 | #define CS35L33_M_AMP_SHORT_SHIFT 2 |
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| 149 | #define CS35L33_M_AMP_SHORT (1 << CS35L33_M_AMP_SHORT_SHIFT) |
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| 150 | #define CS35L33_M_OTW_SHIFT 1 |
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| 151 | #define CS35L33_M_OTW (1 << CS35L33_M_OTW_SHIFT) |
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| 152 | #define CS35L33_M_OTE_SHIFT 0 |
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| 153 | #define CS35L33_M_OTE (1 << CS35L33_M_OTE_SHIFT) |
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| 154 | |
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| 155 | /* CS35L33_INT_STATUS_1 */ |
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| 156 | #define CS35L33_CAL_ERR (1 << 6) |
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| 157 | #define CS35L33_ALIVE_ERR (1 << 5) |
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| 158 | #define CS35L33_ADSPCLK_ERR (1 << 4) |
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| 159 | #define CS35L33_MCLK_ERR (1 << 3) |
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| 160 | #define CS35L33_AMP_SHORT (1 << 2) |
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| 161 | #define CS35L33_OTW (1 << 1) |
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| 162 | #define CS35L33_OTE (1 << 0) |
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| 163 | |
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| 164 | /* CS35L33_INT_STATUS_2 */ |
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| 165 | #define CS35L33_VMON_OVFL (1 << 7) |
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| 166 | #define CS35L33_IMON_OVFL (1 << 6) |
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| 167 | #define CS35L33_VPMON_OVFL (1 << 5) |
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| 168 | #define CS35L33_VBSTMON_OVFL (1 << 4) |
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| 169 | #define CS35L33_PDN_DONE 1 |
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| 170 | |
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| 171 | /* CS35L33_BST_CTL4 */ |
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| 172 | #define CS35L33_BST_RGS 0x70 |
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| 173 | #define CS35L33_BST_COEFF3 0xF |
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| 174 | |
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| 175 | /* CS35L33_HG_MEMLDO_CTL */ |
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| 176 | #define CS35L33_MEM_DEPTH_SHIFT 5 |
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| 177 | #define CS35L33_MEM_DEPTH_MASK (0x3 << CS35L33_MEM_DEPTH_SHIFT) |
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| 178 | #define CS35L33_LDO_THLD_SHIFT 1 |
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| 179 | #define CS35L33_LDO_THLD_MASK (0xF << CS35L33_LDO_THLD_SHIFT) |
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| 180 | #define CS35L33_LDO_DISABLE_SHIFT 0 |
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| 181 | #define CS35L33_LDO_DISABLE_MASK (0x1 << CS35L33_LDO_DISABLE_SHIFT) |
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| 182 | |
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| 183 | /* CS35L33_LDO_DEL */ |
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| 184 | #define CS35L33_VP_HG_VA_SHIFT 5 |
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| 185 | #define CS35L33_VP_HG_VA_MASK (0x7 << CS35L33_VP_HG_VA_SHIFT) |
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| 186 | #define CS35L33_LDO_ENTRY_DELAY_SHIFT 2 |
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| 187 | #define CS35L33_LDO_ENTRY_DELAY_MASK (0x7 << CS35L33_LDO_ENTRY_DELAY_SHIFT) |
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| 188 | #define CS35L33_VP_HG_RATE_SHIFT 0 |
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| 189 | #define CS35L33_VP_HG_RATE_MASK (0x3 << CS35L33_VP_HG_RATE_SHIFT) |
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| 190 | |
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| 191 | /* CS35L33_HG_HEAD */ |
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| 192 | #define CS35L33_HD_RM_SHIFT 0 |
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| 193 | #define CS35L33_HD_RM_MASK (0x7F << CS35L33_HD_RM_SHIFT) |
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| 194 | |
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| 195 | /* CS35L33_HG_EN */ |
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| 196 | #define CS35L33_CLASS_HG_ENA_SHIFT 7 |
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| 197 | #define CS35L33_CLASS_HG_EN_MASK (0x1 << CS35L33_CLASS_HG_ENA_SHIFT) |
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| 198 | #define CS35L33_VP_HG_AUTO_SHIFT 6 |
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| 199 | #define CS35L33_VP_HG_AUTO_MASK (0x1 << 6) |
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| 200 | #define CS35L33_VP_HG_SHIFT 0 |
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| 201 | #define CS35L33_VP_HG_MASK (0x1F << CS35L33_VP_HG_SHIFT) |
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| 202 | |
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| 203 | #define CS35L33_RATES (SNDRV_PCM_RATE_8000_48000) |
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| 204 | #define CS35L33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
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| 205 | SNDRV_PCM_FMTBIT_S24_LE) |
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| 206 | |
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| 207 | /* CS35L33_{RX,TX}_X */ |
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| 208 | #define CS35L33_X_STATE_SHIFT 7 |
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| 209 | #define CS35L33_X_STATE (1 << CS35L33_X_STATE_SHIFT) |
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| 210 | #define CS35L33_X_LOC_SHIFT 0 |
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| 211 | #define CS35L33_X_LOC (0x1F << CS35L33_X_LOC_SHIFT) |
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| 212 | |
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| 213 | /* CS35L33_RX_AUD */ |
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| 214 | #define CS35L33_AUDIN_RX_DEPTH_SHIFT 5 |
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| 215 | #define CS35L33_AUDIN_RX_DEPTH (0x7 << CS35L33_AUDIN_RX_DEPTH_SHIFT) |
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| 216 | |
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| 217 | #endif |
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| 218 | |
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