| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * cs4265.h -- CS4265 ALSA SoC audio driver |
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| 4 | * |
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| 5 | * Copyright 2014 Cirrus Logic, Inc. |
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| 6 | * |
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| 7 | * Author: Paul Handrigan <paul.handrigan@cirrus.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __CS4265_H__ |
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| 11 | #define __CS4265_H__ |
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| 12 | |
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| 13 | #define CS4265_CHIP_ID 0x1 |
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| 14 | #define CS4265_CHIP_ID_VAL 0xD0 |
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| 15 | #define CS4265_CHIP_ID_MASK 0xF0 |
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| 16 | #define CS4265_REV_ID_MASK 0x0F |
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| 17 | |
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| 18 | #define CS4265_PWRCTL 0x02 |
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| 19 | #define CS4265_PWRCTL_PDN 1 |
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| 20 | |
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| 21 | #define CS4265_DAC_CTL 0x3 |
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| 22 | #define CS4265_DAC_CTL_MUTE (1 << 2) |
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| 23 | #define CS4265_DAC_CTL_DIF (3 << 4) |
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| 24 | |
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| 25 | #define CS4265_ADC_CTL 0x4 |
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| 26 | #define CS4265_ADC_MASTER 1 |
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| 27 | #define CS4265_ADC_DIF (1 << 4) |
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| 28 | #define CS4265_ADC_FM (3 << 6) |
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| 29 | |
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| 30 | #define CS4265_MCLK_FREQ 0x5 |
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| 31 | #define CS4265_MCLK_FREQ_MASK (7 << 4) |
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| 32 | |
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| 33 | #define CS4265_SIG_SEL 0x6 |
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| 34 | #define CS4265_SIG_SEL_LOOP (1 << 1) |
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| 35 | |
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| 36 | #define CS4265_CHB_PGA_CTL 0x7 |
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| 37 | #define CS4265_CHA_PGA_CTL 0x8 |
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| 38 | |
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| 39 | #define CS4265_ADC_CTL2 0x9 |
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| 40 | |
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| 41 | #define CS4265_DAC_CHA_VOL 0xA |
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| 42 | #define CS4265_DAC_CHB_VOL 0xB |
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| 43 | |
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| 44 | #define CS4265_DAC_CTL2 0xC |
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| 45 | |
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| 46 | #define CS4265_INT_STATUS 0xD |
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| 47 | #define CS4265_INT_MASK 0xE |
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| 48 | #define CS4265_STATUS_MODE_MSB 0xF |
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| 49 | #define CS4265_STATUS_MODE_LSB 0x10 |
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| 50 | |
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| 51 | #define CS4265_SPDIF_CTL1 0x11 |
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| 52 | |
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| 53 | #define CS4265_SPDIF_CTL2 0x12 |
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| 54 | #define CS4265_SPDIF_CTL2_MUTE (1 << 4) |
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| 55 | #define CS4265_SPDIF_CTL2_DIF (3 << 6) |
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| 56 | |
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| 57 | #define CS4265_C_DATA_BUFF 0x13 |
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| 58 | #define CS4265_MAX_REGISTER 0x2A |
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| 59 | |
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| 60 | #endif |
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| 61 | |
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