| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * cs42l51.h |
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| 4 | * |
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| 5 | * ASoC Driver for Cirrus Logic CS42L51 codecs |
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| 6 | * |
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| 7 | * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com> |
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| 8 | */ |
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| 9 | #ifndef _CS42L51_H |
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| 10 | #define _CS42L51_H |
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| 11 | |
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| 12 | struct device; |
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| 13 | |
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| 14 | extern const struct regmap_config cs42l51_regmap; |
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| 15 | int cs42l51_probe(struct device *dev, struct regmap *regmap); |
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| 16 | void cs42l51_remove(struct device *dev); |
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| 17 | int __maybe_unused cs42l51_suspend(struct device *dev); |
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| 18 | int __maybe_unused cs42l51_resume(struct device *dev); |
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| 19 | |
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| 20 | #define CS42L51_CHIP_ID 0x1B |
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| 21 | #define CS42L51_CHIP_REV_A 0x00 |
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| 22 | #define CS42L51_CHIP_REV_B 0x01 |
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| 23 | #define CS42L51_CHIP_REV_MASK 0x07 |
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| 24 | |
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| 25 | #define CS42L51_CHIP_REV_ID 0x01 |
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| 26 | #define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b)) |
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| 27 | |
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| 28 | #define CS42L51_POWER_CTL1 0x02 |
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| 29 | #define CS42L51_POWER_CTL1_PDN_DACB (1<<6) |
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| 30 | #define CS42L51_POWER_CTL1_PDN_DACA (1<<5) |
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| 31 | #define CS42L51_POWER_CTL1_PDN_PGAB (1<<4) |
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| 32 | #define CS42L51_POWER_CTL1_PDN_PGAA (1<<3) |
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| 33 | #define CS42L51_POWER_CTL1_PDN_ADCB (1<<2) |
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| 34 | #define CS42L51_POWER_CTL1_PDN_ADCA (1<<1) |
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| 35 | #define CS42L51_POWER_CTL1_PDN (1<<0) |
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| 36 | |
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| 37 | #define CS42L51_MIC_POWER_CTL 0x03 |
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| 38 | #define CS42L51_MIC_POWER_CTL_AUTO (1<<7) |
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| 39 | #define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) |
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| 40 | #define CS42L51_QSM_MODE 3 |
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| 41 | #define CS42L51_HSM_MODE 2 |
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| 42 | #define CS42L51_SSM_MODE 1 |
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| 43 | #define CS42L51_DSM_MODE 0 |
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| 44 | #define CS42L51_MIC_POWER_CTL_3ST_SP (1<<4) |
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| 45 | #define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3) |
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| 46 | #define CS42L51_MIC_POWER_CTL_PDN_MICA (1<<2) |
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| 47 | #define CS42L51_MIC_POWER_CTL_PDN_BIAS (1<<1) |
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| 48 | #define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0) |
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| 49 | |
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| 50 | #define CS42L51_INTF_CTL 0x04 |
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| 51 | #define CS42L51_INTF_CTL_LOOPBACK (1<<7) |
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| 52 | #define CS42L51_INTF_CTL_MASTER (1<<6) |
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| 53 | #define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) |
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| 54 | #define CS42L51_DAC_DIF_LJ24 0x00 |
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| 55 | #define CS42L51_DAC_DIF_I2S 0x01 |
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| 56 | #define CS42L51_DAC_DIF_RJ24 0x02 |
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| 57 | #define CS42L51_DAC_DIF_RJ20 0x03 |
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| 58 | #define CS42L51_DAC_DIF_RJ18 0x04 |
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| 59 | #define CS42L51_DAC_DIF_RJ16 0x05 |
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| 60 | #define CS42L51_INTF_CTL_ADC_I2S (1<<2) |
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| 61 | #define CS42L51_INTF_CTL_DIGMIX (1<<1) |
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| 62 | #define CS42L51_INTF_CTL_MICMIX (1<<0) |
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| 63 | |
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| 64 | #define CS42L51_MIC_CTL 0x05 |
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| 65 | #define CS42L51_MIC_CTL_ADC_SNGVOL (1<<7) |
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| 66 | #define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6) |
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| 67 | #define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5) |
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| 68 | #define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4) |
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| 69 | #define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) |
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| 70 | #define CS42L51_MIC_CTL_MICB_BOOST (1<<1) |
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| 71 | #define CS42L51_MIC_CTL_MICA_BOOST (1<<0) |
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| 72 | |
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| 73 | #define CS42L51_ADC_CTL 0x06 |
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| 74 | #define CS42L51_ADC_CTL_ADCB_HPFEN (1<<7) |
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| 75 | #define CS42L51_ADC_CTL_ADCB_HPFRZ (1<<6) |
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| 76 | #define CS42L51_ADC_CTL_ADCA_HPFEN (1<<5) |
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| 77 | #define CS42L51_ADC_CTL_ADCA_HPFRZ (1<<4) |
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| 78 | #define CS42L51_ADC_CTL_SOFTB (1<<3) |
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| 79 | #define CS42L51_ADC_CTL_ZCROSSB (1<<2) |
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| 80 | #define CS42L51_ADC_CTL_SOFTA (1<<1) |
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| 81 | #define CS42L51_ADC_CTL_ZCROSSA (1<<0) |
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| 82 | |
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| 83 | #define CS42L51_ADC_INPUT 0x07 |
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| 84 | #define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) |
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| 85 | #define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) |
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| 86 | #define CS42L51_ADC_INPUT_INV_ADCB (1<<3) |
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| 87 | #define CS42L51_ADC_INPUT_INV_ADCA (1<<2) |
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| 88 | #define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1) |
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| 89 | #define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0) |
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| 90 | |
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| 91 | #define CS42L51_DAC_OUT_CTL 0x08 |
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| 92 | #define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) |
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| 93 | #define CS42L51_DAC_OUT_CTL_DAC_SNGVOL (1<<4) |
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| 94 | #define CS42L51_DAC_OUT_CTL_INV_PCMB (1<<3) |
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| 95 | #define CS42L51_DAC_OUT_CTL_INV_PCMA (1<<2) |
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| 96 | #define CS42L51_DAC_OUT_CTL_DACB_MUTE (1<<1) |
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| 97 | #define CS42L51_DAC_OUT_CTL_DACA_MUTE (1<<0) |
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| 98 | |
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| 99 | #define CS42L51_DAC_CTL 0x09 |
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| 100 | #define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) |
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| 101 | #define CS42L51_DAC_CTL_FREEZE (1<<5) |
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| 102 | #define CS42L51_DAC_CTL_DEEMPH (1<<3) |
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| 103 | #define CS42L51_DAC_CTL_AMUTE (1<<2) |
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| 104 | #define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) |
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| 105 | |
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| 106 | #define CS42L51_ALC_PGA_CTL 0x0A |
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| 107 | #define CS42L51_ALC_PGB_CTL 0x0B |
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| 108 | #define CS42L51_ALC_PGX_ALCX_SRDIS (1<<7) |
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| 109 | #define CS42L51_ALC_PGX_ALCX_ZCDIS (1<<6) |
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| 110 | #define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) |
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| 111 | |
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| 112 | #define CS42L51_ADCA_ATT 0x0C |
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| 113 | #define CS42L51_ADCB_ATT 0x0D |
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| 114 | |
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| 115 | #define CS42L51_ADCA_VOL 0x0E |
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| 116 | #define CS42L51_ADCB_VOL 0x0F |
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| 117 | #define CS42L51_PCMA_VOL 0x10 |
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| 118 | #define CS42L51_PCMB_VOL 0x11 |
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| 119 | #define CS42L51_MIX_MUTE_ADCMIX (1<<7) |
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| 120 | #define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) |
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| 121 | |
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| 122 | #define CS42L51_BEEP_FREQ 0x12 |
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| 123 | #define CS42L51_BEEP_VOL 0x13 |
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| 124 | #define CS42L51_BEEP_CONF 0x14 |
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| 125 | |
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| 126 | #define CS42L51_TONE_CTL 0x15 |
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| 127 | #define CS42L51_TONE_CTL_TREB(x) (((x)&0xf)<<4) |
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| 128 | #define CS42L51_TONE_CTL_BASS(x) (((x)&0xf)<<0) |
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| 129 | |
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| 130 | #define CS42L51_AOUTA_VOL 0x16 |
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| 131 | #define CS42L51_AOUTB_VOL 0x17 |
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| 132 | #define CS42L51_PCM_MIXER 0x18 |
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| 133 | #define CS42L51_LIMIT_THRES_DIS 0x19 |
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| 134 | #define CS42L51_LIMIT_REL 0x1A |
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| 135 | #define CS42L51_LIMIT_ATT 0x1B |
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| 136 | #define CS42L51_ALC_EN 0x1C |
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| 137 | #define CS42L51_ALC_REL 0x1D |
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| 138 | #define CS42L51_ALC_THRES 0x1E |
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| 139 | #define CS42L51_NOISE_CONF 0x1F |
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| 140 | |
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| 141 | #define CS42L51_STATUS 0x20 |
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| 142 | #define CS42L51_STATUS_SP_CLKERR (1<<6) |
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| 143 | #define CS42L51_STATUS_SPEA_OVFL (1<<5) |
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| 144 | #define CS42L51_STATUS_SPEB_OVFL (1<<4) |
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| 145 | #define CS42L51_STATUS_PCMA_OVFL (1<<3) |
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| 146 | #define CS42L51_STATUS_PCMB_OVFL (1<<2) |
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| 147 | #define CS42L51_STATUS_ADCA_OVFL (1<<1) |
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| 148 | #define CS42L51_STATUS_ADCB_OVFL (1<<0) |
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| 149 | |
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| 150 | #define CS42L51_CHARGE_FREQ 0x21 |
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| 151 | |
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| 152 | #define CS42L51_FIRSTREG 0x01 |
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| 153 | /* |
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| 154 | * Hack: with register 0x21, it makes 33 registers. Looks like someone in the |
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| 155 | * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using |
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| 156 | * 32 regs |
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| 157 | */ |
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| 158 | #define CS42L51_LASTREG 0x20 |
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| 159 | #define CS42L51_NUMREGS (CS42L51_LASTREG - CS42L51_FIRSTREG + 1) |
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| 160 | |
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| 161 | #endif |
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| 162 | |
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