1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * cs42l52.h -- CS42L56 ALSA SoC audio driver |
4 | * |
5 | * Copyright 2014 CirrusLogic, Inc. |
6 | * |
7 | * Author: Brian Austin <brian.austin@cirrus.com> |
8 | */ |
9 | |
10 | #ifndef __CS42L56_H__ |
11 | #define __CS42L56_H__ |
12 | |
13 | #define CS42L56_CHIP_ID_1 0x01 |
14 | #define CS42L56_CHIP_ID_2 0x02 |
15 | #define CS42L56_PWRCTL_1 0x03 |
16 | #define CS42L56_PWRCTL_2 0x04 |
17 | #define CS42L56_CLKCTL_1 0x05 |
18 | #define CS42L56_CLKCTL_2 0x06 |
19 | #define CS42L56_SERIAL_FMT 0x07 |
20 | #define CS42L56_CLASSH_CTL 0x08 |
21 | #define CS42L56_MISC_CTL 0x09 |
22 | #define CS42L56_INT_STATUS 0x0a |
23 | #define CS42L56_PLAYBACK_CTL 0x0b |
24 | #define CS42L56_DSP_MUTE_CTL 0x0c |
25 | #define CS42L56_ADCA_MIX_VOLUME 0x0d |
26 | #define CS42L56_ADCB_MIX_VOLUME 0x0e |
27 | #define CS42L56_PCMA_MIX_VOLUME 0x0f |
28 | #define CS42L56_PCMB_MIX_VOLUME 0x10 |
29 | #define CS42L56_ANAINPUT_ADV_VOLUME 0x11 |
30 | #define CS42L56_DIGINPUT_ADV_VOLUME 0x12 |
31 | #define CS42L56_MASTER_A_VOLUME 0x13 |
32 | #define CS42L56_MASTER_B_VOLUME 0x14 |
33 | #define CS42L56_BEEP_FREQ_ONTIME 0x15 |
34 | #define CS42L56_BEEP_FREQ_OFFTIME 0x16 |
35 | #define CS42L56_BEEP_TONE_CFG 0x17 |
36 | #define CS42L56_TONE_CTL 0x18 |
37 | #define CS42L56_CHAN_MIX_SWAP 0x19 |
38 | #define CS42L56_AIN_REFCFG_ADC_MUX 0x1a |
39 | #define CS42L56_HPF_CTL 0x1b |
40 | #define CS42L56_MISC_ADC_CTL 0x1c |
41 | #define CS42L56_GAIN_BIAS_CTL 0x1d |
42 | #define CS42L56_PGAA_MUX_VOLUME 0x1e |
43 | #define CS42L56_PGAB_MUX_VOLUME 0x1f |
44 | #define CS42L56_ADCA_ATTENUATOR 0x20 |
45 | #define CS42L56_ADCB_ATTENUATOR 0x21 |
46 | #define CS42L56_ALC_EN_ATTACK_RATE 0x22 |
47 | #define CS42L56_ALC_RELEASE_RATE 0x23 |
48 | #define CS42L56_ALC_THRESHOLD 0x24 |
49 | #define CS42L56_NOISE_GATE_CTL 0x25 |
50 | #define CS42L56_ALC_LIM_SFT_ZC 0x26 |
51 | #define CS42L56_AMUTE_HPLO_MUX 0x27 |
52 | #define CS42L56_HPA_VOLUME 0x28 |
53 | #define CS42L56_HPB_VOLUME 0x29 |
54 | #define CS42L56_LOA_VOLUME 0x2a |
55 | #define CS42L56_LOB_VOLUME 0x2b |
56 | #define CS42L56_LIM_THRESHOLD_CTL 0x2c |
57 | #define CS42L56_LIM_CTL_RELEASE_RATE 0x2d |
58 | #define CS42L56_LIM_ATTACK_RATE 0x2e |
59 | |
60 | /* Device ID and Rev ID Masks */ |
61 | #define CS42L56_DEVID 0x56 |
62 | #define CS42L56_CHIP_ID_MASK 0xff |
63 | #define CS42L56_AREV_MASK 0x1c |
64 | #define CS42L56_MTLREV_MASK 0x03 |
65 | |
66 | /* Power bit masks */ |
67 | #define CS42L56_PDN_ALL_MASK 0x01 |
68 | #define CS42L56_PDN_ADCA_MASK 0x02 |
69 | #define CS42L56_PDN_ADCB_MASK 0x04 |
70 | #define CS42L56_PDN_CHRG_MASK 0x08 |
71 | #define CS42L56_PDN_BIAS_MASK 0x10 |
72 | #define CS42L56_PDN_VBUF_MASK 0x20 |
73 | #define CS42L56_PDN_LOA_MASK 0x03 |
74 | #define CS42L56_PDN_LOB_MASK 0x0c |
75 | #define CS42L56_PDN_HPA_MASK 0x30 |
76 | #define CS42L56_PDN_HPB_MASK 0xc0 |
77 | |
78 | /* serial port and clk masks */ |
79 | #define CS42L56_MASTER_MODE 0x40 |
80 | #define CS42L56_SLAVE_MODE 0 |
81 | #define CS42L56_MS_MODE_MASK 0x40 |
82 | #define CS42L56_SCLK_INV 0x20 |
83 | #define CS42L56_SCLK_INV_MASK 0x20 |
84 | #define CS42L56_SCLK_MCLK_MASK 0x18 |
85 | #define CS42L56_MCLK_PREDIV 0x04 |
86 | #define CS42L56_MCLK_PREDIV_MASK 0x04 |
87 | #define CS42L56_MCLK_DIV2 0x02 |
88 | #define CS42L56_MCLK_DIV2_MASK 0x02 |
89 | #define CS42L56_MCLK_DIS_MASK 0x01 |
90 | #define CS42L56_CLK_AUTO_MASK 0x20 |
91 | #define CS42L56_CLK_RATIO_MASK 0x1f |
92 | #define CS42L56_DIG_FMT_I2S 0 |
93 | #define CS42L56_DIG_FMT_LEFT_J 0x08 |
94 | #define CS42L56_DIG_FMT_MASK 0x08 |
95 | |
96 | /* Class H and misc ctl masks */ |
97 | #define CS42L56_ADAPT_PWR_MASK 0xc0 |
98 | #define CS42L56_CHRG_FREQ_MASK 0x0f |
99 | #define CS42L56_DIG_MUX_MASK 0x80 |
100 | #define CS42L56_ANLGSFT_MASK 0x10 |
101 | #define CS42L56_ANLGZC_MASK 0x08 |
102 | #define CS42L56_DIGSFT_MASK 0x04 |
103 | #define CS42L56_FREEZE_MASK 0x01 |
104 | #define CS42L56_MIC_BIAS_MASK 0x03 |
105 | #define CS42L56_HPFA_FREQ_MASK 0x03 |
106 | #define CS42L56_HPFB_FREQ_MASK 0xc0 |
107 | #define CS42L56_AIN1A_REF_MASK 0x10 |
108 | #define CS42L56_AIN2A_REF_MASK 0x40 |
109 | #define CS42L56_AIN1B_REF_MASK 0x20 |
110 | #define CS42L56_AIN2B_REF_MASK 0x80 |
111 | |
112 | /* Playback Capture ctl masks */ |
113 | #define CS42L56_PDN_DSP_MASK 0x80 |
114 | #define CS42L56_DEEMPH_MASK 0x40 |
115 | #define CS42L56_PLYBCK_GANG_MASK 0x10 |
116 | #define CS42L56_PCM_INV_MASK 0x0c |
117 | #define CS42L56_MUTE_ALL 0xff |
118 | #define CS42L56_UNMUTE 0 |
119 | #define CS42L56_ADCAMIX_MUTE_MASK 0x40 |
120 | #define CS42L56_ADCBMIX_MUTE_MASK 0x80 |
121 | #define CS42L56_PCMAMIX_MUTE_MASK 0x10 |
122 | #define CS42L56_PCMBMIX_MUTE_MASK 0x20 |
123 | #define CS42L56_MSTB_MUTE_MASK 0x02 |
124 | #define CS42L56_MSTA_MUTE_MASK 0x01 |
125 | #define CS42L56_ADCA_MUTE_MASK 0x01 |
126 | #define CS42L56_ADCB_MUTE_MASK 0x02 |
127 | #define CS42L56_HP_MUTE_MASK 0x80 |
128 | #define CS42L56_LO_MUTE_MASK 0x80 |
129 | |
130 | /* Beep masks */ |
131 | #define CS42L56_BEEP_FREQ_MASK 0xf0 |
132 | #define CS42L56_BEEP_ONTIME_MASK 0x0f |
133 | #define CS42L56_BEEP_OFFTIME_MASK 0xe0 |
134 | #define CS42L56_BEEP_CFG_MASK 0xc0 |
135 | #define CS42L56_BEEP_TREBCF_MASK 0x18 |
136 | #define CS42L56_BEEP_BASSCF_MASK 0x06 |
137 | #define CS42L56_BEEP_TCEN_MASK 0x01 |
138 | #define CS42L56_BEEP_RATE_SHIFT 4 |
139 | #define CS42L56_BEEP_EN_MASK 0x3f |
140 | |
141 | |
142 | /* Supported MCLKS */ |
143 | #define CS42L56_MCLK_5P6448MHZ 5644800 |
144 | #define CS42L56_MCLK_6MHZ 6000000 |
145 | #define CS42L56_MCLK_6P144MHZ 6144000 |
146 | #define CS42L56_MCLK_11P2896MHZ 11289600 |
147 | #define CS42L56_MCLK_12MHZ 12000000 |
148 | #define CS42L56_MCLK_12P288MHZ 12288000 |
149 | #define CS42L56_MCLK_22P5792MHZ 22579200 |
150 | #define CS42L56_MCLK_24MHZ 24000000 |
151 | #define CS42L56_MCLK_24P576MHZ 24576000 |
152 | |
153 | /* Clock ratios */ |
154 | #define CS42L56_MCLK_LRCLK_128 0x08 |
155 | #define CS42L56_MCLK_LRCLK_125 0x09 |
156 | #define CS42L56_MCLK_LRCLK_136 0x0b |
157 | #define CS42L56_MCLK_LRCLK_192 0x0c |
158 | #define CS42L56_MCLK_LRCLK_187P5 0x0d |
159 | #define CS42L56_MCLK_LRCLK_256 0x10 |
160 | #define CS42L56_MCLK_LRCLK_250 0x11 |
161 | #define CS42L56_MCLK_LRCLK_272 0x13 |
162 | #define CS42L56_MCLK_LRCLK_384 0x14 |
163 | #define CS42L56_MCLK_LRCLK_375 0x15 |
164 | #define CS42L56_MCLK_LRCLK_512 0x18 |
165 | #define CS42L56_MCLK_LRCLK_500 0x19 |
166 | #define CS42L56_MCLK_LRCLK_544 0x1b |
167 | #define CS42L56_MCLK_LRCLK_750 0x1c |
168 | #define CS42L56_MCLK_LRCLK_768 0x1d |
169 | |
170 | |
171 | #define CS42L56_MAX_REGISTER 0x34 |
172 | |
173 | #endif |
174 | |