| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * ALSA SoC CS53L30 codec driver |
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| 4 | * |
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| 5 | * Copyright 2015 Cirrus Logic, Inc. |
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| 6 | * |
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| 7 | * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>, |
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| 8 | * Tim Howe <Tim.Howe@cirrus.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef __CS53L30_H__ |
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| 12 | #define __CS53L30_H__ |
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| 13 | |
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| 14 | /* I2C Registers */ |
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| 15 | #define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */ |
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| 16 | #define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */ |
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| 17 | #define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */ |
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| 18 | #define CS53L30_REVID 0x05 /* Revision ID [RO]. */ |
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| 19 | #define CS53L30_PWRCTL 0x06 /* Power Control. */ |
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| 20 | #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */ |
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| 21 | #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */ |
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| 22 | #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */ |
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| 23 | #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */ |
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| 24 | #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */ |
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| 25 | #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */ |
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| 26 | #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */ |
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| 27 | #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */ |
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| 28 | #define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */ |
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| 29 | #define CS53L30_ASP_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */ |
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| 30 | #define CS53L30_ASP_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */ |
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| 31 | #define CS53L30_ASP_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */ |
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| 32 | #define CS53L30_ASP_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */ |
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| 33 | #define CS53L30_ASP_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */ |
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| 34 | #define CS53L30_ASP_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */ |
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| 35 | #define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */ |
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| 36 | #define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */ |
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| 37 | #define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */ |
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| 38 | #define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */ |
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| 39 | #define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */ |
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| 40 | #define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */ |
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| 41 | #define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */ |
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| 42 | #define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */ |
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| 43 | #define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */ |
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| 44 | #define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */ |
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| 45 | #define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */ |
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| 46 | #define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */ |
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| 47 | #define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */ |
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| 48 | #define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */ |
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| 49 | #define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */ |
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| 50 | #define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */ |
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| 51 | #define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */ |
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| 52 | #define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */ |
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| 53 | #define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */ |
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| 54 | #define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */ |
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| 55 | #define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */ |
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| 56 | #define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */ |
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| 57 | #define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */ |
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| 58 | #define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */ |
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| 59 | #define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */ |
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| 60 | #define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */ |
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| 61 | #define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */ |
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| 62 | #define CS53L30_IS 0x36 /* Interrupt Status. */ |
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| 63 | #define CS53L30_MAX_REGISTER 0x36 |
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| 64 | |
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| 65 | #define CS53L30_TDM_SLOT_MAX 4 |
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| 66 | #define CS53L30_ASP_TDMTX_CTL(x) (CS53L30_ASP_TDMTX_CTL1 + (x)) |
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| 67 | /* x : index for registers; n : index for slot; 8 slots per register */ |
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| 68 | #define CS53L30_ASP_TDMTX_ENx(x) (CS53L30_ASP_TDMTX_EN6 - (x)) |
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| 69 | #define CS53L30_ASP_TDMTX_ENn(n) CS53L30_ASP_TDMTX_ENx((n) >> 3) |
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| 70 | #define CS53L30_ASP_TDMTX_ENx_MAX 6 |
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| 71 | |
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| 72 | /* Device ID */ |
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| 73 | #define CS53L30_DEVID 0x53A30 |
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| 74 | |
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| 75 | /* PDN_DONE Poll Maximum |
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| 76 | * If soft ramp is set it will take much longer to power down |
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| 77 | * the system. |
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| 78 | */ |
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| 79 | #define CS53L30_PDN_POLL_MAX 90 |
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| 80 | |
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| 81 | /* Bitfield Definitions */ |
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| 82 | |
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| 83 | /* R6 (0x06) CS53L30_PWRCTL - Power Control */ |
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| 84 | #define CS53L30_PDN_ULP_SHIFT 7 |
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| 85 | #define CS53L30_PDN_ULP_MASK (1 << CS53L30_PDN_ULP_SHIFT) |
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| 86 | #define CS53L30_PDN_ULP (1 << CS53L30_PDN_ULP_SHIFT) |
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| 87 | #define CS53L30_PDN_LP_SHIFT 6 |
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| 88 | #define CS53L30_PDN_LP_MASK (1 << CS53L30_PDN_LP_SHIFT) |
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| 89 | #define CS53L30_PDN_LP (1 << CS53L30_PDN_LP_SHIFT) |
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| 90 | #define CS53L30_DISCHARGE_FILT_SHIFT 5 |
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| 91 | #define CS53L30_DISCHARGE_FILT_MASK (1 << CS53L30_DISCHARGE_FILT_SHIFT) |
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| 92 | #define CS53L30_DISCHARGE_FILT (1 << CS53L30_DISCHARGE_FILT_SHIFT) |
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| 93 | #define CS53L30_THMS_PDN_SHIFT 4 |
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| 94 | #define CS53L30_THMS_PDN_MASK (1 << CS53L30_THMS_PDN_SHIFT) |
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| 95 | #define CS53L30_THMS_PDN (1 << CS53L30_THMS_PDN_SHIFT) |
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| 96 | |
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| 97 | #define CS53L30_PWRCTL_DEFAULT (CS53L30_THMS_PDN) |
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| 98 | |
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| 99 | /* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */ |
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| 100 | #define CS53L30_MCLK_DIS_SHIFT 7 |
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| 101 | #define CS53L30_MCLK_DIS_MASK (1 << CS53L30_MCLK_DIS_SHIFT) |
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| 102 | #define CS53L30_MCLK_DIS (1 << CS53L30_MCLK_DIS_SHIFT) |
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| 103 | #define CS53L30_MCLK_INT_SCALE_SHIFT 6 |
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| 104 | #define CS53L30_MCLK_INT_SCALE_MASK (1 << CS53L30_MCLK_INT_SCALE_SHIFT) |
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| 105 | #define CS53L30_MCLK_INT_SCALE (1 << CS53L30_MCLK_INT_SCALE_SHIFT) |
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| 106 | #define CS53L30_DMIC_DRIVE_SHIFT 5 |
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| 107 | #define CS53L30_DMIC_DRIVE_MASK (1 << CS53L30_DMIC_DRIVE_SHIFT) |
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| 108 | #define CS53L30_DMIC_DRIVE (1 << CS53L30_DMIC_DRIVE_SHIFT) |
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| 109 | #define CS53L30_MCLK_DIV_SHIFT 2 |
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| 110 | #define CS53L30_MCLK_DIV_WIDTH 2 |
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| 111 | #define CS53L30_MCLK_DIV_MASK (((1 << CS53L30_MCLK_DIV_WIDTH) - 1) << CS53L30_MCLK_DIV_SHIFT) |
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| 112 | #define CS53L30_MCLK_DIV_BY_1 (0x0 << CS53L30_MCLK_DIV_SHIFT) |
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| 113 | #define CS53L30_MCLK_DIV_BY_2 (0x1 << CS53L30_MCLK_DIV_SHIFT) |
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| 114 | #define CS53L30_MCLK_DIV_BY_3 (0x2 << CS53L30_MCLK_DIV_SHIFT) |
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| 115 | #define CS53L30_SYNC_EN_SHIFT 1 |
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| 116 | #define CS53L30_SYNC_EN_MASK (1 << CS53L30_SYNC_EN_SHIFT) |
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| 117 | #define CS53L30_SYNC_EN (1 << CS53L30_SYNC_EN_SHIFT) |
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| 118 | |
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| 119 | #define CS53L30_MCLKCTL_DEFAULT (CS53L30_MCLK_DIV_BY_2) |
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| 120 | |
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| 121 | /* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */ |
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| 122 | #define CS53L30_INTRNL_FS_RATIO_SHIFT 4 |
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| 123 | #define CS53L30_INTRNL_FS_RATIO_MASK (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) |
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| 124 | #define CS53L30_INTRNL_FS_RATIO (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) |
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| 125 | #define CS53L30_MCLK_19MHZ_EN_SHIFT 0 |
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| 126 | #define CS53L30_MCLK_19MHZ_EN_MASK (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) |
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| 127 | #define CS53L30_MCLK_19MHZ_EN (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) |
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| 128 | |
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| 129 | /* 0x6 << 1 is reserved bits */ |
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| 130 | #define CS53L30_INT_SR_CTL_DEFAULT (CS53L30_INTRNL_FS_RATIO | 0x6 << 1) |
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| 131 | |
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| 132 | /* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */ |
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| 133 | #define CS53L30_MIC4_BIAS_PDN_SHIFT 7 |
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| 134 | #define CS53L30_MIC4_BIAS_PDN_MASK (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) |
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| 135 | #define CS53L30_MIC4_BIAS_PDN (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) |
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| 136 | #define CS53L30_MIC3_BIAS_PDN_SHIFT 6 |
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| 137 | #define CS53L30_MIC3_BIAS_PDN_MASK (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) |
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| 138 | #define CS53L30_MIC3_BIAS_PDN (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) |
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| 139 | #define CS53L30_MIC2_BIAS_PDN_SHIFT 5 |
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| 140 | #define CS53L30_MIC2_BIAS_PDN_MASK (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) |
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| 141 | #define CS53L30_MIC2_BIAS_PDN (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) |
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| 142 | #define CS53L30_MIC1_BIAS_PDN_SHIFT 4 |
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| 143 | #define CS53L30_MIC1_BIAS_PDN_MASK (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) |
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| 144 | #define CS53L30_MIC1_BIAS_PDN (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) |
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| 145 | #define CS53L30_MICx_BIAS_PDN (0xf << CS53L30_MIC1_BIAS_PDN_SHIFT) |
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| 146 | #define CS53L30_VP_MIN_SHIFT 2 |
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| 147 | #define CS53L30_VP_MIN_MASK (1 << CS53L30_VP_MIN_SHIFT) |
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| 148 | #define CS53L30_VP_MIN (1 << CS53L30_VP_MIN_SHIFT) |
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| 149 | #define CS53L30_MIC_BIAS_CTRL_SHIFT 0 |
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| 150 | #define CS53L30_MIC_BIAS_CTRL_WIDTH 2 |
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| 151 | #define CS53L30_MIC_BIAS_CTRL_MASK (((1 << CS53L30_MIC_BIAS_CTRL_WIDTH) - 1) << CS53L30_MIC_BIAS_CTRL_SHIFT) |
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| 152 | #define CS53L30_MIC_BIAS_CTRL_HIZ (0 << CS53L30_MIC_BIAS_CTRL_SHIFT) |
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| 153 | #define CS53L30_MIC_BIAS_CTRL_1V8 (1 << CS53L30_MIC_BIAS_CTRL_SHIFT) |
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| 154 | #define CS53L30_MIC_BIAS_CTRL_2V75 (2 << CS53L30_MIC_BIAS_CTRL_SHIFT) |
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| 155 | |
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| 156 | #define CS53L30_MICBIAS_CTL_DEFAULT (CS53L30_MICx_BIAS_PDN | CS53L30_VP_MIN) |
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| 157 | |
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| 158 | /* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */ |
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| 159 | #define CS53L30_ASP_MS_SHIFT 7 |
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| 160 | #define CS53L30_ASP_MS_MASK (1 << CS53L30_ASP_MS_SHIFT) |
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| 161 | #define CS53L30_ASP_MS (1 << CS53L30_ASP_MS_SHIFT) |
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| 162 | #define CS53L30_ASP_SCLK_INV_SHIFT 4 |
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| 163 | #define CS53L30_ASP_SCLK_INV_MASK (1 << CS53L30_ASP_SCLK_INV_SHIFT) |
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| 164 | #define CS53L30_ASP_SCLK_INV (1 << CS53L30_ASP_SCLK_INV_SHIFT) |
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| 165 | #define CS53L30_ASP_RATE_SHIFT 0 |
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| 166 | #define CS53L30_ASP_RATE_WIDTH 4 |
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| 167 | #define CS53L30_ASP_RATE_MASK (((1 << CS53L30_ASP_RATE_WIDTH) - 1) << CS53L30_ASP_RATE_SHIFT) |
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| 168 | #define CS53L30_ASP_RATE_48K (0xc << CS53L30_ASP_RATE_SHIFT) |
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| 169 | |
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| 170 | #define CS53L30_ASPCFG_CTL_DEFAULT (CS53L30_ASP_RATE_48K) |
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| 171 | |
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| 172 | /* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */ |
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| 173 | #define CS53L30_ASP_TDM_PDN_SHIFT 7 |
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| 174 | #define CS53L30_ASP_TDM_PDN_MASK (1 << CS53L30_ASP_TDM_PDN_SHIFT) |
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| 175 | #define CS53L30_ASP_TDM_PDN (1 << CS53L30_ASP_TDM_PDN_SHIFT) |
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| 176 | #define CS53L30_ASP_SDOUTx_PDN_SHIFT 6 |
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| 177 | #define CS53L30_ASP_SDOUTx_PDN_MASK (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) |
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| 178 | #define CS53L30_ASP_SDOUTx_PDN (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) |
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| 179 | #define CS53L30_ASP_3ST_SHIFT 5 |
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| 180 | #define CS53L30_ASP_3ST_MASK (1 << CS53L30_ASP_3ST_SHIFT) |
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| 181 | #define CS53L30_ASP_3ST (1 << CS53L30_ASP_3ST_SHIFT) |
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| 182 | #define CS53L30_SHIFT_LEFT_SHIFT 4 |
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| 183 | #define CS53L30_SHIFT_LEFT_MASK (1 << CS53L30_SHIFT_LEFT_SHIFT) |
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| 184 | #define CS53L30_SHIFT_LEFT (1 << CS53L30_SHIFT_LEFT_SHIFT) |
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| 185 | #define CS53L30_ASP_SDOUTx_DRIVE_SHIFT 0 |
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| 186 | #define CS53L30_ASP_SDOUTx_DRIVE_MASK (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) |
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| 187 | #define CS53L30_ASP_SDOUTx_DRIVE (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) |
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| 188 | |
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| 189 | #define CS53L30_ASP_CTL1_DEFAULT (CS53L30_ASP_TDM_PDN) |
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| 190 | #define CS53L30_ASP_CTL2_DEFAULT (0) |
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| 191 | |
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| 192 | /* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */ |
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| 193 | #define CS53L30_ASP_CHx_TX_STATE_SHIFT 7 |
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| 194 | #define CS53L30_ASP_CHx_TX_STATE_MASK (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) |
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| 195 | #define CS53L30_ASP_CHx_TX_STATE (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) |
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| 196 | #define CS53L30_ASP_CHx_TX_LOC_SHIFT 0 |
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| 197 | #define CS53L30_ASP_CHx_TX_LOC_WIDTH 6 |
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| 198 | #define CS53L30_ASP_CHx_TX_LOC_MASK (((1 << CS53L30_ASP_CHx_TX_LOC_WIDTH) - 1) << CS53L30_ASP_CHx_TX_LOC_SHIFT) |
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| 199 | #define CS53L30_ASP_CHx_TX_LOC_MAX (47 << CS53L30_ASP_CHx_TX_LOC_SHIFT) |
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| 200 | #define CS53L30_ASP_CHx_TX_LOC(x) ((x) << CS53L30_ASP_CHx_TX_LOC_SHIFT) |
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| 201 | |
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| 202 | #define CS53L30_ASP_TDMTX_CTLx_DEFAULT (CS53L30_ASP_CHx_TX_LOC_MAX) |
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| 203 | |
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| 204 | /* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */ |
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| 205 | #define CS53L30_ASP_TDMTX_ENx_DEFAULT (0) |
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| 206 | |
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| 207 | /* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */ |
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| 208 | #define CS53L30_DIGSFT_SHIFT 5 |
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| 209 | #define CS53L30_DIGSFT_MASK (1 << CS53L30_DIGSFT_SHIFT) |
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| 210 | #define CS53L30_DIGSFT (1 << CS53L30_DIGSFT_SHIFT) |
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| 211 | |
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| 212 | #define CS53L30_SFT_RMP_DEFAULT (0) |
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| 213 | |
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| 214 | /* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */ |
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| 215 | #define CS53L30_LRCK_50_NPW_SHIFT 3 |
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| 216 | #define CS53L30_LRCK_50_NPW_MASK (1 << CS53L30_LRCK_50_NPW_SHIFT) |
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| 217 | #define CS53L30_LRCK_50_NPW (1 << CS53L30_LRCK_50_NPW_SHIFT) |
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| 218 | #define CS53L30_LRCK_TPWH_SHIFT 0 |
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| 219 | #define CS53L30_LRCK_TPWH_WIDTH 3 |
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| 220 | #define CS53L30_LRCK_TPWH_MASK (((1 << CS53L30_LRCK_TPWH_WIDTH) - 1) << CS53L30_LRCK_TPWH_SHIFT) |
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| 221 | #define CS53L30_LRCK_TPWH(x) (((x) << CS53L30_LRCK_TPWH_SHIFT) & CS53L30_LRCK_TPWH_MASK) |
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| 222 | |
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| 223 | #define CS53L30_LRCK_CTLx_DEFAULT (0) |
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| 224 | |
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| 225 | /* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */ |
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| 226 | #define CS53L30_MUTE_PDN_ULP_SHIFT 7 |
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| 227 | #define CS53L30_MUTE_PDN_ULP_MASK (1 << CS53L30_MUTE_PDN_ULP_SHIFT) |
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| 228 | #define CS53L30_MUTE_PDN_ULP (1 << CS53L30_MUTE_PDN_ULP_SHIFT) |
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| 229 | #define CS53L30_MUTE_PDN_LP_SHIFT 6 |
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| 230 | #define CS53L30_MUTE_PDN_LP_MASK (1 << CS53L30_MUTE_PDN_LP_SHIFT) |
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| 231 | #define CS53L30_MUTE_PDN_LP (1 << CS53L30_MUTE_PDN_LP_SHIFT) |
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| 232 | #define CS53L30_MUTE_M4B_PDN_SHIFT 4 |
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| 233 | #define CS53L30_MUTE_M4B_PDN_MASK (1 << CS53L30_MUTE_M4B_PDN_SHIFT) |
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| 234 | #define CS53L30_MUTE_M4B_PDN (1 << CS53L30_MUTE_M4B_PDN_SHIFT) |
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| 235 | #define CS53L30_MUTE_M3B_PDN_SHIFT 3 |
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| 236 | #define CS53L30_MUTE_M3B_PDN_MASK (1 << CS53L30_MUTE_M3B_PDN_SHIFT) |
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| 237 | #define CS53L30_MUTE_M3B_PDN (1 << CS53L30_MUTE_M3B_PDN_SHIFT) |
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| 238 | #define CS53L30_MUTE_M2B_PDN_SHIFT 2 |
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| 239 | #define CS53L30_MUTE_M2B_PDN_MASK (1 << CS53L30_MUTE_M2B_PDN_SHIFT) |
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| 240 | #define CS53L30_MUTE_M2B_PDN (1 << CS53L30_MUTE_M2B_PDN_SHIFT) |
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| 241 | #define CS53L30_MUTE_M1B_PDN_SHIFT 1 |
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| 242 | #define CS53L30_MUTE_M1B_PDN_MASK (1 << CS53L30_MUTE_M1B_PDN_SHIFT) |
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| 243 | #define CS53L30_MUTE_M1B_PDN (1 << CS53L30_MUTE_M1B_PDN_SHIFT) |
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| 244 | /* Note: be careful - x starts from 0 */ |
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| 245 | #define CS53L30_MUTE_MxB_PDN_SHIFT(x) (CS53L30_MUTE_M1B_PDN_SHIFT + (x)) |
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| 246 | #define CS53L30_MUTE_MxB_PDN_MASK(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) |
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| 247 | #define CS53L30_MUTE_MxB_PDN(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) |
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| 248 | #define CS53L30_MUTE_MB_ALL_PDN_SHIFT 0 |
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| 249 | #define CS53L30_MUTE_MB_ALL_PDN_MASK (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) |
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| 250 | #define CS53L30_MUTE_MB_ALL_PDN (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) |
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| 251 | |
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| 252 | #define CS53L30_MUTEP_CTL1_MUTEALL (0xdf) |
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| 253 | #define CS53L30_MUTEP_CTL1_DEFAULT (0) |
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| 254 | |
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| 255 | /* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */ |
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| 256 | #define CS53L30_MUTE_PIN_POLARITY_SHIFT 7 |
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| 257 | #define CS53L30_MUTE_PIN_POLARITY_MASK (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) |
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| 258 | #define CS53L30_MUTE_PIN_POLARITY (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) |
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| 259 | #define CS53L30_MUTE_ASP_TDM_PDN_SHIFT 6 |
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| 260 | #define CS53L30_MUTE_ASP_TDM_PDN_MASK (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) |
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| 261 | #define CS53L30_MUTE_ASP_TDM_PDN (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) |
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| 262 | #define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT 5 |
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| 263 | #define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) |
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| 264 | #define CS53L30_MUTE_ASP_SDOUT2_PDN (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) |
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| 265 | #define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT 4 |
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| 266 | #define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) |
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| 267 | #define CS53L30_MUTE_ASP_SDOUT1_PDN (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) |
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| 268 | /* Note: be careful - x starts from 0 */ |
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| 269 | #define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x) ((x) + CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) |
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| 270 | #define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x) (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) |
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| 271 | #define CS53L30_MUTE_ASP_SDOUTx_PDN (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) |
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| 272 | #define CS53L30_MUTE_ADC2B_PDN_SHIFT 3 |
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| 273 | #define CS53L30_MUTE_ADC2B_PDN_MASK (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) |
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| 274 | #define CS53L30_MUTE_ADC2B_PDN (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) |
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| 275 | #define CS53L30_MUTE_ADC2A_PDN_SHIFT 2 |
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| 276 | #define CS53L30_MUTE_ADC2A_PDN_MASK (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) |
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| 277 | #define CS53L30_MUTE_ADC2A_PDN (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) |
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| 278 | #define CS53L30_MUTE_ADC1B_PDN_SHIFT 1 |
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| 279 | #define CS53L30_MUTE_ADC1B_PDN_MASK (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) |
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| 280 | #define CS53L30_MUTE_ADC1B_PDN (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) |
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| 281 | #define CS53L30_MUTE_ADC1A_PDN_SHIFT 0 |
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| 282 | #define CS53L30_MUTE_ADC1A_PDN_MASK (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) |
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| 283 | #define CS53L30_MUTE_ADC1A_PDN (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) |
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| 284 | |
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| 285 | #define CS53L30_MUTEP_CTL2_DEFAULT (CS53L30_MUTE_PIN_POLARITY) |
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| 286 | |
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| 287 | /* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */ |
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| 288 | #define CS53L30_IN4M_BIAS_SHIFT 6 |
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| 289 | #define CS53L30_IN4M_BIAS_WIDTH 2 |
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| 290 | #define CS53L30_IN4M_BIAS_MASK (((1 << CS53L30_IN4M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) |
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| 291 | #define CS53L30_IN4M_BIAS_OPEN (0 << CS53L30_IN4M_BIAS_SHIFT) |
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| 292 | #define CS53L30_IN4M_BIAS_PULL_DOWN (1 << CS53L30_IN4M_BIAS_SHIFT) |
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| 293 | #define CS53L30_IN4M_BIAS_VCM (2 << CS53L30_IN4M_BIAS_SHIFT) |
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| 294 | #define CS53L30_IN4P_BIAS_SHIFT 4 |
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| 295 | #define CS53L30_IN4P_BIAS_WIDTH 2 |
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| 296 | #define CS53L30_IN4P_BIAS_MASK (((1 << CS53L30_IN4P_BIAS_WIDTH) - 1) << CS53L30_IN4P_BIAS_SHIFT) |
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| 297 | #define CS53L30_IN4P_BIAS_OPEN (0 << CS53L30_IN4P_BIAS_SHIFT) |
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| 298 | #define CS53L30_IN4P_BIAS_PULL_DOWN (1 << CS53L30_IN4P_BIAS_SHIFT) |
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| 299 | #define CS53L30_IN4P_BIAS_VCM (2 << CS53L30_IN4P_BIAS_SHIFT) |
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| 300 | #define CS53L30_IN3M_BIAS_SHIFT 2 |
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| 301 | #define CS53L30_IN3M_BIAS_WIDTH 2 |
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| 302 | #define CS53L30_IN3M_BIAS_MASK (((1 << CS53L30_IN3M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) |
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| 303 | #define CS53L30_IN3M_BIAS_OPEN (0 << CS53L30_IN3M_BIAS_SHIFT) |
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| 304 | #define CS53L30_IN3M_BIAS_PULL_DOWN (1 << CS53L30_IN3M_BIAS_SHIFT) |
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| 305 | #define CS53L30_IN3M_BIAS_VCM (2 << CS53L30_IN3M_BIAS_SHIFT) |
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| 306 | #define CS53L30_IN3P_BIAS_SHIFT 0 |
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| 307 | #define CS53L30_IN3P_BIAS_WIDTH 2 |
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| 308 | #define CS53L30_IN3P_BIAS_MASK (((1 << CS53L30_IN3P_BIAS_WIDTH) - 1) << CS53L30_IN3P_BIAS_SHIFT) |
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| 309 | #define CS53L30_IN3P_BIAS_OPEN (0 << CS53L30_IN3P_BIAS_SHIFT) |
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| 310 | #define CS53L30_IN3P_BIAS_PULL_DOWN (1 << CS53L30_IN3P_BIAS_SHIFT) |
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| 311 | #define CS53L30_IN3P_BIAS_VCM (2 << CS53L30_IN3P_BIAS_SHIFT) |
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| 312 | |
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| 313 | #define CS53L30_INBIAS_CTL1_DEFAULT (CS53L30_IN4M_BIAS_VCM | CS53L30_IN4P_BIAS_VCM |\ |
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| 314 | CS53L30_IN3M_BIAS_VCM | CS53L30_IN3P_BIAS_VCM) |
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| 315 | |
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| 316 | /* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */ |
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| 317 | #define CS53L30_IN2M_BIAS_SHIFT 6 |
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| 318 | #define CS53L30_IN2M_BIAS_WIDTH 2 |
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| 319 | #define CS53L30_IN2M_BIAS_MASK (((1 << CS53L30_IN2M_BIAS_WIDTH) - 1) << CS53L30_IN2M_BIAS_SHIFT) |
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| 320 | #define CS53L30_IN2M_BIAS_OPEN (0 << CS53L30_IN2M_BIAS_SHIFT) |
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| 321 | #define CS53L30_IN2M_BIAS_PULL_DOWN (1 << CS53L30_IN2M_BIAS_SHIFT) |
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| 322 | #define CS53L30_IN2M_BIAS_VCM (2 << CS53L30_IN2M_BIAS_SHIFT) |
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| 323 | #define CS53L30_IN2P_BIAS_SHIFT 4 |
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| 324 | #define CS53L30_IN2P_BIAS_WIDTH 2 |
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| 325 | #define CS53L30_IN2P_BIAS_MASK (((1 << CS53L30_IN2P_BIAS_WIDTH) - 1) << CS53L30_IN2P_BIAS_SHIFT) |
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| 326 | #define CS53L30_IN2P_BIAS_OPEN (0 << CS53L30_IN2P_BIAS_SHIFT) |
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| 327 | #define CS53L30_IN2P_BIAS_PULL_DOWN (1 << CS53L30_IN2P_BIAS_SHIFT) |
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| 328 | #define CS53L30_IN2P_BIAS_VCM (2 << CS53L30_IN2P_BIAS_SHIFT) |
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| 329 | #define CS53L30_IN1M_BIAS_SHIFT 2 |
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| 330 | #define CS53L30_IN1M_BIAS_WIDTH 2 |
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| 331 | #define CS53L30_IN1M_BIAS_MASK (((1 << CS53L30_IN1M_BIAS_WIDTH) - 1) << CS53L30_IN1M_BIAS_SHIFT) |
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| 332 | #define CS53L30_IN1M_BIAS_OPEN (0 << CS53L30_IN1M_BIAS_SHIFT) |
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| 333 | #define CS53L30_IN1M_BIAS_PULL_DOWN (1 << CS53L30_IN1M_BIAS_SHIFT) |
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| 334 | #define CS53L30_IN1M_BIAS_VCM (2 << CS53L30_IN1M_BIAS_SHIFT) |
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| 335 | #define CS53L30_IN1P_BIAS_SHIFT 0 |
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| 336 | #define CS53L30_IN1P_BIAS_WIDTH 2 |
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| 337 | #define CS53L30_IN1P_BIAS_MASK (((1 << CS53L30_IN1P_BIAS_WIDTH) - 1) << CS53L30_IN1P_BIAS_SHIFT) |
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| 338 | #define CS53L30_IN1P_BIAS_OPEN (0 << CS53L30_IN1P_BIAS_SHIFT) |
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| 339 | #define CS53L30_IN1P_BIAS_PULL_DOWN (1 << CS53L30_IN1P_BIAS_SHIFT) |
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| 340 | #define CS53L30_IN1P_BIAS_VCM (2 << CS53L30_IN1P_BIAS_SHIFT) |
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| 341 | |
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| 342 | #define CS53L30_INBIAS_CTL2_DEFAULT (CS53L30_IN2M_BIAS_VCM | CS53L30_IN2P_BIAS_VCM |\ |
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| 343 | CS53L30_IN1M_BIAS_VCM | CS53L30_IN1P_BIAS_VCM) |
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| 344 | |
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| 345 | /* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */ |
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| 346 | #define CS53L30_DMICx_STEREO_ENB_SHIFT 5 |
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| 347 | #define CS53L30_DMICx_STEREO_ENB_MASK (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) |
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| 348 | #define CS53L30_DMICx_STEREO_ENB (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) |
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| 349 | |
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| 350 | /* 0x88 and 0xCC are reserved bits */ |
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| 351 | #define CS53L30_DMIC1_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0x88) |
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| 352 | #define CS53L30_DMIC2_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0xCC) |
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| 353 | |
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| 354 | /* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */ |
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| 355 | #define CS53L30_ADCxB_PDN_SHIFT 7 |
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| 356 | #define CS53L30_ADCxB_PDN_MASK (1 << CS53L30_ADCxB_PDN_SHIFT) |
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| 357 | #define CS53L30_ADCxB_PDN (1 << CS53L30_ADCxB_PDN_SHIFT) |
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| 358 | #define CS53L30_ADCxA_PDN_SHIFT 6 |
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| 359 | #define CS53L30_ADCxA_PDN_MASK (1 << CS53L30_ADCxA_PDN_SHIFT) |
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| 360 | #define CS53L30_ADCxA_PDN (1 << CS53L30_ADCxA_PDN_SHIFT) |
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| 361 | #define CS53L30_DMICx_PDN_SHIFT 2 |
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| 362 | #define CS53L30_DMICx_PDN_MASK (1 << CS53L30_DMICx_PDN_SHIFT) |
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| 363 | #define CS53L30_DMICx_PDN (1 << CS53L30_DMICx_PDN_SHIFT) |
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| 364 | #define CS53L30_DMICx_SCLK_DIV_SHIFT 1 |
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| 365 | #define CS53L30_DMICx_SCLK_DIV_MASK (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) |
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| 366 | #define CS53L30_DMICx_SCLK_DIV (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) |
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| 367 | #define CS53L30_CH_TYPE_SHIFT 0 |
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| 368 | #define CS53L30_CH_TYPE_MASK (1 << CS53L30_CH_TYPE_SHIFT) |
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| 369 | #define CS53L30_CH_TYPE (1 << CS53L30_CH_TYPE_SHIFT) |
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| 370 | |
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| 371 | #define CS53L30_ADCDMICx_PDN_MASK 0xFF |
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| 372 | #define CS53L30_ADCDMICx_CTL1_DEFAULT (CS53L30_DMICx_PDN) |
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| 373 | |
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| 374 | /* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */ |
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| 375 | #define CS53L30_ADCx_NOTCH_DIS_SHIFT 7 |
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| 376 | #define CS53L30_ADCx_NOTCH_DIS_MASK (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) |
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| 377 | #define CS53L30_ADCx_NOTCH_DIS (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) |
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| 378 | #define CS53L30_ADCxB_INV_SHIFT 5 |
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| 379 | #define CS53L30_ADCxB_INV_MASK (1 << CS53L30_ADCxB_INV_SHIFT) |
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| 380 | #define CS53L30_ADCxB_INV (1 << CS53L30_ADCxB_INV_SHIFT) |
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| 381 | #define CS53L30_ADCxA_INV_SHIFT 4 |
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| 382 | #define CS53L30_ADCxA_INV_MASK (1 << CS53L30_ADCxA_INV_SHIFT) |
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| 383 | #define CS53L30_ADCxA_INV (1 << CS53L30_ADCxA_INV_SHIFT) |
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| 384 | #define CS53L30_ADCxB_DIG_BOOST_SHIFT 1 |
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| 385 | #define CS53L30_ADCxB_DIG_BOOST_MASK (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) |
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| 386 | #define CS53L30_ADCxB_DIG_BOOST (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) |
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| 387 | #define CS53L30_ADCxA_DIG_BOOST_SHIFT 0 |
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| 388 | #define CS53L30_ADCxA_DIG_BOOST_MASK (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) |
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| 389 | #define CS53L30_ADCxA_DIG_BOOST (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) |
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| 390 | |
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| 391 | #define CS53L30_ADCDMIC1_CTL2_DEFAULT (0) |
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| 392 | |
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| 393 | /* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */ |
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| 394 | #define CS53L30_ADCx_HPF_EN_SHIFT 3 |
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| 395 | #define CS53L30_ADCx_HPF_EN_MASK (1 << CS53L30_ADCx_HPF_EN_SHIFT) |
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| 396 | #define CS53L30_ADCx_HPF_EN (1 << CS53L30_ADCx_HPF_EN_SHIFT) |
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| 397 | #define CS53L30_ADCx_HPF_CF_SHIFT 1 |
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| 398 | #define CS53L30_ADCx_HPF_CF_WIDTH 2 |
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| 399 | #define CS53L30_ADCx_HPF_CF_MASK (((1 << CS53L30_ADCx_HPF_CF_WIDTH) - 1) << CS53L30_ADCx_HPF_CF_SHIFT) |
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| 400 | #define CS53L30_ADCx_HPF_CF_1HZ86 (0 << CS53L30_ADCx_HPF_CF_SHIFT) |
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| 401 | #define CS53L30_ADCx_HPF_CF_120HZ (1 << CS53L30_ADCx_HPF_CF_SHIFT) |
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| 402 | #define CS53L30_ADCx_HPF_CF_235HZ (2 << CS53L30_ADCx_HPF_CF_SHIFT) |
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| 403 | #define CS53L30_ADCx_HPF_CF_466HZ (3 << CS53L30_ADCx_HPF_CF_SHIFT) |
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| 404 | #define CS53L30_ADCx_NG_ALL_SHIFT 0 |
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| 405 | #define CS53L30_ADCx_NG_ALL_MASK (1 << CS53L30_ADCx_NG_ALL_SHIFT) |
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| 406 | #define CS53L30_ADCx_NG_ALL (1 << CS53L30_ADCx_NG_ALL_SHIFT) |
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| 407 | |
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| 408 | #define CS53L30_ADCx_CTL3_DEFAULT (CS53L30_ADCx_HPF_EN) |
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| 409 | |
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| 410 | /* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */ |
|---|
| 411 | #define CS53L30_ADCxB_NG_SHIFT 7 |
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| 412 | #define CS53L30_ADCxB_NG_MASK (1 << CS53L30_ADCxB_NG_SHIFT) |
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| 413 | #define CS53L30_ADCxB_NG (1 << CS53L30_ADCxB_NG_SHIFT) |
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| 414 | #define CS53L30_ADCxA_NG_SHIFT 6 |
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| 415 | #define CS53L30_ADCxA_NG_MASK (1 << CS53L30_ADCxA_NG_SHIFT) |
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| 416 | #define CS53L30_ADCxA_NG (1 << CS53L30_ADCxA_NG_SHIFT) |
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| 417 | #define CS53L30_ADCx_NG_BOOST_SHIFT 5 |
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| 418 | #define CS53L30_ADCx_NG_BOOST_MASK (1 << CS53L30_ADCx_NG_BOOST_SHIFT) |
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| 419 | #define CS53L30_ADCx_NG_BOOST (1 << CS53L30_ADCx_NG_BOOST_SHIFT) |
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| 420 | #define CS53L30_ADCx_NG_THRESH_SHIFT 2 |
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| 421 | #define CS53L30_ADCx_NG_THRESH_WIDTH 3 |
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| 422 | #define CS53L30_ADCx_NG_THRESH_MASK (((1 << CS53L30_ADCx_NG_THRESH_WIDTH) - 1) << CS53L30_ADCx_NG_THRESH_SHIFT) |
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| 423 | #define CS53L30_ADCx_NG_DELAY_SHIFT 0 |
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| 424 | #define CS53L30_ADCx_NG_DELAY_WIDTH 2 |
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| 425 | #define CS53L30_ADCx_NG_DELAY_MASK (((1 << CS53L30_ADCx_NG_DELAY_WIDTH) - 1) << CS53L30_ADCx_NG_DELAY_SHIFT) |
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| 426 | |
|---|
| 427 | #define CS53L30_ADCx_NG_CTL_DEFAULT (0) |
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| 428 | |
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| 429 | /* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */ |
|---|
| 430 | #define CS53L30_ADCxy_PREAMP_SHIFT 6 |
|---|
| 431 | #define CS53L30_ADCxy_PREAMP_WIDTH 2 |
|---|
| 432 | #define CS53L30_ADCxy_PREAMP_MASK (((1 << CS53L30_ADCxy_PREAMP_WIDTH) - 1) << CS53L30_ADCxy_PREAMP_SHIFT) |
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| 433 | #define CS53L30_ADCxy_PGA_VOL_SHIFT 0 |
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| 434 | #define CS53L30_ADCxy_PGA_VOL_WIDTH 6 |
|---|
| 435 | #define CS53L30_ADCxy_PGA_VOL_MASK (((1 << CS53L30_ADCxy_PGA_VOL_WIDTH) - 1) << CS53L30_ADCxy_PGA_VOL_SHIFT) |
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| 436 | |
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| 437 | #define CS53L30_ADCxy_AFE_CTL_DEFAULT (0) |
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| 438 | |
|---|
| 439 | /* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */ |
|---|
| 440 | #define CS53L30_ADCxy_VOL_MUTE (0x80) |
|---|
| 441 | |
|---|
| 442 | #define CS53L30_ADCxy_DIG_VOL_DEFAULT (0x0) |
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| 443 | |
|---|
| 444 | /* CS53L30_INT */ |
|---|
| 445 | #define CS53L30_PDN_DONE (1 << 7) |
|---|
| 446 | #define CS53L30_THMS_TRIP (1 << 6) |
|---|
| 447 | #define CS53L30_SYNC_DONE (1 << 5) |
|---|
| 448 | #define CS53L30_ADC2B_OVFL (1 << 4) |
|---|
| 449 | #define CS53L30_ADC2A_OVFL (1 << 3) |
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| 450 | #define CS53L30_ADC1B_OVFL (1 << 2) |
|---|
| 451 | #define CS53L30_ADC1A_OVFL (1 << 1) |
|---|
| 452 | #define CS53L30_MUTE_PIN (1 << 0) |
|---|
| 453 | #define CS53L30_DEVICE_INT_MASK 0xFF |
|---|
| 454 | |
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| 455 | #endif /* __CS53L30_H__ */ |
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| 456 | |
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