| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * es8326.h -- es8326 ALSA SoC audio driver |
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| 4 | * Copyright Everest Semiconductor Co.,Ltd |
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| 5 | * |
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| 6 | * Authors: David Yang <yangxiaohua@everest-semi.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _ES8326_H |
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| 10 | #define _ES8326_H |
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| 11 | |
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| 12 | /* ES8326 register space */ |
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| 13 | #define ES8326_RESET 0x00 |
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| 14 | #define ES8326_CLK_CTL 0x01 |
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| 15 | #define ES8326_CLK_INV 0x02 |
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| 16 | #define ES8326_CLK_RESAMPLE 0x03 |
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| 17 | #define ES8326_CLK_DIV1 0x04 |
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| 18 | #define ES8326_CLK_DIV2 0x05 |
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| 19 | #define ES8326_CLK_DLL 0x06 |
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| 20 | #define ES8326_CLK_MUX 0x07 |
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| 21 | #define ES8326_CLK_ADC_SEL 0x08 |
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| 22 | #define ES8326_CLK_DAC_SEL 0x09 |
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| 23 | #define ES8326_CLK_ADC_OSR 0x0a |
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| 24 | #define ES8326_CLK_DAC_OSR 0x0b |
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| 25 | #define ES8326_CLK_DIV_CPC 0x0c |
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| 26 | #define ES8326_CLK_DIV_BCLK 0x0d |
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| 27 | #define ES8326_CLK_TRI 0x0e |
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| 28 | #define ES8326_CLK_DIV_LRCK 0x0f |
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| 29 | #define ES8326_CLK_VMIDS1 0x10 |
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| 30 | #define ES8326_CLK_VMIDS2 0x11 |
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| 31 | #define ES8326_CLK_CAL_TIME 0x12 |
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| 32 | #define ES8326_FMT 0x13 |
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| 33 | |
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| 34 | #define ES8326_DAC_MUTE 0x14 |
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| 35 | #define ES8326_ADC_MUTE 0x15 |
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| 36 | #define ES8326_ANA_PDN 0x16 |
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| 37 | #define ES8326_PGA_PDN 0x17 |
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| 38 | #define ES8326_VMIDSEL 0x18 |
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| 39 | #define ES8326_ANA_LP 0x19 |
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| 40 | #define ES8326_ANA_DMS 0x1a |
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| 41 | #define ES8326_ANA_MICBIAS 0x1b |
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| 42 | #define ES8326_ANA_VSEL 0x1c |
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| 43 | #define ES8326_SYS_BIAS 0x1d |
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| 44 | #define ES8326_BIAS_SW1 0x1e |
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| 45 | #define ES8326_BIAS_SW2 0x1f |
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| 46 | #define ES8326_BIAS_SW3 0x20 |
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| 47 | #define ES8326_BIAS_SW4 0x21 |
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| 48 | #define ES8326_VMIDLOW 0x22 |
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| 49 | #define ES8326_PGAGAIN 0x23 |
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| 50 | #define ES8326_HP_DRIVER 0x24 |
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| 51 | #define ES8326_DAC2HPMIX 0x25 |
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| 52 | #define ES8326_HP_VOL 0x26 |
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| 53 | #define ES8326_HP_CAL 0x27 |
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| 54 | #define ES8326_HP_DRIVER_REF 0x28 |
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| 55 | #define ES8326_ADC_SCALE 0x29 |
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| 56 | #define ES8326_ADC1_SRC 0x2a |
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| 57 | #define ES8326_ADC2_SRC 0x2b |
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| 58 | #define ES8326_ADC1_VOL 0x2c |
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| 59 | #define ES8326_ADC2_VOL 0x2d |
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| 60 | #define ES8326_ADC_RAMPRATE 0x2e |
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| 61 | #define ES8326_ALC_RECOVERY 0x32 |
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| 62 | #define ES8326_ALC_LEVEL 0x33 |
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| 63 | #define ES8326_ADC_HPFS1 0x34 |
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| 64 | #define ES8326_ADC_HPFS2 0x35 |
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| 65 | #define ES8326_ADC_EQ 0x36 |
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| 66 | #define ES8326_HP_OFFSET_CAL 0x4A |
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| 67 | #define ES8326_HPL_OFFSET_INI 0x4B |
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| 68 | #define ES8326_HPR_OFFSET_INI 0x4C |
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| 69 | #define ES8326_DAC_DSM 0x4D |
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| 70 | #define ES8326_DAC_RAMPRATE 0x4E |
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| 71 | #define ES8326_DAC_VPPSCALE 0x4F |
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| 72 | #define ES8326_DACL_VOL 0x50 |
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| 73 | #define ES8326_DRC_RECOVERY 0x53 |
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| 74 | #define ES8326_DRC_WINSIZE 0x54 |
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| 75 | #define ES8326_DAC_CROSSTALK 0x55 |
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| 76 | #define ES8326_HPJACK_TIMER 0x56 |
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| 77 | #define ES8326_HPDET_TYPE 0x57 |
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| 78 | #define ES8326_INT_SOURCE 0x58 |
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| 79 | #define ES8326_INTOUT_IO 0x59 |
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| 80 | #define ES8326_SDINOUT1_IO 0x5A |
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| 81 | #define ES8326_SDINOUT23_IO 0x5B |
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| 82 | #define ES8326_JACK_PULSE 0x5C |
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| 83 | |
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| 84 | #define ES8326_DACR_VOL 0xF4 |
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| 85 | #define ES8326_SPKL_VOL 0xF5 |
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| 86 | #define ES8326_SPKR_VOL 0xF6 |
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| 87 | #define ES8326_HP_MISC 0xF7 |
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| 88 | #define ES8326_CTIA_OMTP_STA 0xF8 |
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| 89 | #define ES8326_PULLUP_CTL 0xF9 |
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| 90 | #define ES8326_CSM_I2C_STA 0xFA |
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| 91 | #define ES8326_HPDET_STA 0xFB |
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| 92 | #define ES8326_CSM_MUTE_STA 0xFC |
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| 93 | #define ES8326_CHIP_ID1 0xFD |
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| 94 | #define ES8326_CHIP_ID2 0xFE |
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| 95 | #define ES8326_CHIP_VERSION 0xFF |
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| 96 | |
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| 97 | /* ES8326_RESET */ |
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| 98 | #define ES8326_CSM_ON (1 << 7) |
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| 99 | #define ES8326_MASTER_MODE_EN (1 << 6) |
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| 100 | #define ES8326_PWRUP_SEQ_EN (1 << 5) |
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| 101 | #define ES8326_CODEC_RESET (0x0f << 0) |
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| 102 | #define ES8326_CSM_OFF (0 << 7) |
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| 103 | #define ES8326_MUTE_MASK (3 << 0) |
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| 104 | #define ES8326_MUTE (3 << 0) |
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| 105 | |
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| 106 | /* ES8326_CLK_CTL */ |
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| 107 | #define ES8326_CLK_ON (0x7f << 0) |
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| 108 | #define ES8326_CLK_OFF (0 << 0) |
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| 109 | |
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| 110 | /* ES8326_CLK_INV */ |
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| 111 | #define ES8326_BCLK_AS_MCLK (1 << 3) |
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| 112 | |
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| 113 | /* ES8326_FMT */ |
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| 114 | #define ES8326_S24_LE (0 << 2) |
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| 115 | #define ES8326_S20_3_LE (1 << 2) |
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| 116 | #define ES8326_S18_LE (2 << 2) |
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| 117 | #define ES8326_S16_LE (3 << 2) |
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| 118 | #define ES8326_S32_LE (4 << 2) |
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| 119 | #define ES8326_DATA_LEN_MASK (7 << 2) |
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| 120 | |
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| 121 | #define ES8326_DAIFMT_MASK ((1 << 5) | (3 << 0)) |
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| 122 | #define ES8326_DAIFMT_I2S 0 |
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| 123 | #define ES8326_DAIFMT_LEFT_J (1 << 0) |
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| 124 | #define ES8326_DAIFMT_DSP_A (3 << 0) |
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| 125 | #define ES8326_DAIFMT_DSP_B ((1 << 5) | (3 << 0)) |
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| 126 | |
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| 127 | /* ES8326_PGAGAIN */ |
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| 128 | #define ES8326_MIC_SEL_MASK (3 << 4) |
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| 129 | #define ES8326_MIC1_SEL (1 << 4) |
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| 130 | #define ES8326_MIC2_SEL (1 << 5) |
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| 131 | |
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| 132 | /* ES8326_HP_CAL */ |
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| 133 | #define ES8326_HP_OFF 0 |
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| 134 | #define ES8326_HP_FORCE_CAL ((1 << 7) | (1 << 3)) |
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| 135 | #define ES8326_HP_ON ((7 << 4) | (7 << 0)) |
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| 136 | |
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| 137 | /* ES8326_ADC1_SRC */ |
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| 138 | #define ES8326_ADC1_SHIFT 0 |
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| 139 | #define ES8326_ADC2_SHIFT 4 |
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| 140 | #define ES8326_ADC_SRC_ANA 0 |
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| 141 | #define ES8326_ADC_SRC_ANA_INV_SW0 1 |
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| 142 | #define ES8326_ADC_SRC_ANA_INV_SW1 2 |
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| 143 | #define ES8326_ADC_SRC_DMIC_MCLK 3 |
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| 144 | #define ES8326_ADC_SRC_DMIC_SDIN2 4 |
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| 145 | #define ES8326_ADC_SRC_DMIC_SDIN2_INV 5 |
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| 146 | #define ES8326_ADC_SRC_DMIC_SDIN3 6 |
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| 147 | #define ES8326_ADC_SRC_DMIC_SDIN3_INV 7 |
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| 148 | |
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| 149 | #define ES8326_ADC_AMIC ((ES8326_ADC_SRC_ANA_INV_SW1 << ES8326_ADC2_SHIFT) \ |
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| 150 | | (ES8326_ADC_SRC_ANA_INV_SW1 << ES8326_ADC1_SHIFT)) |
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| 151 | #define ES8326_ADC_DMIC ((ES8326_ADC_SRC_DMIC_SDIN2 << ES8326_ADC2_SHIFT) \ |
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| 152 | | (ES8326_ADC_SRC_DMIC_SDIN2 << ES8326_ADC1_SHIFT)) |
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| 153 | /* ES8326_ADC2_SRC */ |
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| 154 | #define ES8326_ADC3_SHIFT 0 |
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| 155 | #define ES8326_ADC4_SHIFT 3 |
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| 156 | |
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| 157 | /* ES8326_HPDET_TYPE */ |
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| 158 | #define ES8326_HP_DET_SRC_PIN27 (1 << 5) |
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| 159 | #define ES8326_HP_DET_SRC_PIN9 (1 << 4) |
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| 160 | #define ES8326_HP_DET_JACK_POL (1 << 3) |
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| 161 | #define ES8326_HP_DET_BUTTON_POL (1 << 2) |
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| 162 | #define ES8326_HP_TYPE_OMTP (3 << 0) |
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| 163 | #define ES8326_HP_TYPE_CTIA (2 << 0) |
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| 164 | #define ES8326_HP_TYPE_AUTO (1 << 0) |
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| 165 | #define ES8326_HP_TYPE_AUTO_INV (0 << 0) |
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| 166 | |
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| 167 | /* ES8326_INT_SOURCE */ |
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| 168 | #define ES8326_INT_SRC_DAC_MOZ (1 << 0) |
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| 169 | #define ES8326_INT_SRC_ADC_MOZ (1 << 1) |
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| 170 | #define ES8326_INT_SRC_BUTTON (1 << 2) |
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| 171 | #define ES8326_INT_SRC_PIN9 (1 << 3) |
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| 172 | #define ES8326_INT_SRC_PIN27 (1 << 4) |
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| 173 | |
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| 174 | /* ES8326_SDINOUT1_IO */ |
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| 175 | #define ES8326_IO_INPUT (0 << 0) |
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| 176 | #define ES8326_IO_SDIN_SLOT0 (1 << 0) |
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| 177 | #define ES8326_IO_SDIN_SLOT1 (2 << 0) |
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| 178 | #define ES8326_IO_SDIN_SLOT2 (3 << 0) |
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| 179 | #define ES8326_IO_SDIN_SLOT7 (8 << 0) |
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| 180 | #define ES8326_IO_DMIC_CLK (9 << 0) |
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| 181 | #define ES8326_IO_DMIC_CLK_INV (0x0a << 0) |
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| 182 | #define ES8326_IO_SDOUT2 (0x0b << 0) |
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| 183 | #define ES8326_IO_LOW (0x0e << 0) |
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| 184 | #define ES8326_IO_HIGH (0x0f << 0) |
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| 185 | #define ES8326_ADC2DAC (1 << 3) |
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| 186 | #define ES8326_SDINOUT1_SHIFT 4 |
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| 187 | |
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| 188 | /* ES8326_SDINOUT23_IO */ |
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| 189 | #define ES8326_SDINOUT2_SHIFT 4 |
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| 190 | #define ES8326_SDINOUT3_SHIFT 0 |
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| 191 | |
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| 192 | /* ES8326_HPDET_STA */ |
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| 193 | #define ES8326_HPINSERT_FLAG (1 << 1) |
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| 194 | #define ES8326_HPBUTTON_FLAG (1 << 0) |
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| 195 | |
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| 196 | /* ES8326_CHIP_VERSION 0xFF */ |
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| 197 | #define ES8326_VERSION (1 << 0) |
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| 198 | #define ES8326_VERSION_B (3 << 0) |
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| 199 | |
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| 200 | #endif |
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| 201 | |
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