| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * lm49453.h - LM49453 ALSA Soc Audio drive |
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| 4 | * |
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| 5 | * Copyright (c) 2012 Texas Instruments, Inc |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _LM49453_H |
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| 9 | #define _LM49453_H |
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| 10 | |
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| 11 | #include <linux/bitops.h> |
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| 12 | |
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| 13 | /* LM49453_P0 register space for page0 */ |
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| 14 | #define LM49453_P0_PMC_SETUP_REG 0x00 |
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| 15 | #define LM49453_P0_PLL_CLK_SEL1_REG 0x01 |
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| 16 | #define LM49453_P0_PLL_CLK_SEL2_REG 0x02 |
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| 17 | #define LM49453_P0_PMC_CLK_DIV_REG 0x03 |
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| 18 | #define LM49453_P0_HSDET_CLK_DIV_REG 0x04 |
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| 19 | #define LM49453_P0_DMIC_CLK_DIV_REG 0x05 |
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| 20 | #define LM49453_P0_ADC_CLK_DIV_REG 0x06 |
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| 21 | #define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07 |
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| 22 | #define LM49453_P0_PLL_HF_M_REG 0x08 |
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| 23 | #define LM49453_P0_PLL_LF_M_REG 0x09 |
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| 24 | #define LM49453_P0_PLL_NL_REG 0x0A |
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| 25 | #define LM49453_P0_PLL_N_MODL_REG 0x0B |
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| 26 | #define LM49453_P0_PLL_N_MODH_REG 0x0C |
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| 27 | #define LM49453_P0_PLL_P1_REG 0x0D |
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| 28 | #define LM49453_P0_PLL_P2_REG 0x0E |
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| 29 | #define LM49453_P0_FLL_REF_FREQL_REG 0x0F |
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| 30 | #define LM49453_P0_FLL_REF_FREQH_REG 0x10 |
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| 31 | #define LM49453_P0_VCO_TARGETLL_REG 0x11 |
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| 32 | #define LM49453_P0_VCO_TARGETLH_REG 0x12 |
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| 33 | #define LM49453_P0_VCO_TARGETHL_REG 0x13 |
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| 34 | #define LM49453_P0_VCO_TARGETHH_REG 0x14 |
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| 35 | #define LM49453_P0_PLL_CONFIG_REG 0x15 |
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| 36 | #define LM49453_P0_DAC_CLK_SEL_REG 0x16 |
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| 37 | #define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17 |
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| 38 | |
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| 39 | /* Analog Mixer Input Stages */ |
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| 40 | #define LM49453_P0_MICL_REG 0x20 |
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| 41 | #define LM49453_P0_MICR_REG 0x21 |
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| 42 | #define LM49453_P0_EP_REG 0x24 |
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| 43 | #define LM49453_P0_DIS_PKVL_FB_REG 0x25 |
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| 44 | |
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| 45 | /* Analog Mixer Output Stages */ |
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| 46 | #define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E |
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| 47 | |
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| 48 | /*ADC or DAC */ |
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| 49 | #define LM49453_P0_ADC_DSP_REG 0x30 |
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| 50 | #define LM49453_P0_DAC_DSP_REG 0x31 |
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| 51 | |
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| 52 | /* EFFECTS ENABLES */ |
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| 53 | #define LM49453_P0_ADC_FX_ENABLES_REG 0x33 |
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| 54 | |
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| 55 | /* GPIO */ |
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| 56 | #define LM49453_P0_GPIO1_REG 0x38 |
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| 57 | #define LM49453_P0_GPIO2_REG 0x39 |
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| 58 | #define LM49453_P0_GPIO3_REG 0x3A |
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| 59 | #define LM49453_P0_HAP_CTL_REG 0x3B |
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| 60 | #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C |
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| 61 | #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D |
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| 62 | #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E |
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| 63 | #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F |
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| 64 | |
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| 65 | /* DIGITAL MIXER */ |
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| 66 | #define LM49453_P0_DMIX_CLK_SEL_REG 0x40 |
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| 67 | #define LM49453_P0_PORT1_RX_LVL1_REG 0x41 |
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| 68 | #define LM49453_P0_PORT1_RX_LVL2_REG 0x42 |
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| 69 | #define LM49453_P0_PORT2_RX_LVL_REG 0x43 |
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| 70 | #define LM49453_P0_PORT1_TX1_REG 0x44 |
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| 71 | #define LM49453_P0_PORT1_TX2_REG 0x45 |
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| 72 | #define LM49453_P0_PORT1_TX3_REG 0x46 |
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| 73 | #define LM49453_P0_PORT1_TX4_REG 0x47 |
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| 74 | #define LM49453_P0_PORT1_TX5_REG 0x48 |
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| 75 | #define LM49453_P0_PORT1_TX6_REG 0x49 |
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| 76 | #define LM49453_P0_PORT1_TX7_REG 0x4A |
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| 77 | #define LM49453_P0_PORT1_TX8_REG 0x4B |
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| 78 | #define LM49453_P0_PORT2_TX1_REG 0x4C |
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| 79 | #define LM49453_P0_PORT2_TX2_REG 0x4D |
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| 80 | #define LM49453_P0_STN_SEL_REG 0x4F |
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| 81 | #define LM49453_P0_DACHPL1_REG 0x50 |
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| 82 | #define LM49453_P0_DACHPL2_REG 0x51 |
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| 83 | #define LM49453_P0_DACHPR1_REG 0x52 |
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| 84 | #define LM49453_P0_DACHPR2_REG 0x53 |
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| 85 | #define LM49453_P0_DACLOL1_REG 0x54 |
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| 86 | #define LM49453_P0_DACLOL2_REG 0x55 |
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| 87 | #define LM49453_P0_DACLOR1_REG 0x56 |
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| 88 | #define LM49453_P0_DACLOR2_REG 0x57 |
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| 89 | #define LM49453_P0_DACLSL1_REG 0x58 |
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| 90 | #define LM49453_P0_DACLSL2_REG 0x59 |
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| 91 | #define LM49453_P0_DACLSR1_REG 0x5A |
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| 92 | #define LM49453_P0_DACLSR2_REG 0x5B |
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| 93 | #define LM49453_P0_DACHAL1_REG 0x5C |
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| 94 | #define LM49453_P0_DACHAL2_REG 0x5D |
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| 95 | #define LM49453_P0_DACHAR1_REG 0x5E |
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| 96 | #define LM49453_P0_DACHAR2_REG 0x5F |
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| 97 | |
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| 98 | /* AUDIO PORT 1 (TDM) */ |
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| 99 | #define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60 |
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| 100 | #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61 |
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| 101 | #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62 |
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| 102 | #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63 |
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| 103 | #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64 |
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| 104 | #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65 |
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| 105 | #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66 |
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| 106 | #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67 |
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| 107 | #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68 |
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| 108 | #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69 |
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| 109 | |
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| 110 | /* AUDIO PORT 2 */ |
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| 111 | #define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A |
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| 112 | #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B |
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| 113 | #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C |
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| 114 | #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D |
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| 115 | #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E |
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| 116 | #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F |
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| 117 | #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70 |
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| 118 | |
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| 119 | /* SAMPLE RATE */ |
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| 120 | #define LM49453_P0_PORT1_SR_LSB_REG 0x79 |
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| 121 | #define LM49453_P0_PORT1_SR_MSB_REG 0x7A |
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| 122 | #define LM49453_P0_PORT2_SR_LSB_REG 0x7B |
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| 123 | #define LM49453_P0_PORT2_SR_MSB_REG 0x7C |
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| 124 | |
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| 125 | /* EFFECTS - HPFs */ |
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| 126 | #define LM49453_P0_HPF_REG 0x80 |
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| 127 | |
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| 128 | /* EFFECTS ADC ALC */ |
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| 129 | #define LM49453_P0_ADC_ALC1_REG 0x82 |
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| 130 | #define LM49453_P0_ADC_ALC2_REG 0x83 |
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| 131 | #define LM49453_P0_ADC_ALC3_REG 0x84 |
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| 132 | #define LM49453_P0_ADC_ALC4_REG 0x85 |
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| 133 | #define LM49453_P0_ADC_ALC5_REG 0x86 |
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| 134 | #define LM49453_P0_ADC_ALC6_REG 0x87 |
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| 135 | #define LM49453_P0_ADC_ALC7_REG 0x88 |
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| 136 | #define LM49453_P0_ADC_ALC8_REG 0x89 |
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| 137 | #define LM49453_P0_DMIC1_LEVELL_REG 0x8A |
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| 138 | #define LM49453_P0_DMIC1_LEVELR_REG 0x8B |
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| 139 | #define LM49453_P0_DMIC2_LEVELL_REG 0x8C |
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| 140 | #define LM49453_P0_DMIC2_LEVELR_REG 0x8D |
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| 141 | #define LM49453_P0_ADC_LEVELL_REG 0x8E |
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| 142 | #define LM49453_P0_ADC_LEVELR_REG 0x8F |
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| 143 | #define LM49453_P0_DAC_HP_LEVELL_REG 0x90 |
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| 144 | #define LM49453_P0_DAC_HP_LEVELR_REG 0x91 |
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| 145 | #define LM49453_P0_DAC_LO_LEVELL_REG 0x92 |
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| 146 | #define LM49453_P0_DAC_LO_LEVELR_REG 0x93 |
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| 147 | #define LM49453_P0_DAC_LS_LEVELL_REG 0x94 |
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| 148 | #define LM49453_P0_DAC_LS_LEVELR_REG 0x95 |
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| 149 | #define LM49453_P0_DAC_HA_LEVELL_REG 0x96 |
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| 150 | #define LM49453_P0_DAC_HA_LEVELR_REG 0x97 |
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| 151 | #define LM49453_P0_SOFT_MUTE_REG 0x98 |
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| 152 | #define LM49453_P0_DMIC_MUTE_CFG_REG 0x99 |
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| 153 | #define LM49453_P0_ADC_MUTE_CFG_REG 0x9A |
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| 154 | #define LM49453_P0_DAC_MUTE_CFG_REG 0x9B |
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| 155 | |
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| 156 | /*DIGITAL MIC1 */ |
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| 157 | #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0 |
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| 158 | #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1 |
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| 159 | #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2 |
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| 160 | |
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| 161 | /*DIGITAL MIC2 */ |
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| 162 | #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3 |
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| 163 | #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4 |
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| 164 | #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5 |
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| 165 | |
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| 166 | /* ADC DECIMATOR */ |
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| 167 | #define LM49453_P0_ADC_DECIMATOR_REG 0xB6 |
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| 168 | |
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| 169 | /* DAC CONFIGURE */ |
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| 170 | #define LM49453_P0_DAC_CONFIG_REG 0xB7 |
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| 171 | |
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| 172 | /* SIDETONE */ |
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| 173 | #define LM49453_P0_STN_VOL_ADCL_REG 0xB8 |
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| 174 | #define LM49453_P0_STN_VOL_ADCR_REG 0xB9 |
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| 175 | #define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA |
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| 176 | #define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB |
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| 177 | #define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC |
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| 178 | #define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD |
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| 179 | |
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| 180 | /* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */ |
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| 181 | #define LM49453_P0_ADC_DEC_CLIP_REG 0xC2 |
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| 182 | #define LM49453_P0_ADC_HPF_CLIP_REG 0xC3 |
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| 183 | #define LM49453_P0_ADC_LVL_CLIP_REG 0xC4 |
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| 184 | #define LM49453_P0_DAC_LVL_CLIP_REG 0xC5 |
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| 185 | |
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| 186 | /* ADC ALC EFFECT MONITORS (Read Only) */ |
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| 187 | #define LM49453_P0_ADC_LVLMONL_REG 0xC8 |
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| 188 | #define LM49453_P0_ADC_LVLMONR_REG 0xC9 |
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| 189 | #define LM49453_P0_ADC_ALCMONL_REG 0xCA |
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| 190 | #define LM49453_P0_ADC_ALCMONR_REG 0xCB |
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| 191 | #define LM49453_P0_ADC_MUTED_REG 0xCC |
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| 192 | #define LM49453_P0_DAC_MUTED_REG 0xCD |
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| 193 | |
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| 194 | /* HEADSET DETECT */ |
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| 195 | #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0 |
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| 196 | #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1 |
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| 197 | #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2 |
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| 198 | #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3 |
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| 199 | #define LM49453_P0_HSD_TIMEOUT1_REG 0xD4 |
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| 200 | #define LM49453_P0_HSD_TIMEOUT2_REG 0xD5 |
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| 201 | #define LM49453_P0_HSD_TIMEOUT3_REG 0xD6 |
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| 202 | #define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7 |
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| 203 | #define LM49453_P0_HSD_IRQ1_REG 0xD8 |
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| 204 | #define LM49453_P0_HSD_IRQ2_REG 0xD9 |
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| 205 | #define LM49453_P0_HSD_IRQ3_REG 0xDA |
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| 206 | #define LM49453_P0_HSD_IRQ4_REG 0xDB |
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| 207 | #define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC |
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| 208 | #define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD |
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| 209 | #define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE |
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| 210 | #define LM49453_P0_HSD_R_HPLL_REG 0xE0 |
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| 211 | #define LM49453_P0_HSD_R_HPLH_REG 0xE1 |
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| 212 | #define LM49453_P0_HSD_R_HPLU_REG 0xE2 |
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| 213 | #define LM49453_P0_HSD_R_HPRL_REG 0xE3 |
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| 214 | #define LM49453_P0_HSD_R_HPRH_REG 0xE4 |
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| 215 | #define LM49453_P0_HSD_R_HPRU_REG 0xE5 |
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| 216 | #define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6 |
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| 217 | #define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7 |
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| 218 | #define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8 |
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| 219 | #define LM49453_P0_HSD_RO_FINALL_REG 0xE9 |
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| 220 | #define LM49453_P0_HSD_RO_FINALH_REG 0xEA |
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| 221 | #define LM49453_P0_HSD_RO_FINALU_REG 0xEB |
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| 222 | #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC |
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| 223 | #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED |
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| 224 | #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE |
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| 225 | #define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF |
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| 226 | #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1 |
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| 227 | #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2 |
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| 228 | #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3 |
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| 229 | #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4 |
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| 230 | #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5 |
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| 231 | |
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| 232 | /* I/O PULLDOWN CONFIG */ |
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| 233 | #define LM49453_P0_PULL_CONFIG1_REG 0xF8 |
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| 234 | #define LM49453_P0_PULL_CONFIG2_REG 0xF9 |
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| 235 | #define LM49453_P0_PULL_CONFIG3_REG 0xFA |
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| 236 | |
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| 237 | /* RESET */ |
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| 238 | #define LM49453_P0_RESET_REG 0xFE |
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| 239 | |
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| 240 | /* PAGE */ |
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| 241 | #define LM49453_PAGE_REG 0xFF |
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| 242 | |
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| 243 | #define LM49453_MAX_REGISTER (0xFF+1) |
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| 244 | |
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| 245 | /* LM49453_P0_PMC_SETUP_REG (0x00h) */ |
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| 246 | #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0)) |
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| 247 | #define LM49453_PMC_SETUP_PLL_EN BIT(2) |
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| 248 | #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3) |
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| 249 | #define LM49453_PMC_SETUP_PLL_FLL BIT(4) |
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| 250 | #define LM49453_PMC_SETUP_MCLK_OVER BIT(5) |
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| 251 | #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6) |
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| 252 | #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7) |
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| 253 | |
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| 254 | /* Chip Enable bits */ |
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| 255 | #define LM49453_CHIP_EN_SHUTDOWN 0x00 |
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| 256 | #define LM49453_CHIP_EN 0x01 |
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| 257 | #define LM49453_CHIP_EN_HSD_DETECT 0x02 |
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| 258 | #define LM49453_CHIP_EN_INVALID_HSD 0x03 |
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| 259 | |
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| 260 | /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ |
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| 261 | #define LM49453_CLK_SEL1_MCLK_SEL 0x11 |
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| 262 | #define LM49453_CLK_SEL1_RTC_SEL 0x11 |
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| 263 | #define LM49453_CLK_SEL1_PORT1_SEL 0x10 |
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| 264 | #define LM49453_CLK_SEL1_PORT2_SEL 0x11 |
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| 265 | |
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| 266 | /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ |
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| 267 | #define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38 |
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| 268 | |
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| 269 | /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ |
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| 270 | #define LM49453_FLL_REF_FREQ_VAL 0x8ca0001 |
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| 271 | |
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| 272 | /* LM49453_P0_VCO_TARGETLL_REG (0x11) */ |
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| 273 | #define LM49453_VCO_TARGET_VAL 0x8ca0001 |
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| 274 | |
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| 275 | /* LM49453_P0_ADC_DSP_REG (0x30h) */ |
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| 276 | #define LM49453_ADC_DSP_ADC_MUTEL BIT(0) |
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| 277 | #define LM49453_ADC_DSP_ADC_MUTER BIT(1) |
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| 278 | #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2) |
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| 279 | #define LM49453_ADC_DSP_DMIC1_MUTER BIT(3) |
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| 280 | #define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4) |
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| 281 | #define LM49453_ADC_DSP_DMIC2_MUTER BIT(5) |
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| 282 | #define LM49453_ADC_DSP_MUTE_ALL 0x3F |
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| 283 | |
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| 284 | /* LM49453_P0_DAC_DSP_REG (0x31h) */ |
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| 285 | #define LM49453_DAC_DSP_MUTE_ALL 0xFF |
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| 286 | |
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| 287 | /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ |
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| 288 | #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3)) |
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| 289 | #define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3) |
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| 290 | #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4) |
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| 291 | |
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| 292 | /* LM49453_P0_RESET_REG (0xFEh) */ |
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| 293 | #define LM49453_RESET_REG_RST BIT(0) |
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| 294 | |
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| 295 | /* Page select register bits (0xFF) */ |
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| 296 | #define LM49453_PAGE0_SELECT 0x0 |
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| 297 | #define LM49453_PAGE1_SELECT 0x1 |
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| 298 | |
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| 299 | /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */ |
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| 300 | #define LM49453_JACK_DISABLE 0x00 |
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| 301 | #define LM49453_JACK_CONFIG1 0x01 |
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| 302 | #define LM49453_JACK_CONFIG2 0x02 |
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| 303 | #define LM49453_JACK_CONFIG3 0x03 |
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| 304 | #define LM49453_JACK_CONFIG4 0x04 |
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| 305 | #define LM49453_JACK_CONFIG5 0x05 |
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| 306 | |
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| 307 | /* Page 1 REGISTERS */ |
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| 308 | |
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| 309 | /* SIDETONE */ |
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| 310 | #define LM49453_P1_SIDETONE_SA0L_REG 0x80 |
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| 311 | #define LM49453_P1_SIDETONE_SA0H_REG 0x81 |
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| 312 | #define LM49453_P1_SIDETONE_SAB0U_REG 0x82 |
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| 313 | #define LM49453_P1_SIDETONE_SB0L_REG 0x83 |
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| 314 | #define LM49453_P1_SIDETONE_SB0H_REG 0x84 |
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| 315 | #define LM49453_P1_SIDETONE_SH0L_REG 0x85 |
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| 316 | #define LM49453_P1_SIDETONE_SH0H_REG 0x86 |
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| 317 | #define LM49453_P1_SIDETONE_SH0U_REG 0x87 |
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| 318 | #define LM49453_P1_SIDETONE_SA1L_REG 0x88 |
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| 319 | #define LM49453_P1_SIDETONE_SA1H_REG 0x89 |
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| 320 | #define LM49453_P1_SIDETONE_SAB1U_REG 0x8A |
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| 321 | #define LM49453_P1_SIDETONE_SB1L_REG 0x8B |
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| 322 | #define LM49453_P1_SIDETONE_SB1H_REG 0x8C |
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| 323 | #define LM49453_P1_SIDETONE_SH1L_REG 0x8D |
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| 324 | #define LM49453_P1_SIDETONE_SH1H_REG 0x8E |
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| 325 | #define LM49453_P1_SIDETONE_SH1U_REG 0x8F |
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| 326 | #define LM49453_P1_SIDETONE_SA2L_REG 0x90 |
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| 327 | #define LM49453_P1_SIDETONE_SA2H_REG 0x91 |
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| 328 | #define LM49453_P1_SIDETONE_SAB2U_REG 0x92 |
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| 329 | #define LM49453_P1_SIDETONE_SB2L_REG 0x93 |
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| 330 | #define LM49453_P1_SIDETONE_SB2H_REG 0x94 |
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| 331 | #define LM49453_P1_SIDETONE_SH2L_REG 0x95 |
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| 332 | #define LM49453_P1_SIDETONE_SH2H_REG 0x96 |
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| 333 | #define LM49453_P1_SIDETONE_SH2U_REG 0x97 |
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| 334 | #define LM49453_P1_SIDETONE_SA3L_REG 0x98 |
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| 335 | #define LM49453_P1_SIDETONE_SA3H_REG 0x99 |
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| 336 | #define LM49453_P1_SIDETONE_SAB3U_REG 0x9A |
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| 337 | #define LM49453_P1_SIDETONE_SB3L_REG 0x9B |
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| 338 | #define LM49453_P1_SIDETONE_SB3H_REG 0x9C |
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| 339 | #define LM49453_P1_SIDETONE_SH3L_REG 0x9D |
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| 340 | #define LM49453_P1_SIDETONE_SH3H_REG 0x9E |
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| 341 | #define LM49453_P1_SIDETONE_SH3U_REG 0x9F |
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| 342 | #define LM49453_P1_SIDETONE_SA4L_REG 0xA0 |
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| 343 | #define LM49453_P1_SIDETONE_SA4H_REG 0xA1 |
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| 344 | #define LM49453_P1_SIDETONE_SAB4U_REG 0xA2 |
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| 345 | #define LM49453_P1_SIDETONE_SB4L_REG 0xA3 |
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| 346 | #define LM49453_P1_SIDETONE_SB4H_REG 0xA4 |
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| 347 | #define LM49453_P1_SIDETONE_SH4L_REG 0xA5 |
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| 348 | #define LM49453_P1_SIDETONE_SH4H_REG 0xA6 |
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| 349 | #define LM49453_P1_SIDETONE_SH4U_REG 0xA7 |
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| 350 | #define LM49453_P1_SIDETONE_SA5L_REG 0xA8 |
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| 351 | #define LM49453_P1_SIDETONE_SA5H_REG 0xA9 |
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| 352 | #define LM49453_P1_SIDETONE_SAB5U_REG 0xAA |
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| 353 | #define LM49453_P1_SIDETONE_SB5L_REG 0xAB |
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| 354 | #define LM49453_P1_SIDETONE_SB5H_REG 0xAC |
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| 355 | #define LM49453_P1_SIDETONE_SH5L_REG 0xAD |
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| 356 | #define LM49453_P1_SIDETONE_SH5H_REG 0xAE |
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| 357 | #define LM49453_P1_SIDETONE_SH5U_REG 0xAF |
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| 358 | |
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| 359 | /* CHARGE PUMP CONFIG */ |
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| 360 | #define LM49453_P1_CP_CONFIG1_REG 0xB0 |
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| 361 | #define LM49453_P1_CP_CONFIG2_REG 0xB1 |
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| 362 | #define LM49453_P1_CP_CONFIG3_REG 0xB2 |
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| 363 | #define LM49453_P1_CP_CONFIG4_REG 0xB3 |
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| 364 | #define LM49453_P1_CP_LA_VTH1L_REG 0xB4 |
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| 365 | #define LM49453_P1_CP_LA_VTH1M_REG 0xB5 |
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| 366 | #define LM49453_P1_CP_LA_VTH2L_REG 0xB6 |
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| 367 | #define LM49453_P1_CP_LA_VTH2M_REG 0xB7 |
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| 368 | #define LM49453_P1_CP_LA_VTH3L_REG 0xB8 |
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| 369 | #define LM49453_P1_CP_LA_VTH3H_REG 0xB9 |
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| 370 | #define LM49453_P1_CP_CLK_DIV_REG 0xBA |
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| 371 | |
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| 372 | /* DAC */ |
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| 373 | #define LM49453_P1_DAC_CHOP_REG 0xC0 |
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| 374 | |
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| 375 | #define LM49453_CLK_SRC_MCLK 1 |
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| 376 | #endif |
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| 377 | |
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