| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * max98088.h -- MAX98088 ALSA SoC Audio driver |
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| 4 | * |
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| 5 | * Copyright 2010 Maxim Integrated Products |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _MAX98088_H |
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| 9 | #define _MAX98088_H |
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| 10 | |
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| 11 | /* |
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| 12 | * MAX98088 Registers Definition |
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| 13 | */ |
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| 14 | #define M98088_REG_00_IRQ_STATUS 0x00 |
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| 15 | #define M98088_REG_01_MIC_STATUS 0x01 |
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| 16 | #define M98088_REG_02_JACK_STATUS 0x02 |
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| 17 | #define M98088_REG_03_BATTERY_VOLTAGE 0x03 |
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| 18 | #define M98088_REG_0F_IRQ_ENABLE 0x0F |
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| 19 | #define M98088_REG_10_SYS_CLK 0x10 |
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| 20 | #define M98088_REG_11_DAI1_CLKMODE 0x11 |
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| 21 | #define M98088_REG_12_DAI1_CLKCFG_HI 0x12 |
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| 22 | #define M98088_REG_13_DAI1_CLKCFG_LO 0x13 |
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| 23 | #define M98088_REG_14_DAI1_FORMAT 0x14 |
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| 24 | #define M98088_REG_15_DAI1_CLOCK 0x15 |
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| 25 | #define M98088_REG_16_DAI1_IOCFG 0x16 |
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| 26 | #define M98088_REG_17_DAI1_TDM 0x17 |
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| 27 | #define M98088_REG_18_DAI1_FILTERS 0x18 |
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| 28 | #define M98088_REG_19_DAI2_CLKMODE 0x19 |
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| 29 | #define M98088_REG_1A_DAI2_CLKCFG_HI 0x1A |
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| 30 | #define M98088_REG_1B_DAI2_CLKCFG_LO 0x1B |
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| 31 | #define M98088_REG_1C_DAI2_FORMAT 0x1C |
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| 32 | #define M98088_REG_1D_DAI2_CLOCK 0x1D |
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| 33 | #define M98088_REG_1E_DAI2_IOCFG 0x1E |
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| 34 | #define M98088_REG_1F_DAI2_TDM 0x1F |
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| 35 | #define M98088_REG_20_DAI2_FILTERS 0x20 |
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| 36 | #define M98088_REG_21_SRC 0x21 |
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| 37 | #define M98088_REG_22_MIX_DAC 0x22 |
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| 38 | #define M98088_REG_23_MIX_ADC_LEFT 0x23 |
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| 39 | #define M98088_REG_24_MIX_ADC_RIGHT 0x24 |
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| 40 | #define M98088_REG_25_MIX_HP_LEFT 0x25 |
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| 41 | #define M98088_REG_26_MIX_HP_RIGHT 0x26 |
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| 42 | #define M98088_REG_27_MIX_HP_CNTL 0x27 |
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| 43 | #define M98088_REG_28_MIX_REC_LEFT 0x28 |
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| 44 | #define M98088_REG_29_MIX_REC_RIGHT 0x29 |
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| 45 | #define M98088_REG_2A_MIC_REC_CNTL 0x2A |
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| 46 | #define M98088_REG_2B_MIX_SPK_LEFT 0x2B |
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| 47 | #define M98088_REG_2C_MIX_SPK_RIGHT 0x2C |
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| 48 | #define M98088_REG_2D_MIX_SPK_CNTL 0x2D |
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| 49 | #define M98088_REG_2E_LVL_SIDETONE 0x2E |
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| 50 | #define M98088_REG_2F_LVL_DAI1_PLAY 0x2F |
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| 51 | #define M98088_REG_30_LVL_DAI1_PLAY_EQ 0x30 |
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| 52 | #define M98088_REG_31_LVL_DAI2_PLAY 0x31 |
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| 53 | #define M98088_REG_32_LVL_DAI2_PLAY_EQ 0x32 |
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| 54 | #define M98088_REG_33_LVL_ADC_L 0x33 |
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| 55 | #define M98088_REG_34_LVL_ADC_R 0x34 |
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| 56 | #define M98088_REG_35_LVL_MIC1 0x35 |
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| 57 | #define M98088_REG_36_LVL_MIC2 0x36 |
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| 58 | #define M98088_REG_37_LVL_INA 0x37 |
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| 59 | #define M98088_REG_38_LVL_INB 0x38 |
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| 60 | #define M98088_REG_39_LVL_HP_L 0x39 |
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| 61 | #define M98088_REG_3A_LVL_HP_R 0x3A |
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| 62 | #define M98088_REG_3B_LVL_REC_L 0x3B |
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| 63 | #define M98088_REG_3C_LVL_REC_R 0x3C |
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| 64 | #define M98088_REG_3D_LVL_SPK_L 0x3D |
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| 65 | #define M98088_REG_3E_LVL_SPK_R 0x3E |
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| 66 | #define M98088_REG_3F_MICAGC_CFG 0x3F |
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| 67 | #define M98088_REG_40_MICAGC_THRESH 0x40 |
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| 68 | #define M98088_REG_41_SPKDHP 0x41 |
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| 69 | #define M98088_REG_42_SPKDHP_THRESH 0x42 |
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| 70 | #define M98088_REG_43_SPKALC_COMP 0x43 |
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| 71 | #define M98088_REG_44_PWRLMT_CFG 0x44 |
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| 72 | #define M98088_REG_45_PWRLMT_TIME 0x45 |
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| 73 | #define M98088_REG_46_THDLMT_CFG 0x46 |
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| 74 | #define M98088_REG_47_CFG_AUDIO_IN 0x47 |
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| 75 | #define M98088_REG_48_CFG_MIC 0x48 |
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| 76 | #define M98088_REG_49_CFG_LEVEL 0x49 |
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| 77 | #define M98088_REG_4A_CFG_BYPASS 0x4A |
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| 78 | #define M98088_REG_4B_CFG_JACKDET 0x4B |
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| 79 | #define M98088_REG_4C_PWR_EN_IN 0x4C |
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| 80 | #define M98088_REG_4D_PWR_EN_OUT 0x4D |
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| 81 | #define M98088_REG_4E_BIAS_CNTL 0x4E |
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| 82 | #define M98088_REG_4F_DAC_BIAS1 0x4F |
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| 83 | #define M98088_REG_50_DAC_BIAS2 0x50 |
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| 84 | #define M98088_REG_51_PWR_SYS 0x51 |
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| 85 | #define M98088_REG_52_DAI1_EQ_BASE 0x52 |
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| 86 | #define M98088_REG_84_DAI2_EQ_BASE 0x84 |
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| 87 | #define M98088_REG_B6_DAI1_BIQUAD_BASE 0xB6 |
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| 88 | #define M98088_REG_C0_DAI2_BIQUAD_BASE 0xC0 |
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| 89 | #define M98088_REG_FF_REV_ID 0xFF |
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| 90 | |
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| 91 | #define M98088_REG_CNT (0xFF+1) |
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| 92 | |
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| 93 | /* MAX98088 Registers Bit Fields */ |
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| 94 | |
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| 95 | /* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ |
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| 96 | #define M98088_CLKMODE_MASK 0xFF |
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| 97 | |
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| 98 | /* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ |
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| 99 | #define M98088_DAI_MAS (1<<7) |
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| 100 | #define M98088_DAI_WCI (1<<6) |
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| 101 | #define M98088_DAI_BCI (1<<5) |
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| 102 | #define M98088_DAI_DLY (1<<4) |
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| 103 | #define M98088_DAI_TDM (1<<2) |
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| 104 | #define M98088_DAI_FSW (1<<1) |
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| 105 | #define M98088_DAI_WS (1<<0) |
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| 106 | |
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| 107 | /* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ |
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| 108 | #define M98088_DAI_BSEL64 (1<<0) |
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| 109 | #define M98088_DAI_OSR64 (1<<6) |
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| 110 | |
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| 111 | /* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ |
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| 112 | #define M98088_S1NORMAL (1<<6) |
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| 113 | #define M98088_S2NORMAL (2<<6) |
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| 114 | #define M98088_SDATA (3<<0) |
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| 115 | |
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| 116 | /* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ |
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| 117 | #define M98088_DAI_DHF (1<<3) |
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| 118 | |
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| 119 | /* M98088_REG_22_MIX_DAC */ |
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| 120 | #define M98088_DAI1L_TO_DACL (1<<7) |
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| 121 | #define M98088_DAI1R_TO_DACL (1<<6) |
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| 122 | #define M98088_DAI2L_TO_DACL (1<<5) |
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| 123 | #define M98088_DAI2R_TO_DACL (1<<4) |
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| 124 | #define M98088_DAI1L_TO_DACR (1<<3) |
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| 125 | #define M98088_DAI1R_TO_DACR (1<<2) |
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| 126 | #define M98088_DAI2L_TO_DACR (1<<1) |
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| 127 | #define M98088_DAI2R_TO_DACR (1<<0) |
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| 128 | |
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| 129 | /* M98088_REG_2A_MIC_REC_CNTL */ |
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| 130 | #define M98088_REC_LINEMODE (1<<7) |
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| 131 | #define M98088_REC_LINEMODE_MASK (1<<7) |
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| 132 | |
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| 133 | /* M98088_REG_2D_MIX_SPK_CNTL */ |
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| 134 | #define M98088_MIX_SPKR_GAIN_MASK (3<<2) |
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| 135 | #define M98088_MIX_SPKR_GAIN_SHIFT 2 |
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| 136 | #define M98088_MIX_SPKL_GAIN_MASK (3<<0) |
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| 137 | #define M98088_MIX_SPKL_GAIN_SHIFT 0 |
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| 138 | |
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| 139 | /* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ |
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| 140 | #define M98088_DAI_MUTE (1<<7) |
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| 141 | #define M98088_DAI_MUTE_MASK (1<<7) |
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| 142 | #define M98088_DAI_VOICE_GAIN_MASK (3<<4) |
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| 143 | #define M98088_DAI_ATTENUATION_MASK (0xF<<0) |
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| 144 | #define M98088_DAI_ATTENUATION_SHIFT 0 |
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| 145 | |
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| 146 | /* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ |
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| 147 | #define M98088_MICPRE_MASK (3<<5) |
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| 148 | #define M98088_MICPRE_SHIFT 5 |
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| 149 | |
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| 150 | /* M98088_REG_3A_LVL_HP_R */ |
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| 151 | #define M98088_HP_MUTE (1<<7) |
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| 152 | |
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| 153 | /* M98088_REG_3C_LVL_REC_R */ |
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| 154 | #define M98088_REC_MUTE (1<<7) |
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| 155 | |
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| 156 | /* M98088_REG_3E_LVL_SPK_R */ |
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| 157 | #define M98088_SP_MUTE (1<<7) |
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| 158 | |
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| 159 | /* M98088_REG_48_CFG_MIC */ |
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| 160 | #define M98088_EXTMIC_MASK (3<<0) |
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| 161 | #define M98088_DIGMIC_L (1<<5) |
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| 162 | #define M98088_DIGMIC_R (1<<4) |
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| 163 | |
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| 164 | /* M98088_REG_49_CFG_LEVEL */ |
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| 165 | #define M98088_VSEN (1<<6) |
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| 166 | #define M98088_ZDEN (1<<5) |
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| 167 | #define M98088_EQ2EN (1<<1) |
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| 168 | #define M98088_EQ1EN (1<<0) |
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| 169 | |
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| 170 | /* M98088_REG_4C_PWR_EN_IN */ |
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| 171 | #define M98088_INAEN (1<<7) |
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| 172 | #define M98088_INBEN (1<<6) |
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| 173 | #define M98088_MBEN (1<<3) |
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| 174 | #define M98088_ADLEN (1<<1) |
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| 175 | #define M98088_ADREN (1<<0) |
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| 176 | |
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| 177 | /* M98088_REG_4D_PWR_EN_OUT */ |
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| 178 | #define M98088_HPLEN (1<<7) |
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| 179 | #define M98088_HPREN (1<<6) |
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| 180 | #define M98088_HPEN ((1<<7)|(1<<6)) |
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| 181 | #define M98088_SPLEN (1<<5) |
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| 182 | #define M98088_SPREN (1<<4) |
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| 183 | #define M98088_RECEN (1<<3) |
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| 184 | #define M98088_DALEN (1<<1) |
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| 185 | #define M98088_DAREN (1<<0) |
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| 186 | |
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| 187 | /* M98088_REG_51_PWR_SYS */ |
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| 188 | #define M98088_SHDNRUN (1<<7) |
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| 189 | #define M98088_PERFMODE (1<<3) |
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| 190 | #define M98088_HPPLYBACK (1<<2) |
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| 191 | #define M98088_PWRSV8K (1<<1) |
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| 192 | #define M98088_PWRSV (1<<0) |
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| 193 | |
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| 194 | /* Line inputs */ |
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| 195 | #define LINE_INA 0 |
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| 196 | #define LINE_INB 1 |
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| 197 | |
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| 198 | #define M98088_COEFS_PER_BAND 5 |
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| 199 | |
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| 200 | #define M98088_BYTE1(w) ((w >> 8) & 0xff) |
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| 201 | #define M98088_BYTE0(w) (w & 0xff) |
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| 202 | |
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| 203 | #endif |
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| 204 | |
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