1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * max98095.h -- MAX98095 ALSA SoC Audio driver |
4 | * |
5 | * Copyright 2011 Maxim Integrated Products |
6 | */ |
7 | |
8 | #ifndef _MAX98095_H |
9 | #define _MAX98095_H |
10 | |
11 | /* |
12 | * MAX98095 Registers Definition |
13 | */ |
14 | |
15 | #define M98095_000_HOST_DATA 0x00 |
16 | #define M98095_001_HOST_INT_STS 0x01 |
17 | #define M98095_002_HOST_RSP_STS 0x02 |
18 | #define M98095_003_HOST_CMD_STS 0x03 |
19 | #define M98095_004_CODEC_STS 0x04 |
20 | #define M98095_005_DAI1_ALC_STS 0x05 |
21 | #define M98095_006_DAI2_ALC_STS 0x06 |
22 | #define M98095_007_JACK_AUTO_STS 0x07 |
23 | #define M98095_008_JACK_MANUAL_STS 0x08 |
24 | #define M98095_009_JACK_VBAT_STS 0x09 |
25 | #define M98095_00A_ACC_ADC_STS 0x0A |
26 | #define M98095_00B_MIC_NG_AGC_STS 0x0B |
27 | #define M98095_00C_SPK_L_VOLT_STS 0x0C |
28 | #define M98095_00D_SPK_R_VOLT_STS 0x0D |
29 | #define M98095_00E_TEMP_SENSOR_STS 0x0E |
30 | #define M98095_00F_HOST_CFG 0x0F |
31 | #define M98095_010_HOST_INT_CFG 0x10 |
32 | #define M98095_011_HOST_INT_EN 0x11 |
33 | #define M98095_012_CODEC_INT_EN 0x12 |
34 | #define M98095_013_JACK_INT_EN 0x13 |
35 | #define M98095_014_JACK_INT_EN 0x14 |
36 | #define M98095_015_DEC 0x15 |
37 | #define M98095_016_RESERVED 0x16 |
38 | #define M98095_017_RESERVED 0x17 |
39 | #define M98095_018_KEYCODE3 0x18 |
40 | #define M98095_019_KEYCODE2 0x19 |
41 | #define M98095_01A_KEYCODE1 0x1A |
42 | #define M98095_01B_KEYCODE0 0x1B |
43 | #define M98095_01C_OEMCODE1 0x1C |
44 | #define M98095_01D_OEMCODE0 0x1D |
45 | #define M98095_01E_XCFG1 0x1E |
46 | #define M98095_01F_XCFG2 0x1F |
47 | #define M98095_020_XCFG3 0x20 |
48 | #define M98095_021_XCFG4 0x21 |
49 | #define M98095_022_XCFG5 0x22 |
50 | #define M98095_023_XCFG6 0x23 |
51 | #define M98095_024_XGPIO 0x24 |
52 | #define M98095_025_XCLKCFG 0x25 |
53 | #define M98095_026_SYS_CLK 0x26 |
54 | #define M98095_027_DAI1_CLKMODE 0x27 |
55 | #define M98095_028_DAI1_CLKCFG_HI 0x28 |
56 | #define M98095_029_DAI1_CLKCFG_LO 0x29 |
57 | #define M98095_02A_DAI1_FORMAT 0x2A |
58 | #define M98095_02B_DAI1_CLOCK 0x2B |
59 | #define M98095_02C_DAI1_IOCFG 0x2C |
60 | #define M98095_02D_DAI1_TDM 0x2D |
61 | #define M98095_02E_DAI1_FILTERS 0x2E |
62 | #define M98095_02F_DAI1_LVL1 0x2F |
63 | #define M98095_030_DAI1_LVL2 0x30 |
64 | #define M98095_031_DAI2_CLKMODE 0x31 |
65 | #define M98095_032_DAI2_CLKCFG_HI 0x32 |
66 | #define M98095_033_DAI2_CLKCFG_LO 0x33 |
67 | #define M98095_034_DAI2_FORMAT 0x34 |
68 | #define M98095_035_DAI2_CLOCK 0x35 |
69 | #define M98095_036_DAI2_IOCFG 0x36 |
70 | #define M98095_037_DAI2_TDM 0x37 |
71 | #define M98095_038_DAI2_FILTERS 0x38 |
72 | #define M98095_039_DAI2_LVL1 0x39 |
73 | #define M98095_03A_DAI2_LVL2 0x3A |
74 | #define M98095_03B_DAI3_CLKMODE 0x3B |
75 | #define M98095_03C_DAI3_CLKCFG_HI 0x3C |
76 | #define M98095_03D_DAI3_CLKCFG_LO 0x3D |
77 | #define M98095_03E_DAI3_FORMAT 0x3E |
78 | #define M98095_03F_DAI3_CLOCK 0x3F |
79 | #define M98095_040_DAI3_IOCFG 0x40 |
80 | #define M98095_041_DAI3_TDM 0x41 |
81 | #define M98095_042_DAI3_FILTERS 0x42 |
82 | #define M98095_043_DAI3_LVL1 0x43 |
83 | #define M98095_044_DAI3_LVL2 0x44 |
84 | #define M98095_045_CFG_DSP 0x45 |
85 | #define M98095_046_DAC_CTRL1 0x46 |
86 | #define M98095_047_DAC_CTRL2 0x47 |
87 | #define M98095_048_MIX_DAC_LR 0x48 |
88 | #define M98095_049_MIX_DAC_M 0x49 |
89 | #define M98095_04A_MIX_ADC_LEFT 0x4A |
90 | #define M98095_04B_MIX_ADC_RIGHT 0x4B |
91 | #define M98095_04C_MIX_HP_LEFT 0x4C |
92 | #define M98095_04D_MIX_HP_RIGHT 0x4D |
93 | #define M98095_04E_CFG_HP 0x4E |
94 | #define M98095_04F_MIX_RCV 0x4F |
95 | #define M98095_050_MIX_SPK_LEFT 0x50 |
96 | #define M98095_051_MIX_SPK_RIGHT 0x51 |
97 | #define M98095_052_MIX_SPK_CFG 0x52 |
98 | #define M98095_053_MIX_LINEOUT1 0x53 |
99 | #define M98095_054_MIX_LINEOUT2 0x54 |
100 | #define M98095_055_MIX_LINEOUT_CFG 0x55 |
101 | #define M98095_056_LVL_SIDETONE_DAI12 0x56 |
102 | #define M98095_057_LVL_SIDETONE_DAI3 0x57 |
103 | #define M98095_058_LVL_DAI1_PLAY 0x58 |
104 | #define M98095_059_LVL_DAI1_EQ 0x59 |
105 | #define M98095_05A_LVL_DAI2_PLAY 0x5A |
106 | #define M98095_05B_LVL_DAI2_EQ 0x5B |
107 | #define M98095_05C_LVL_DAI3_PLAY 0x5C |
108 | #define M98095_05D_LVL_ADC_L 0x5D |
109 | #define M98095_05E_LVL_ADC_R 0x5E |
110 | #define M98095_05F_LVL_MIC1 0x5F |
111 | #define M98095_060_LVL_MIC2 0x60 |
112 | #define M98095_061_LVL_LINEIN 0x61 |
113 | #define M98095_062_LVL_LINEOUT1 0x62 |
114 | #define M98095_063_LVL_LINEOUT2 0x63 |
115 | #define M98095_064_LVL_HP_L 0x64 |
116 | #define M98095_065_LVL_HP_R 0x65 |
117 | #define M98095_066_LVL_RCV 0x66 |
118 | #define M98095_067_LVL_SPK_L 0x67 |
119 | #define M98095_068_LVL_SPK_R 0x68 |
120 | #define M98095_069_MICAGC_CFG 0x69 |
121 | #define M98095_06A_MICAGC_THRESH 0x6A |
122 | #define M98095_06B_SPK_NOISEGATE 0x6B |
123 | #define M98095_06C_DAI1_ALC1_TIME 0x6C |
124 | #define M98095_06D_DAI1_ALC1_COMP 0x6D |
125 | #define M98095_06E_DAI1_ALC1_EXPN 0x6E |
126 | #define M98095_06F_DAI1_ALC1_GAIN 0x6F |
127 | #define M98095_070_DAI1_ALC2_TIME 0x70 |
128 | #define M98095_071_DAI1_ALC2_COMP 0x71 |
129 | #define M98095_072_DAI1_ALC2_EXPN 0x72 |
130 | #define M98095_073_DAI1_ALC2_GAIN 0x73 |
131 | #define M98095_074_DAI1_ALC3_TIME 0x74 |
132 | #define M98095_075_DAI1_ALC3_COMP 0x75 |
133 | #define M98095_076_DAI1_ALC3_EXPN 0x76 |
134 | #define M98095_077_DAI1_ALC3_GAIN 0x77 |
135 | #define M98095_078_DAI2_ALC1_TIME 0x78 |
136 | #define M98095_079_DAI2_ALC1_COMP 0x79 |
137 | #define M98095_07A_DAI2_ALC1_EXPN 0x7A |
138 | #define M98095_07B_DAI2_ALC1_GAIN 0x7B |
139 | #define M98095_07C_DAI2_ALC2_TIME 0x7C |
140 | #define M98095_07D_DAI2_ALC2_COMP 0x7D |
141 | #define M98095_07E_DAI2_ALC2_EXPN 0x7E |
142 | #define M98095_07F_DAI2_ALC2_GAIN 0x7F |
143 | #define M98095_080_DAI2_ALC3_TIME 0x80 |
144 | #define M98095_081_DAI2_ALC3_COMP 0x81 |
145 | #define M98095_082_DAI2_ALC3_EXPN 0x82 |
146 | #define M98095_083_DAI2_ALC3_GAIN 0x83 |
147 | #define M98095_084_HP_NOISE_GATE 0x84 |
148 | #define M98095_085_AUX_ADC 0x85 |
149 | #define M98095_086_CFG_LINE 0x86 |
150 | #define M98095_087_CFG_MIC 0x87 |
151 | #define M98095_088_CFG_LEVEL 0x88 |
152 | #define M98095_089_JACK_DET_AUTO 0x89 |
153 | #define M98095_08A_JACK_DET_MANUAL 0x8A |
154 | #define M98095_08B_JACK_KEYSCAN_DBC 0x8B |
155 | #define M98095_08C_JACK_KEYSCAN_DLY 0x8C |
156 | #define M98095_08D_JACK_KEY_THRESH 0x8D |
157 | #define M98095_08E_JACK_DC_SLEW 0x8E |
158 | #define M98095_08F_JACK_TEST_CFG 0x8F |
159 | #define M98095_090_PWR_EN_IN 0x90 |
160 | #define M98095_091_PWR_EN_OUT 0x91 |
161 | #define M98095_092_PWR_EN_OUT 0x92 |
162 | #define M98095_093_BIAS_CTRL 0x93 |
163 | #define M98095_094_PWR_DAC_21 0x94 |
164 | #define M98095_095_PWR_DAC_03 0x95 |
165 | #define M98095_096_PWR_DAC_CK 0x96 |
166 | #define M98095_097_PWR_SYS 0x97 |
167 | |
168 | #define M98095_0FF_REV_ID 0xFF |
169 | |
170 | #define M98095_REG_CNT (0xFF+1) |
171 | #define M98095_REG_MAX_CACHED 0X97 |
172 | |
173 | /* MAX98095 Registers Bit Fields */ |
174 | |
175 | /* M98095_007_JACK_AUTO_STS */ |
176 | #define M98095_MIC_IN (1<<3) |
177 | #define M98095_LO_IN (1<<5) |
178 | #define M98095_HP_IN (1<<6) |
179 | #define M98095_DDONE (1<<7) |
180 | |
181 | /* M98095_00F_HOST_CFG */ |
182 | #define M98095_SEG (1<<0) |
183 | #define M98095_XTEN (1<<1) |
184 | #define M98095_MDLLEN (1<<2) |
185 | |
186 | /* M98095_013_JACK_INT_EN */ |
187 | #define M98095_IMIC_IN (1<<3) |
188 | #define M98095_ILO_IN (1<<5) |
189 | #define M98095_IHP_IN (1<<6) |
190 | #define M98095_IDDONE (1<<7) |
191 | |
192 | /* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */ |
193 | #define M98095_CLKMODE_MASK 0xFF |
194 | |
195 | /* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */ |
196 | #define M98095_DAI_MAS (1<<7) |
197 | #define M98095_DAI_WCI (1<<6) |
198 | #define M98095_DAI_BCI (1<<5) |
199 | #define M98095_DAI_DLY (1<<4) |
200 | #define M98095_DAI_TDM (1<<2) |
201 | #define M98095_DAI_FSW (1<<1) |
202 | #define M98095_DAI_WS (1<<0) |
203 | |
204 | /* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */ |
205 | #define M98095_DAI_BSEL64 (1<<0) |
206 | #define M98095_DAI_DOSR_DIV2 (0<<5) |
207 | #define M98095_DAI_DOSR_DIV4 (1<<5) |
208 | |
209 | /* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */ |
210 | #define M98095_S1NORMAL (1<<6) |
211 | #define M98095_S2NORMAL (2<<6) |
212 | #define M98095_S3NORMAL (3<<6) |
213 | #define M98095_SDATA (3<<0) |
214 | |
215 | /* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */ |
216 | #define M98095_DAI_DHF (1<<3) |
217 | |
218 | /* M98095_045_DSP_CFG */ |
219 | #define M98095_DSPNORMAL (5<<4) |
220 | |
221 | /* M98095_048_MIX_DAC_LR */ |
222 | #define M98095_DAI1L_TO_DACR (1<<7) |
223 | #define M98095_DAI1R_TO_DACR (1<<6) |
224 | #define M98095_DAI2M_TO_DACR (1<<5) |
225 | #define M98095_DAI1L_TO_DACL (1<<3) |
226 | #define M98095_DAI1R_TO_DACL (1<<2) |
227 | #define M98095_DAI2M_TO_DACL (1<<1) |
228 | #define M98095_DAI3M_TO_DACL (1<<0) |
229 | |
230 | /* M98095_049_MIX_DAC_M */ |
231 | #define M98095_DAI1L_TO_DACM (1<<3) |
232 | #define M98095_DAI1R_TO_DACM (1<<2) |
233 | #define M98095_DAI2M_TO_DACM (1<<1) |
234 | #define M98095_DAI3M_TO_DACM (1<<0) |
235 | |
236 | /* M98095_04E_MIX_HP_CFG */ |
237 | #define M98095_HPNORMAL (3<<4) |
238 | |
239 | /* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */ |
240 | #define M98095_MICPRE_MASK (3<<5) |
241 | #define M98095_MICPRE_SHIFT 5 |
242 | |
243 | /* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */ |
244 | #define M98095_HP_MUTE (1<<7) |
245 | |
246 | /* M98095_066_LVL_RCV */ |
247 | #define M98095_REC_MUTE (1<<7) |
248 | |
249 | /* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */ |
250 | #define M98095_SP_MUTE (1<<7) |
251 | |
252 | /* M98095_087_CFG_MIC */ |
253 | #define M98095_MICSEL_MASK (3<<0) |
254 | #define M98095_DIGMIC_L (1<<2) |
255 | #define M98095_DIGMIC_R (1<<3) |
256 | #define M98095_DIGMIC2L (1<<4) |
257 | #define M98095_DIGMIC2R (1<<5) |
258 | |
259 | /* M98095_088_CFG_LEVEL */ |
260 | #define M98095_VSEN (1<<6) |
261 | #define M98095_ZDEN (1<<5) |
262 | #define M98095_BQ2EN (1<<3) |
263 | #define M98095_BQ1EN (1<<2) |
264 | #define M98095_EQ2EN (1<<1) |
265 | #define M98095_EQ1EN (1<<0) |
266 | |
267 | /* M98095_089_JACK_DET_AUTO */ |
268 | #define M98095_PIN5EN (1<<2) |
269 | #define M98095_JDEN (1<<7) |
270 | |
271 | /* M98095_090_PWR_EN_IN */ |
272 | #define M98095_INEN (1<<7) |
273 | #define M98095_MB2EN (1<<3) |
274 | #define M98095_MB1EN (1<<2) |
275 | #define M98095_MBEN (3<<2) |
276 | #define M98095_ADREN (1<<1) |
277 | #define M98095_ADLEN (1<<0) |
278 | |
279 | /* M98095_091_PWR_EN_OUT */ |
280 | #define M98095_HPLEN (1<<7) |
281 | #define M98095_HPREN (1<<6) |
282 | #define M98095_SPLEN (1<<5) |
283 | #define M98095_SPREN (1<<4) |
284 | #define M98095_RECEN (1<<3) |
285 | #define M98095_DALEN (1<<1) |
286 | #define M98095_DAREN (1<<0) |
287 | |
288 | /* M98095_092_PWR_EN_OUT */ |
289 | #define M98095_SPK_FIXEDSPECTRUM (0<<4) |
290 | #define M98095_SPK_SPREADSPECTRUM (1<<4) |
291 | |
292 | /* M98095_097_PWR_SYS */ |
293 | #define M98095_SHDNRUN (1<<7) |
294 | #define M98095_PERFMODE (1<<3) |
295 | #define M98095_HPPLYBACK (1<<2) |
296 | #define M98095_PWRSV8K (1<<1) |
297 | #define M98095_PWRSV (1<<0) |
298 | |
299 | #define M98095_COEFS_PER_BAND 5 |
300 | |
301 | #define M98095_BYTE1(w) ((w >> 8) & 0xff) |
302 | #define M98095_BYTE0(w) (w & 0xff) |
303 | |
304 | /* Equalizer filter coefficients */ |
305 | #define M98095_110_DAI1_EQ_BASE 0x10 |
306 | #define M98095_142_DAI2_EQ_BASE 0x42 |
307 | |
308 | /* Biquad filter coefficients */ |
309 | #define M98095_174_DAI1_BQ_BASE 0x74 |
310 | #define M98095_17E_DAI2_BQ_BASE 0x7E |
311 | |
312 | /* Default Delay used in Slew Rate Calculation for Jack detection */ |
313 | #define M98095_DEFAULT_SLEW_DELAY 0x18 |
314 | |
315 | extern int max98095_jack_detect(struct snd_soc_component *component, |
316 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack); |
317 | |
318 | #endif |
319 | |