| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * max98925.h -- MAX98925 ALSA SoC Audio driver |
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| 4 | * |
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| 5 | * Copyright 2013-2015 Maxim Integrated Products |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _MAX98925_H |
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| 9 | #define _MAX98925_H |
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| 10 | |
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| 11 | #define MAX98925_VERSION 0x51 |
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| 12 | #define MAX98925_VERSION1 0x80 |
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| 13 | #define MAX98925_VBAT_DATA 0x00 |
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| 14 | #define MAX98925_VBST_DATA 0x01 |
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| 15 | #define MAX98925_LIVE_STATUS0 0x02 |
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| 16 | #define MAX98925_LIVE_STATUS1 0x03 |
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| 17 | #define MAX98925_LIVE_STATUS2 0x04 |
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| 18 | #define MAX98925_STATE0 0x05 |
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| 19 | #define MAX98925_STATE1 0x06 |
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| 20 | #define MAX98925_STATE2 0x07 |
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| 21 | #define MAX98925_FLAG0 0x08 |
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| 22 | #define MAX98925_FLAG1 0x09 |
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| 23 | #define MAX98925_FLAG2 0x0A |
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| 24 | #define MAX98925_IRQ_ENABLE0 0x0B |
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| 25 | #define MAX98925_IRQ_ENABLE1 0x0C |
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| 26 | #define MAX98925_IRQ_ENABLE2 0x0D |
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| 27 | #define MAX98925_IRQ_CLEAR0 0x0E |
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| 28 | #define MAX98925_IRQ_CLEAR1 0x0F |
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| 29 | #define MAX98925_IRQ_CLEAR2 0x10 |
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| 30 | #define MAX98925_MAP0 0x11 |
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| 31 | #define MAX98925_MAP1 0x12 |
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| 32 | #define MAX98925_MAP2 0x13 |
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| 33 | #define MAX98925_MAP3 0x14 |
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| 34 | #define MAX98925_MAP4 0x15 |
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| 35 | #define MAX98925_MAP5 0x16 |
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| 36 | #define MAX98925_MAP6 0x17 |
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| 37 | #define MAX98925_MAP7 0x18 |
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| 38 | #define MAX98925_MAP8 0x19 |
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| 39 | #define MAX98925_DAI_CLK_MODE1 0x1A |
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| 40 | #define MAX98925_DAI_CLK_MODE2 0x1B |
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| 41 | #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C |
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| 42 | #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D |
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| 43 | #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E |
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| 44 | #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F |
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| 45 | #define MAX98925_FORMAT 0x20 |
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| 46 | #define MAX98925_TDM_SLOT_SELECT 0x21 |
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| 47 | #define MAX98925_DOUT_CFG_VMON 0x22 |
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| 48 | #define MAX98925_DOUT_CFG_IMON 0x23 |
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| 49 | #define MAX98925_DOUT_CFG_VBAT 0x24 |
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| 50 | #define MAX98925_DOUT_CFG_VBST 0x25 |
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| 51 | #define MAX98925_DOUT_CFG_FLAG 0x26 |
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| 52 | #define MAX98925_DOUT_HIZ_CFG1 0x27 |
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| 53 | #define MAX98925_DOUT_HIZ_CFG2 0x28 |
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| 54 | #define MAX98925_DOUT_HIZ_CFG3 0x29 |
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| 55 | #define MAX98925_DOUT_HIZ_CFG4 0x2A |
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| 56 | #define MAX98925_DOUT_DRV_STRENGTH 0x2B |
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| 57 | #define MAX98925_FILTERS 0x2C |
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| 58 | #define MAX98925_GAIN 0x2D |
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| 59 | #define MAX98925_GAIN_RAMPING 0x2E |
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| 60 | #define MAX98925_SPK_AMP 0x2F |
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| 61 | #define MAX98925_THRESHOLD 0x30 |
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| 62 | #define MAX98925_ALC_ATTACK 0x31 |
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| 63 | #define MAX98925_ALC_ATTEN_RLS 0x32 |
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| 64 | #define MAX98925_ALC_HOLD_RLS 0x33 |
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| 65 | #define MAX98925_ALC_CONFIGURATION 0x34 |
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| 66 | #define MAX98925_BOOST_CONVERTER 0x35 |
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| 67 | #define MAX98925_BLOCK_ENABLE 0x36 |
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| 68 | #define MAX98925_CONFIGURATION 0x37 |
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| 69 | #define MAX98925_GLOBAL_ENABLE 0x38 |
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| 70 | #define MAX98925_BOOST_LIMITER 0x3A |
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| 71 | #define MAX98925_REV_VERSION 0xFF |
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| 72 | |
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| 73 | #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1) |
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| 74 | |
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| 75 | /* MAX98925 Register Bit Fields */ |
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| 76 | |
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| 77 | /* MAX98925_R002_LIVE_STATUS0 */ |
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| 78 | #define M98925_THERMWARN_STATUS_MASK (1<<3) |
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| 79 | #define M98925_THERMWARN_STATUS_SHIFT 3 |
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| 80 | #define M98925_THERMWARN_STATUS_WIDTH 1 |
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| 81 | #define M98925_THERMSHDN_STATUS_MASK (1<<1) |
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| 82 | #define M98925_THERMSHDN_STATUS_SHIFT 1 |
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| 83 | #define M98925_THERMSHDN_STATUS_WIDTH 1 |
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| 84 | |
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| 85 | /* MAX98925_R003_LIVE_STATUS1 */ |
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| 86 | #define M98925_SPKCURNT_STATUS_MASK (1<<5) |
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| 87 | #define M98925_SPKCURNT_STATUS_SHIFT 5 |
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| 88 | #define M98925_SPKCURNT_STATUS_WIDTH 1 |
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| 89 | #define M98925_WATCHFAIL_STATUS_MASK (1<<4) |
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| 90 | #define M98925_WATCHFAIL_STATUS_SHIFT 4 |
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| 91 | #define M98925_WATCHFAIL_STATUS_WIDTH 1 |
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| 92 | #define M98925_ALCINFH_STATUS_MASK (1<<3) |
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| 93 | #define M98925_ALCINFH_STATUS_SHIFT 3 |
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| 94 | #define M98925_ALCINFH_STATUS_WIDTH 1 |
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| 95 | #define M98925_ALCACT_STATUS_MASK (1<<2) |
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| 96 | #define M98925_ALCACT_STATUS_SHIFT 2 |
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| 97 | #define M98925_ALCACT_STATUS_WIDTH 1 |
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| 98 | #define M98925_ALCMUT_STATUS_MASK (1<<1) |
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| 99 | #define M98925_ALCMUT_STATUS_SHIFT 1 |
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| 100 | #define M98925_ALCMUT_STATUS_WIDTH 1 |
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| 101 | #define M98925_ACLP_STATUS_MASK (1<<0) |
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| 102 | #define M98925_ACLP_STATUS_SHIFT 0 |
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| 103 | #define M98925_ACLP_STATUS_WIDTH 1 |
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| 104 | |
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| 105 | /* MAX98925_R004_LIVE_STATUS2 */ |
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| 106 | #define M98925_SLOTOVRN_STATUS_MASK (1<<6) |
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| 107 | #define M98925_SLOTOVRN_STATUS_SHIFT 6 |
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| 108 | #define M98925_SLOTOVRN_STATUS_WIDTH 1 |
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| 109 | #define M98925_INVALSLOT_STATUS_MASK (1<<5) |
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| 110 | #define M98925_INVALSLOT_STATUS_SHIFT 5 |
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| 111 | #define M98925_INVALSLOT_STATUS_WIDTH 1 |
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| 112 | #define M98925_SLOTCNFLT_STATUS_MASK (1<<4) |
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| 113 | #define M98925_SLOTCNFLT_STATUS_SHIFT 4 |
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| 114 | #define M98925_SLOTCNFLT_STATUS_WIDTH 1 |
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| 115 | #define M98925_VBSTOVFL_STATUS_MASK (1<<3) |
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| 116 | #define M98925_VBSTOVFL_STATUS_SHIFT 3 |
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| 117 | #define M98925_VBSTOVFL_STATUS_WIDTH 1 |
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| 118 | #define M98925_VBATOVFL_STATUS_MASK (1<<2) |
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| 119 | #define M98925_VBATOVFL_STATUS_SHIFT 2 |
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| 120 | #define M98925_VBATOVFL_STATUS_WIDTH 1 |
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| 121 | #define M98925_IMONOVFL_STATUS_MASK (1<<1) |
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| 122 | #define M98925_IMONOVFL_STATUS_SHIFT 1 |
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| 123 | #define M98925_IMONOVFL_STATUS_WIDTH 1 |
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| 124 | #define M98925_VMONOVFL_STATUS_MASK (1<<0) |
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| 125 | #define M98925_VMONOVFL_STATUS_SHIFT 0 |
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| 126 | #define M98925_VMONOVFL_STATUS_WIDTH 1 |
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| 127 | |
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| 128 | /* MAX98925_R005_STATE0 */ |
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| 129 | #define M98925_THERMWARN_END_STATE_MASK (1<<3) |
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| 130 | #define M98925_THERMWARN_END_STATE_SHIFT 3 |
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| 131 | #define M98925_THERMWARN_END_STATE_WIDTH 1 |
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| 132 | #define M98925_THERMWARN_BGN_STATE_MASK (1<<2) |
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| 133 | #define M98925_THERMWARN_BGN_STATE_SHIFT 1 |
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| 134 | #define M98925_THERMWARN_BGN_STATE_WIDTH 1 |
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| 135 | #define M98925_THERMSHDN_END_STATE_MASK (1<<1) |
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| 136 | #define M98925_THERMSHDN_END_STATE_SHIFT 1 |
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| 137 | #define M98925_THERMSHDN_END_STATE_WIDTH 1 |
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| 138 | #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0) |
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| 139 | #define M98925_THERMSHDN_BGN_STATE_SHIFT 0 |
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| 140 | #define M98925_THERMSHDN_BGN_STATE_WIDTH 1 |
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| 141 | |
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| 142 | /* MAX98925_R006_STATE1 */ |
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| 143 | #define M98925_SPRCURNT_STATE_MASK (1<<5) |
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| 144 | #define M98925_SPRCURNT_STATE_SHIFT 5 |
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| 145 | #define M98925_SPRCURNT_STATE_WIDTH 1 |
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| 146 | #define M98925_WATCHFAIL_STATE_MASK (1<<4) |
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| 147 | #define M98925_WATCHFAIL_STATE_SHIFT 4 |
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| 148 | #define M98925_WATCHFAIL_STATE_WIDTH 1 |
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| 149 | #define M98925_ALCINFH_STATE_MASK (1<<3) |
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| 150 | #define M98925_ALCINFH_STATE_SHIFT 3 |
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| 151 | #define M98925_ALCINFH_STATE_WIDTH 1 |
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| 152 | #define M98925_ALCACT_STATE_MASK (1<<2) |
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| 153 | #define M98925_ALCACT_STATE_SHIFT 2 |
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| 154 | #define M98925_ALCACT_STATE_WIDTH 1 |
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| 155 | #define M98925_ALCMUT_STATE_MASK (1<<1) |
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| 156 | #define M98925_ALCMUT_STATE_SHIFT 1 |
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| 157 | #define M98925_ALCMUT_STATE_WIDTH 1 |
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| 158 | #define M98925_ALCP_STATE_MASK (1<<0) |
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| 159 | #define M98925_ALCP_STATE_SHIFT 0 |
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| 160 | #define M98925_ALCP_STATE_WIDTH 1 |
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| 161 | |
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| 162 | /* MAX98925_R007_STATE2 */ |
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| 163 | #define M98925_SLOTOVRN_STATE_MASK (1<<6) |
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| 164 | #define M98925_SLOTOVRN_STATE_SHIFT 6 |
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| 165 | #define M98925_SLOTOVRN_STATE_WIDTH 1 |
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| 166 | #define M98925_INVALSLOT_STATE_MASK (1<<5) |
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| 167 | #define M98925_INVALSLOT_STATE_SHIFT 5 |
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| 168 | #define M98925_INVALSLOT_STATE_WIDTH 1 |
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| 169 | #define M98925_SLOTCNFLT_STATE_MASK (1<<4) |
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| 170 | #define M98925_SLOTCNFLT_STATE_SHIFT 4 |
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| 171 | #define M98925_SLOTCNFLT_STATE_WIDTH 1 |
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| 172 | #define M98925_VBSTOVFL_STATE_MASK (1<<3) |
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| 173 | #define M98925_VBSTOVFL_STATE_SHIFT 3 |
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| 174 | #define M98925_VBSTOVFL_STATE_WIDTH 1 |
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| 175 | #define M98925_VBATOVFL_STATE_MASK (1<<2) |
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| 176 | #define M98925_VBATOVFL_STATE_SHIFT 2 |
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| 177 | #define M98925_VBATOVFL_STATE_WIDTH 1 |
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| 178 | #define M98925_IMONOVFL_STATE_MASK (1<<1) |
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| 179 | #define M98925_IMONOVFL_STATE_SHIFT 1 |
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| 180 | #define M98925_IMONOVFL_STATE_WIDTH 1 |
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| 181 | #define M98925_VMONOVFL_STATE_MASK (1<<0) |
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| 182 | #define M98925_VMONOVFL_STATE_SHIFT 0 |
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| 183 | #define M98925_VMONOVFL_STATE_WIDTH 1 |
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| 184 | |
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| 185 | /* MAX98925_R008_FLAG0 */ |
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| 186 | #define M98925_THERMWARN_END_FLAG_MASK (1<<3) |
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| 187 | #define M98925_THERMWARN_END_FLAG_SHIFT 3 |
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| 188 | #define M98925_THERMWARN_END_FLAG_WIDTH 1 |
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| 189 | #define M98925_THERMWARN_BGN_FLAG_MASK (1<<2) |
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| 190 | #define M98925_THERMWARN_BGN_FLAG_SHIFT 2 |
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| 191 | #define M98925_THERMWARN_BGN_FLAG_WIDTH 1 |
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| 192 | #define M98925_THERMSHDN_END_FLAG_MASK (1<<1) |
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| 193 | #define M98925_THERMSHDN_END_FLAG_SHIFT 1 |
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| 194 | #define M98925_THERMSHDN_END_FLAG_WIDTH 1 |
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| 195 | #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0) |
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| 196 | #define M98925_THERMSHDN_BGN_FLAG_SHIFT 0 |
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| 197 | #define M98925_THERMSHDN_BGN_FLAG_WIDTH 1 |
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| 198 | |
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| 199 | /* MAX98925_R009_FLAG1 */ |
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| 200 | #define M98925_SPKCURNT_FLAG_MASK (1<<5) |
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| 201 | #define M98925_SPKCURNT_FLAG_SHIFT 5 |
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| 202 | #define M98925_SPKCURNT_FLAG_WIDTH 1 |
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| 203 | #define M98925_WATCHFAIL_FLAG_MASK (1<<4) |
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| 204 | #define M98925_WATCHFAIL_FLAG_SHIFT 4 |
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| 205 | #define M98925_WATCHFAIL_FLAG_WIDTH 1 |
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| 206 | #define M98925_ALCINFH_FLAG_MASK (1<<3) |
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| 207 | #define M98925_ALCINFH_FLAG_SHIFT 3 |
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| 208 | #define M98925_ALCINFH_FLAG_WIDTH 1 |
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| 209 | #define M98925_ALCACT_FLAG_MASK (1<<2) |
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| 210 | #define M98925_ALCACT_FLAG_SHIFT 2 |
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| 211 | #define M98925_ALCACT_FLAG_WIDTH 1 |
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| 212 | #define M98925_ALCMUT_FLAG_MASK (1<<1) |
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| 213 | #define M98925_ALCMUT_FLAG_SHIFT 1 |
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| 214 | #define M98925_ALCMUT_FLAG_WIDTH 1 |
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| 215 | #define M98925_ALCP_FLAG_MASK (1<<0) |
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| 216 | #define M98925_ALCP_FLAG_SHIFT 0 |
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| 217 | #define M98925_ALCP_FLAG_WIDTH 1 |
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| 218 | |
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| 219 | /* MAX98925_R00A_FLAG2 */ |
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| 220 | #define M98925_SLOTOVRN_FLAG_MASK (1<<6) |
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| 221 | #define M98925_SLOTOVRN_FLAG_SHIFT 6 |
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| 222 | #define M98925_SLOTOVRN_FLAG_WIDTH 1 |
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| 223 | #define M98925_INVALSLOT_FLAG_MASK (1<<5) |
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| 224 | #define M98925_INVALSLOT_FLAG_SHIFT 5 |
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| 225 | #define M98925_INVALSLOT_FLAG_WIDTH 1 |
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| 226 | #define M98925_SLOTCNFLT_FLAG_MASK (1<<4) |
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| 227 | #define M98925_SLOTCNFLT_FLAG_SHIFT 4 |
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| 228 | #define M98925_SLOTCNFLT_FLAG_WIDTH 1 |
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| 229 | #define M98925_VBSTOVFL_FLAG_MASK (1<<3) |
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| 230 | #define M98925_VBSTOVFL_FLAG_SHIFT 3 |
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| 231 | #define M98925_VBSTOVFL_FLAG_WIDTH 1 |
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| 232 | #define M98925_VBATOVFL_FLAG_MASK (1<<2) |
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| 233 | #define M98925_VBATOVFL_FLAG_SHIFT 2 |
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| 234 | #define M98925_VBATOVFL_FLAG_WIDTH 1 |
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| 235 | #define M98925_IMONOVFL_FLAG_MASK (1<<1) |
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| 236 | #define M98925_IMONOVFL_FLAG_SHIFT 1 |
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| 237 | #define M98925_IMONOVFL_FLAG_WIDTH 1 |
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| 238 | #define M98925_VMONOVFL_FLAG_MASK (1<<0) |
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| 239 | #define M98925_VMONOVFL_FLAG_SHIFT 0 |
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| 240 | #define M98925_VMONOVFL_FLAG_WIDTH 1 |
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| 241 | |
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| 242 | /* MAX98925_R00B_IRQ_ENABLE0 */ |
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| 243 | #define M98925_THERMWARN_END_EN_MASK (1<<3) |
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| 244 | #define M98925_THERMWARN_END_EN_SHIFT 3 |
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| 245 | #define M98925_THERMWARN_END_EN_WIDTH 1 |
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| 246 | #define M98925_THERMWARN_BGN_EN_MASK (1<<2) |
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| 247 | #define M98925_THERMWARN_BGN_EN_SHIFT 2 |
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| 248 | #define M98925_THERMWARN_BGN_EN_WIDTH 1 |
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| 249 | #define M98925_THERMSHDN_END_EN_MASK (1<<1) |
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| 250 | #define M98925_THERMSHDN_END_EN_SHIFT 1 |
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| 251 | #define M98925_THERMSHDN_END_EN_WIDTH 1 |
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| 252 | #define M98925_THERMSHDN_BGN_EN_MASK (1<<0) |
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| 253 | #define M98925_THERMSHDN_BGN_EN_SHIFT 0 |
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| 254 | #define M98925_THERMSHDN_BGN_EN_WIDTH 1 |
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| 255 | |
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| 256 | /* MAX98925_R00C_IRQ_ENABLE1 */ |
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| 257 | #define M98925_SPKCURNT_EN_MASK (1<<5) |
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| 258 | #define M98925_SPKCURNT_EN_SHIFT 5 |
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| 259 | #define M98925_SPKCURNT_EN_WIDTH 1 |
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| 260 | #define M98925_WATCHFAIL_EN_MASK (1<<4) |
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| 261 | #define M98925_WATCHFAIL_EN_SHIFT 4 |
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| 262 | #define M98925_WATCHFAIL_EN_WIDTH 1 |
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| 263 | #define M98925_ALCINFH_EN_MASK (1<<3) |
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| 264 | #define M98925_ALCINFH_EN_SHIFT 3 |
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| 265 | #define M98925_ALCINFH_EN_WIDTH 1 |
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| 266 | #define M98925_ALCACT_EN_MASK (1<<2) |
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| 267 | #define M98925_ALCACT_EN_SHIFT 2 |
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| 268 | #define M98925_ALCACT_EN_WIDTH 1 |
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| 269 | #define M98925_ALCMUT_EN_MASK (1<<1) |
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| 270 | #define M98925_ALCMUT_EN_SHIFT 1 |
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| 271 | #define M98925_ALCMUT_EN_WIDTH 1 |
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| 272 | #define M98925_ALCP_EN_MASK (1<<0) |
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| 273 | #define M98925_ALCP_EN_SHIFT 0 |
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| 274 | #define M98925_ALCP_EN_WIDTH 1 |
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| 275 | |
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| 276 | /* MAX98925_R00D_IRQ_ENABLE2 */ |
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| 277 | #define M98925_SLOTOVRN_EN_MASK (1<<6) |
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| 278 | #define M98925_SLOTOVRN_EN_SHIFT 6 |
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| 279 | #define M98925_SLOTOVRN_EN_WIDTH 1 |
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| 280 | #define M98925_INVALSLOT_EN_MASK (1<<5) |
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| 281 | #define M98925_INVALSLOT_EN_SHIFT 5 |
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| 282 | #define M98925_INVALSLOT_EN_WIDTH 1 |
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| 283 | #define M98925_SLOTCNFLT_EN_MASK (1<<4) |
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| 284 | #define M98925_SLOTCNFLT_EN_SHIFT 4 |
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| 285 | #define M98925_SLOTCNFLT_EN_WIDTH 1 |
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| 286 | #define M98925_VBSTOVFL_EN_MASK (1<<3) |
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| 287 | #define M98925_VBSTOVFL_EN_SHIFT 3 |
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| 288 | #define M98925_VBSTOVFL_EN_WIDTH 1 |
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| 289 | #define M98925_VBATOVFL_EN_MASK (1<<2) |
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| 290 | #define M98925_VBATOVFL_EN_SHIFT 2 |
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| 291 | #define M98925_VBATOVFL_EN_WIDTH 1 |
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| 292 | #define M98925_IMONOVFL_EN_MASK (1<<1) |
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| 293 | #define M98925_IMONOVFL_EN_SHIFT 1 |
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| 294 | #define M98925_IMONOVFL_EN_WIDTH 1 |
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| 295 | #define M98925_VMONOVFL_EN_MASK (1<<0) |
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| 296 | #define M98925_VMONOVFL_EN_SHIFT 0 |
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| 297 | #define M98925_VMONOVFL_EN_WIDTH 1 |
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| 298 | |
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| 299 | /* MAX98925_R00E_IRQ_CLEAR0 */ |
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| 300 | #define M98925_THERMWARN_END_CLR_MASK (1<<3) |
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| 301 | #define M98925_THERMWARN_END_CLR_SHIFT 3 |
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| 302 | #define M98925_THERMWARN_END_CLR_WIDTH 1 |
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| 303 | #define M98925_THERMWARN_BGN_CLR_MASK (1<<2) |
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| 304 | #define M98925_THERMWARN_BGN_CLR_SHIFT 2 |
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| 305 | #define M98925_THERMWARN_BGN_CLR_WIDTH 1 |
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| 306 | #define M98925_THERMSHDN_END_CLR_MASK (1<<1) |
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| 307 | #define M98925_THERMSHDN_END_CLR_SHIFT 1 |
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| 308 | #define M98925_THERMSHDN_END_CLR_WIDTH 1 |
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| 309 | #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0) |
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| 310 | #define M98925_THERMSHDN_BGN_CLR_SHIFT 0 |
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| 311 | #define M98925_THERMSHDN_BGN_CLR_WIDTH 1 |
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| 312 | |
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| 313 | /* MAX98925_R00F_IRQ_CLEAR1 */ |
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| 314 | #define M98925_SPKCURNT_CLR_MASK (1<<5) |
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| 315 | #define M98925_SPKCURNT_CLR_SHIFT 5 |
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| 316 | #define M98925_SPKCURNT_CLR_WIDTH 1 |
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| 317 | #define M98925_WATCHFAIL_CLR_MASK (1<<4) |
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| 318 | #define M98925_WATCHFAIL_CLR_SHIFT 4 |
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| 319 | #define M98925_WATCHFAIL_CLR_WIDTH 1 |
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| 320 | #define M98925_ALCINFH_CLR_MASK (1<<3) |
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| 321 | #define M98925_ALCINFH_CLR_SHIFT 3 |
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| 322 | #define M98925_ALCINFH_CLR_WIDTH 1 |
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| 323 | #define M98925_ALCACT_CLR_MASK (1<<2) |
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| 324 | #define M98925_ALCACT_CLR_SHIFT 2 |
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| 325 | #define M98925_ALCACT_CLR_WIDTH 1 |
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| 326 | #define M98925_ALCMUT_CLR_MASK (1<<1) |
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| 327 | #define M98925_ALCMUT_CLR_SHIFT 1 |
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| 328 | #define M98925_ALCMUT_CLR_WIDTH 1 |
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| 329 | #define M98925_ALCP_CLR_MASK (1<<0) |
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| 330 | #define M98925_ALCP_CLR_SHIFT 0 |
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| 331 | #define M98925_ALCP_CLR_WIDTH 1 |
|---|
| 332 | |
|---|
| 333 | /* MAX98925_R010_IRQ_CLEAR2 */ |
|---|
| 334 | #define M98925_SLOTOVRN_CLR_MASK (1<<6) |
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| 335 | #define M98925_SLOTOVRN_CLR_SHIFT 6 |
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| 336 | #define M98925_SLOTOVRN_CLR_WIDTH 1 |
|---|
| 337 | #define M98925_INVALSLOT_CLR_MASK (1<<5) |
|---|
| 338 | #define M98925_INVALSLOT_CLR_SHIFT 5 |
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| 339 | #define M98925_INVALSLOT_CLR_WIDTH 1 |
|---|
| 340 | #define M98925_SLOTCNFLT_CLR_MASK (1<<4) |
|---|
| 341 | #define M98925_SLOTCNFLT_CLR_SHIFT 4 |
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| 342 | #define M98925_SLOTCNFLT_CLR_WIDTH 1 |
|---|
| 343 | #define M98925_VBSTOVFL_CLR_MASK (1<<3) |
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| 344 | #define M98925_VBSTOVFL_CLR_SHIFT 3 |
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| 345 | #define M98925_VBSTOVFL_CLR_WIDTH 1 |
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| 346 | #define M98925_VBATOVFL_CLR_MASK (1<<2) |
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| 347 | #define M98925_VBATOVFL_CLR_SHIFT 2 |
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| 348 | #define M98925_VBATOVFL_CLR_WIDTH 1 |
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| 349 | #define M98925_IMONOVFL_CLR_MASK (1<<1) |
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| 350 | #define M98925_IMONOVFL_CLR_SHIFT 1 |
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| 351 | #define M98925_IMONOVFL_CLR_WIDTH 1 |
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| 352 | #define M98925_VMONOVFL_CLR_MASK (1<<0) |
|---|
| 353 | #define M98925_VMONOVFL_CLR_SHIFT 0 |
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| 354 | #define M98925_VMONOVFL_CLR_WIDTH 1 |
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| 355 | |
|---|
| 356 | /* MAX98925_R011_MAP0 */ |
|---|
| 357 | #define M98925_ER_THERMWARN_EN_MASK (1<<7) |
|---|
| 358 | #define M98925_ER_THERMWARN_EN_SHIFT 7 |
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| 359 | #define M98925_ER_THERMWARN_EN_WIDTH 1 |
|---|
| 360 | #define M98925_ER_THERMWARN_MAP_MASK (0x07<<4) |
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| 361 | #define M98925_ER_THERMWARN_MAP_SHIFT 4 |
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| 362 | #define M98925_ER_THERMWARN_MAP_WIDTH 3 |
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| 363 | |
|---|
| 364 | /* MAX98925_R012_MAP1 */ |
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| 365 | #define M98925_ER_ALCMUT_EN_MASK (1<<7) |
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| 366 | #define M98925_ER_ALCMUT_EN_SHIFT 7 |
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| 367 | #define M98925_ER_ALCMUT_EN_WIDTH 1 |
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| 368 | #define M98925_ER_ALCMUT_MAP_MASK (0x07<<4) |
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| 369 | #define M98925_ER_ALCMUT_MAP_SHIFT 4 |
|---|
| 370 | #define M98925_ER_ALCMUT_MAP_WIDTH 3 |
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| 371 | #define M98925_ER_ALCP_EN_MASK (1<<3) |
|---|
| 372 | #define M98925_ER_ALCP_EN_SHIFT 3 |
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| 373 | #define M98925_ER_ALCP_EN_WIDTH 1 |
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| 374 | #define M98925_ER_ALCP_MAP_MASK (0x07<<0) |
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| 375 | #define M98925_ER_ALCP_MAP_SHIFT 0 |
|---|
| 376 | #define M98925_ER_ALCP_MAP_WIDTH 3 |
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| 377 | |
|---|
| 378 | /* MAX98925_R013_MAP2 */ |
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| 379 | #define M98925_ER_ALCINFH_EN_MASK (1<<7) |
|---|
| 380 | #define M98925_ER_ALCINFH_EN_SHIFT 7 |
|---|
| 381 | #define M98925_ER_ALCINFH_EN_WIDTH 1 |
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| 382 | #define M98925_ER_ALCINFH_MAP_MASK (0x07<<4) |
|---|
| 383 | #define M98925_ER_ALCINFH_MAP_SHIFT 4 |
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| 384 | #define M98925_ER_ALCINFH_MAP_WIDTH 3 |
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| 385 | #define M98925_ER_ALCACT_EN_MASK (1<<3) |
|---|
| 386 | #define M98925_ER_ALCACT_EN_SHIFT 3 |
|---|
| 387 | #define M98925_ER_ALCACT_EN_WIDTH 1 |
|---|
| 388 | #define M98925_ER_ALCACT_MAP_MASK (0x07<<0) |
|---|
| 389 | #define M98925_ER_ALCACT_MAP_SHIFT 0 |
|---|
| 390 | #define M98925_ER_ALCACT_MAP_WIDTH 3 |
|---|
| 391 | |
|---|
| 392 | /* MAX98925_R014_MAP3 */ |
|---|
| 393 | #define M98925_ER_SPKCURNT_EN_MASK (1<<7) |
|---|
| 394 | #define M98925_ER_SPKCURNT_EN_SHIFT 7 |
|---|
| 395 | #define M98925_ER_SPKCURNT_EN_WIDTH 1 |
|---|
| 396 | #define M98925_ER_SPKCURNT_MAP_MASK (0x07<<4) |
|---|
| 397 | #define M98925_ER_SPKCURNT_MAP_SHIFT 4 |
|---|
| 398 | #define M98925_ER_SPKCURNT_MAP_WIDTH 3 |
|---|
| 399 | |
|---|
| 400 | /* MAX98925_R015_MAP4 */ |
|---|
| 401 | /* RESERVED */ |
|---|
| 402 | |
|---|
| 403 | /* MAX98925_R016_MAP5 */ |
|---|
| 404 | #define M98925_ER_IMONOVFL_EN_MASK (1<<7) |
|---|
| 405 | #define M98925_ER_IMONOVFL_EN_SHIFT 7 |
|---|
| 406 | #define M98925_ER_IMONOVFL_EN_WIDTH 1 |
|---|
| 407 | #define M98925_ER_IMONOVFL_MAP_MASK (0x07<<4) |
|---|
| 408 | #define M98925_ER_IMONOVFL_MAP_SHIFT 4 |
|---|
| 409 | #define M98925_ER_IMONOVFL_MAP_WIDTH 3 |
|---|
| 410 | #define M98925_ER_VMONOVFL_EN_MASK (1<<3) |
|---|
| 411 | #define M98925_ER_VMONOVFL_EN_SHIFT 3 |
|---|
| 412 | #define M98925_ER_VMONOVFL_EN_WIDTH 1 |
|---|
| 413 | #define M98925_ER_VMONOVFL_MAP_MASK (0x07<<0) |
|---|
| 414 | #define M98925_ER_VMONOVFL_MAP_SHIFT 0 |
|---|
| 415 | #define M98925_ER_VMONOVFL_MAP_WIDTH 3 |
|---|
| 416 | |
|---|
| 417 | /* MAX98925_R017_MAP6 */ |
|---|
| 418 | #define M98925_ER_VBSTOVFL_EN_MASK (1<<7) |
|---|
| 419 | #define M98925_ER_VBSTOVFL_EN_SHIFT 7 |
|---|
| 420 | #define M98925_ER_VBSTOVFL_EN_WIDTH 1 |
|---|
| 421 | #define M98925_ER_VBSTOVFL_MAP_MASK (0x07<<4) |
|---|
| 422 | #define M98925_ER_VBSTOVFL_MAP_SHIFT 4 |
|---|
| 423 | #define M98925_ER_VBSTOVFL_MAP_WIDTH 3 |
|---|
| 424 | #define M98925_ER_VBATOVFL_EN_MASK (1<<3) |
|---|
| 425 | #define M98925_ER_VBATOVFL_EN_SHIFT 3 |
|---|
| 426 | #define M98925_ER_VBATOVFL_EN_WIDTH 1 |
|---|
| 427 | #define M98925_ER_VBATOVFL_MAP_MASK (0x07<<0) |
|---|
| 428 | #define M98925_ER_VBATOVFL_MAP_SHIFT 0 |
|---|
| 429 | #define M98925_ER_VBATOVFL_MAP_WIDTH 3 |
|---|
| 430 | |
|---|
| 431 | /* MAX98925_R018_MAP7 */ |
|---|
| 432 | #define M98925_ER_INVALSLOT_EN_MASK (1<<7) |
|---|
| 433 | #define M98925_ER_INVALSLOT_EN_SHIFT 7 |
|---|
| 434 | #define M98925_ER_INVALSLOT_EN_WIDTH 1 |
|---|
| 435 | #define M98925_ER_INVALSLOT_MAP_MASK (0x07<<4) |
|---|
| 436 | #define M98925_ER_INVALSLOT_MAP_SHIFT 4 |
|---|
| 437 | #define M98925_ER_INVALSLOT_MAP_WIDTH 3 |
|---|
| 438 | #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3) |
|---|
| 439 | #define M98925_ER_SLOTCNFLT_EN_SHIFT 3 |
|---|
| 440 | #define M98925_ER_SLOTCNFLT_EN_WIDTH 1 |
|---|
| 441 | #define M98925_ER_SLOTCNFLT_MAP_MASK (0x07<<0) |
|---|
| 442 | #define M98925_ER_SLOTCNFLT_MAP_SHIFT 0 |
|---|
| 443 | #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3 |
|---|
| 444 | |
|---|
| 445 | /* MAX98925_R019_MAP8 */ |
|---|
| 446 | #define M98925_ER_SLOTOVRN_EN_MASK (1<<3) |
|---|
| 447 | #define M98925_ER_SLOTOVRN_EN_SHIFT 3 |
|---|
| 448 | #define M98925_ER_SLOTOVRN_EN_WIDTH 1 |
|---|
| 449 | #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<<0) |
|---|
| 450 | #define M98925_ER_SLOTOVRN_MAP_SHIFT 0 |
|---|
| 451 | #define M98925_ER_SLOTOVRN_MAP_WIDTH 3 |
|---|
| 452 | |
|---|
| 453 | /* MAX98925_R01A_DAI_CLK_MODE1 */ |
|---|
| 454 | #define M98925_DAI_CLK_SOURCE_MASK (1<<6) |
|---|
| 455 | #define M98925_DAI_CLK_SOURCE_SHIFT 6 |
|---|
| 456 | #define M98925_DAI_CLK_SOURCE_WIDTH 1 |
|---|
| 457 | #define M98925_MDLL_MULT_MASK (0x0F<<0) |
|---|
| 458 | #define M98925_MDLL_MULT_SHIFT 0 |
|---|
| 459 | #define M98925_MDLL_MULT_WIDTH 4 |
|---|
| 460 | |
|---|
| 461 | #define M98925_MDLL_MULT_MCLKx8 6 |
|---|
| 462 | #define M98925_MDLL_MULT_MCLKx16 8 |
|---|
| 463 | |
|---|
| 464 | /* MAX98925_R01B_DAI_CLK_MODE2 */ |
|---|
| 465 | #define M98925_DAI_SR_MASK (0x0F<<4) |
|---|
| 466 | #define M98925_DAI_SR_SHIFT 4 |
|---|
| 467 | #define M98925_DAI_SR_WIDTH 4 |
|---|
| 468 | #define M98925_DAI_MAS_MASK (1<<3) |
|---|
| 469 | #define M98925_DAI_MAS_SHIFT 3 |
|---|
| 470 | #define M98925_DAI_MAS_WIDTH 1 |
|---|
| 471 | #define M98925_DAI_BSEL_MASK (0x07<<0) |
|---|
| 472 | #define M98925_DAI_BSEL_SHIFT 0 |
|---|
| 473 | #define M98925_DAI_BSEL_WIDTH 3 |
|---|
| 474 | |
|---|
| 475 | #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT) |
|---|
| 476 | #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT) |
|---|
| 477 | #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BSEL_SHIFT) |
|---|
| 478 | #define M98925_DAI_BSEL_256 (6 << M98925_DAI_BSEL_SHIFT) |
|---|
| 479 | |
|---|
| 480 | /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */ |
|---|
| 481 | #define M98925_DAI_M_MSBS_MASK (0xFF<<0) |
|---|
| 482 | #define M98925_DAI_M_MSBS_SHIFT 0 |
|---|
| 483 | #define M98925_DAI_M_MSBS_WIDTH 8 |
|---|
| 484 | |
|---|
| 485 | /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */ |
|---|
| 486 | #define M98925_DAI_M_LSBS_MASK (0xFF<<0) |
|---|
| 487 | #define M98925_DAI_M_LSBS_SHIFT 0 |
|---|
| 488 | #define M98925_DAI_M_LSBS_WIDTH 8 |
|---|
| 489 | |
|---|
| 490 | /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */ |
|---|
| 491 | #define M98925_DAI_N_MSBS_MASK (0x7F<<0) |
|---|
| 492 | #define M98925_DAI_N_MSBS_SHIFT 0 |
|---|
| 493 | #define M98925_DAI_N_MSBS_WIDTH 7 |
|---|
| 494 | |
|---|
| 495 | /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */ |
|---|
| 496 | #define M98925_DAI_N_LSBS_MASK (0xFF<<0) |
|---|
| 497 | #define M98925_DAI_N_LSBS_SHIFT 0 |
|---|
| 498 | #define M98925_DAI_N_LSBS_WIDTH 8 |
|---|
| 499 | |
|---|
| 500 | /* MAX98925_R020_FORMAT */ |
|---|
| 501 | #define M98925_DAI_CHANSZ_MASK (0x03<<6) |
|---|
| 502 | #define M98925_DAI_CHANSZ_SHIFT 6 |
|---|
| 503 | #define M98925_DAI_CHANSZ_WIDTH 2 |
|---|
| 504 | #define M98925_DAI_EXTBCLK_HIZ_MASK (1<<4) |
|---|
| 505 | #define M98925_DAI_EXTBCLK_HIZ_SHIFT 4 |
|---|
| 506 | #define M98925_DAI_EXTBCLK_HIZ_WIDTH 1 |
|---|
| 507 | #define M98925_DAI_WCI_MASK (1<<3) |
|---|
| 508 | #define M98925_DAI_WCI_SHIFT 3 |
|---|
| 509 | #define M98925_DAI_WCI_WIDTH 1 |
|---|
| 510 | #define M98925_DAI_BCI_MASK (1<<2) |
|---|
| 511 | #define M98925_DAI_BCI_SHIFT 2 |
|---|
| 512 | #define M98925_DAI_BCI_WIDTH 1 |
|---|
| 513 | #define M98925_DAI_DLY_MASK (1<<1) |
|---|
| 514 | #define M98925_DAI_DLY_SHIFT 1 |
|---|
| 515 | #define M98925_DAI_DLY_WIDTH 1 |
|---|
| 516 | #define M98925_DAI_TDM_MASK (1<<0) |
|---|
| 517 | #define M98925_DAI_TDM_SHIFT 0 |
|---|
| 518 | #define M98925_DAI_TDM_WIDTH 1 |
|---|
| 519 | |
|---|
| 520 | #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT) |
|---|
| 521 | #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_CHANSZ_SHIFT) |
|---|
| 522 | #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT) |
|---|
| 523 | |
|---|
| 524 | /* MAX98925_R021_TDM_SLOT_SELECT */ |
|---|
| 525 | #define M98925_DAI_DO_EN_MASK (1<<7) |
|---|
| 526 | #define M98925_DAI_DO_EN_SHIFT 7 |
|---|
| 527 | #define M98925_DAI_DO_EN_WIDTH 1 |
|---|
| 528 | #define M98925_DAI_DIN_EN_MASK (1<<6) |
|---|
| 529 | #define M98925_DAI_DIN_EN_SHIFT 6 |
|---|
| 530 | #define M98925_DAI_DIN_EN_WIDTH 1 |
|---|
| 531 | #define M98925_DAI_INR_SOURCE_MASK (0x07<<3) |
|---|
| 532 | #define M98925_DAI_INR_SOURCE_SHIFT 3 |
|---|
| 533 | #define M98925_DAI_INR_SOURCE_WIDTH 3 |
|---|
| 534 | #define M98925_DAI_INL_SOURCE_MASK (0x07<<0) |
|---|
| 535 | #define M98925_DAI_INL_SOURCE_SHIFT 0 |
|---|
| 536 | #define M98925_DAI_INL_SOURCE_WIDTH 3 |
|---|
| 537 | |
|---|
| 538 | /* MAX98925_R022_DOUT_CFG_VMON */ |
|---|
| 539 | #define M98925_DAI_VMON_EN_MASK (1<<5) |
|---|
| 540 | #define M98925_DAI_VMON_EN_SHIFT 5 |
|---|
| 541 | #define M98925_DAI_VMON_EN_WIDTH 1 |
|---|
| 542 | #define M98925_DAI_VMON_SLOT_MASK (0x1F<<0) |
|---|
| 543 | #define M98925_DAI_VMON_SLOT_SHIFT 0 |
|---|
| 544 | #define M98925_DAI_VMON_SLOT_WIDTH 5 |
|---|
| 545 | |
|---|
| 546 | #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 547 | #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 548 | #define M98925_DAI_VMON_SLOT_02_03 (2 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 549 | #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 550 | #define M98925_DAI_VMON_SLOT_04_05 (4 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 551 | #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 552 | #define M98925_DAI_VMON_SLOT_06_07 (6 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 553 | #define M98925_DAI_VMON_SLOT_07_08 (7 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 554 | #define M98925_DAI_VMON_SLOT_08_09 (8 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 555 | #define M98925_DAI_VMON_SLOT_09_0A (9 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 556 | #define M98925_DAI_VMON_SLOT_0A_0B (10 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 557 | #define M98925_DAI_VMON_SLOT_0B_0C (11 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 558 | #define M98925_DAI_VMON_SLOT_0C_0D (12 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 559 | #define M98925_DAI_VMON_SLOT_0D_0E (13 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 560 | #define M98925_DAI_VMON_SLOT_0E_0F (14 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 561 | #define M98925_DAI_VMON_SLOT_0F_10 (15 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 562 | #define M98925_DAI_VMON_SLOT_10_11 (16 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 563 | #define M98925_DAI_VMON_SLOT_11_12 (17 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 564 | #define M98925_DAI_VMON_SLOT_12_13 (18 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 565 | #define M98925_DAI_VMON_SLOT_13_14 (19 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 566 | #define M98925_DAI_VMON_SLOT_14_15 (20 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 567 | #define M98925_DAI_VMON_SLOT_15_16 (21 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 568 | #define M98925_DAI_VMON_SLOT_16_17 (22 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 569 | #define M98925_DAI_VMON_SLOT_17_18 (23 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 570 | #define M98925_DAI_VMON_SLOT_18_19 (24 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 571 | #define M98925_DAI_VMON_SLOT_19_1A (25 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 572 | #define M98925_DAI_VMON_SLOT_1A_1B (26 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 573 | #define M98925_DAI_VMON_SLOT_1B_1C (27 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 574 | #define M98925_DAI_VMON_SLOT_1C_1D (28 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 575 | #define M98925_DAI_VMON_SLOT_1D_1E (29 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 576 | #define M98925_DAI_VMON_SLOT_1E_1F (30 << M98925_DAI_VMON_SLOT_SHIFT) |
|---|
| 577 | |
|---|
| 578 | /* MAX98925_R023_DOUT_CFG_IMON */ |
|---|
| 579 | #define M98925_DAI_IMON_EN_MASK (1<<5) |
|---|
| 580 | #define M98925_DAI_IMON_EN_SHIFT 5 |
|---|
| 581 | #define M98925_DAI_IMON_EN_WIDTH 1 |
|---|
| 582 | #define M98925_DAI_IMON_SLOT_MASK (0x1F<<0) |
|---|
| 583 | #define M98925_DAI_IMON_SLOT_SHIFT 0 |
|---|
| 584 | #define M98925_DAI_IMON_SLOT_WIDTH 5 |
|---|
| 585 | |
|---|
| 586 | #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 587 | #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 588 | #define M98925_DAI_IMON_SLOT_02_03 (2 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 589 | #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 590 | #define M98925_DAI_IMON_SLOT_04_05 (4 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 591 | #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 592 | #define M98925_DAI_IMON_SLOT_06_07 (6 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 593 | #define M98925_DAI_IMON_SLOT_07_08 (7 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 594 | #define M98925_DAI_IMON_SLOT_08_09 (8 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 595 | #define M98925_DAI_IMON_SLOT_09_0A (9 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 596 | #define M98925_DAI_IMON_SLOT_0A_0B (10 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 597 | #define M98925_DAI_IMON_SLOT_0B_0C (11 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 598 | #define M98925_DAI_IMON_SLOT_0C_0D (12 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 599 | #define M98925_DAI_IMON_SLOT_0D_0E (13 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 600 | #define M98925_DAI_IMON_SLOT_0E_0F (14 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 601 | #define M98925_DAI_IMON_SLOT_0F_10 (15 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 602 | #define M98925_DAI_IMON_SLOT_10_11 (16 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 603 | #define M98925_DAI_IMON_SLOT_11_12 (17 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 604 | #define M98925_DAI_IMON_SLOT_12_13 (18 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 605 | #define M98925_DAI_IMON_SLOT_13_14 (19 << M98925_DAI_IMON_SLOT_SHIFT) |
|---|
| 606 | #define M98925_DAI_IMON_SLOT_14_15 (20 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 607 | #define M98925_DAI_IMON_SLOT_15_16 (21 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 608 | #define M98925_DAI_IMON_SLOT_16_17 (22 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 609 | #define M98925_DAI_IMON_SLOT_17_18 (23 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 610 | #define M98925_DAI_IMON_SLOT_18_19 (24 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 611 | #define M98925_DAI_IMON_SLOT_19_1A (25 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 612 | #define M98925_DAI_IMON_SLOT_1A_1B (26 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 613 | #define M98925_DAI_IMON_SLOT_1B_1C (27 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 614 | #define M98925_DAI_IMON_SLOT_1C_1D (28 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 615 | #define M98925_DAI_IMON_SLOT_1D_1E (29 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 616 | #define M98925_DAI_IMON_SLOT_1E_1F (30 << M98925_DAI_IMON_SLOT_SHIFT) |
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| 617 | |
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| 618 | /* MAX98925_R024_DOUT_CFG_VBAT */ |
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| 619 | #define M98925_DAI_VBAT_EN_MASK (1<<5) |
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| 620 | #define M98925_DAI_VBAT_EN_SHIFT 5 |
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| 621 | #define M98925_DAI_VBAT_EN_WIDTH 1 |
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| 622 | #define M98925_DAI_VBAT_SLOT_MASK (0x1F<<0) |
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| 623 | #define M98925_DAI_VBAT_SLOT_SHIFT 0 |
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| 624 | #define M98925_DAI_VBAT_SLOT_WIDTH 5 |
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| 625 | |
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| 626 | /* MAX98925_R025_DOUT_CFG_VBST */ |
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| 627 | #define M98925_DAI_VBST_EN_MASK (1<<5) |
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| 628 | #define M98925_DAI_VBST_EN_SHIFT 5 |
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| 629 | #define M98925_DAI_VBST_EN_WIDTH 1 |
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| 630 | #define M98925_DAI_VBST_SLOT_MASK (0x1F<<0) |
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| 631 | #define M98925_DAI_VBST_SLOT_SHIFT 0 |
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| 632 | #define M98925_DAI_VBST_SLOT_WIDTH 5 |
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| 633 | |
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| 634 | /* MAX98925_R026_DOUT_CFG_FLAG */ |
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| 635 | #define M98925_DAI_FLAG_EN_MASK (1<<5) |
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| 636 | #define M98925_DAI_FLAG_EN_SHIFT 5 |
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| 637 | #define M98925_DAI_FLAG_EN_WIDTH 1 |
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| 638 | #define M98925_DAI_FLAG_SLOT_MASK (0x1F<<0) |
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| 639 | #define M98925_DAI_FLAG_SLOT_SHIFT 0 |
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| 640 | #define M98925_DAI_FLAG_SLOT_WIDTH 5 |
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| 641 | |
|---|
| 642 | /* MAX98925_R027_DOUT_HIZ_CFG1 */ |
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| 643 | #define M98925_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0) |
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| 644 | #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT 0 |
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| 645 | #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH 8 |
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| 646 | |
|---|
| 647 | /* MAX98925_R028_DOUT_HIZ_CFG2 */ |
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| 648 | #define M98925_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0) |
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| 649 | #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT 0 |
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| 650 | #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH 8 |
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| 651 | |
|---|
| 652 | /* MAX98925_R029_DOUT_HIZ_CFG3 */ |
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| 653 | #define M98925_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0) |
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| 654 | #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT 0 |
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| 655 | #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH 8 |
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| 656 | |
|---|
| 657 | /* MAX98925_R02A_DOUT_HIZ_CFG4 */ |
|---|
| 658 | #define M98925_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0) |
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| 659 | #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT 0 |
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| 660 | #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH 8 |
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| 661 | |
|---|
| 662 | /* MAX98925_R02B_DOUT_DRV_STRENGTH */ |
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| 663 | #define M98925_DAI_OUT_DRIVE_MASK (0x03<<0) |
|---|
| 664 | #define M98925_DAI_OUT_DRIVE_SHIFT 0 |
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| 665 | #define M98925_DAI_OUT_DRIVE_WIDTH 2 |
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| 666 | |
|---|
| 667 | /* MAX98925_R02C_FILTERS */ |
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| 668 | #define M98925_ADC_DITHER_EN_MASK (1<<7) |
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| 669 | #define M98925_ADC_DITHER_EN_SHIFT 7 |
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| 670 | #define M98925_ADC_DITHER_EN_WIDTH 1 |
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| 671 | #define M98925_IV_DCB_EN_MASK (1<<6) |
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| 672 | #define M98925_IV_DCB_EN_SHIFT 6 |
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| 673 | #define M98925_IV_DCB_EN_WIDTH 1 |
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| 674 | #define M98925_DAC_DITHER_EN_MASK (1<<4) |
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| 675 | #define M98925_DAC_DITHER_EN_SHIFT 4 |
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| 676 | #define M98925_DAC_DITHER_EN_WIDTH 1 |
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| 677 | #define M98925_DAC_FILTER_MODE_MASK (1<<3) |
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| 678 | #define M98925_DAC_FILTER_MODE_SHIFT 3 |
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| 679 | #define M98925_DAC_FILTER_MODE_WIDTH 1 |
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| 680 | #define M98925_DAC_HPF_MASK (0x07<<0) |
|---|
| 681 | #define M98925_DAC_HPF_SHIFT 0 |
|---|
| 682 | #define M98925_DAC_HPF_WIDTH 3 |
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| 683 | #define M98925_DAC_HPF_DISABLE (0 << M98925_DAC_HPF_SHIFT) |
|---|
| 684 | #define M98925_DAC_HPF_DC_BLOCK (1 << M98925_DAC_HPF_SHIFT) |
|---|
| 685 | #define M98925_DAC_HPF_EN_100 (2 << M98925_DAC_HPF_SHIFT) |
|---|
| 686 | #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT) |
|---|
| 687 | #define M98925_DAC_HPF_EN_400 (4 << M98925_DAC_HPF_SHIFT) |
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| 688 | #define M98925_DAC_HPF_EN_800 (5 << M98925_DAC_HPF_SHIFT) |
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| 689 | |
|---|
| 690 | /* MAX98925_R02D_GAIN */ |
|---|
| 691 | #define M98925_DAC_IN_SEL_MASK (0x03<<5) |
|---|
| 692 | #define M98925_DAC_IN_SEL_SHIFT 5 |
|---|
| 693 | #define M98925_DAC_IN_SEL_WIDTH 2 |
|---|
| 694 | #define M98925_SPK_GAIN_MASK (0x1F<<0) |
|---|
| 695 | #define M98925_SPK_GAIN_SHIFT 0 |
|---|
| 696 | #define M98925_SPK_GAIN_WIDTH 5 |
|---|
| 697 | |
|---|
| 698 | #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT) |
|---|
| 699 | #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT) |
|---|
| 700 | #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98925_DAC_IN_SEL_SHIFT) |
|---|
| 701 | #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT) |
|---|
| 702 | |
|---|
| 703 | /* MAX98925_R02E_GAIN_RAMPING */ |
|---|
| 704 | #define M98925_SPK_RMP_EN_MASK (1<<1) |
|---|
| 705 | #define M98925_SPK_RMP_EN_SHIFT 1 |
|---|
| 706 | #define M98925_SPK_RMP_EN_WIDTH 1 |
|---|
| 707 | #define M98925_SPK_ZCD_EN_MASK (1<<0) |
|---|
| 708 | #define M98925_SPK_ZCD_EN_SHIFT 0 |
|---|
| 709 | #define M98925_SPK_ZCD_EN_WIDTH 1 |
|---|
| 710 | |
|---|
| 711 | /* MAX98925_R02F_SPK_AMP */ |
|---|
| 712 | #define M98925_SPK_MODE_MASK (1<<0) |
|---|
| 713 | #define M98925_SPK_MODE_SHIFT 0 |
|---|
| 714 | #define M98925_SPK_MODE_WIDTH 1 |
|---|
| 715 | |
|---|
| 716 | /* MAX98925_R030_THRESHOLD */ |
|---|
| 717 | #define M98925_ALC_EN_MASK (1<<5) |
|---|
| 718 | #define M98925_ALC_EN_SHIFT 5 |
|---|
| 719 | #define M98925_ALC_EN_WIDTH 1 |
|---|
| 720 | #define M98925_ALC_TH_MASK (0x1F<<0) |
|---|
| 721 | #define M98925_ALC_TH_SHIFT 0 |
|---|
| 722 | #define M98925_ALC_TH_WIDTH 5 |
|---|
| 723 | |
|---|
| 724 | /* MAX98925_R031_ALC_ATTACK */ |
|---|
| 725 | #define M98925_ALC_ATK_STEP_MASK (0x0F<<4) |
|---|
| 726 | #define M98925_ALC_ATK_STEP_SHIFT 4 |
|---|
| 727 | #define M98925_ALC_ATK_STEP_WIDTH 4 |
|---|
| 728 | #define M98925_ALC_ATK_RATE_MASK (0x7<<0) |
|---|
| 729 | #define M98925_ALC_ATK_RATE_SHIFT 0 |
|---|
| 730 | #define M98925_ALC_ATK_RATE_WIDTH 3 |
|---|
| 731 | |
|---|
| 732 | /* MAX98925_R032_ALC_ATTEN_RLS */ |
|---|
| 733 | #define M98925_ALC_MAX_ATTEN_MASK (0x0F<<4) |
|---|
| 734 | #define M98925_ALC_MAX_ATTEN_SHIFT 4 |
|---|
| 735 | #define M98925_ALC_MAX_ATTEN_WIDTH 4 |
|---|
| 736 | #define M98925_ALC_RLS_RATE_MASK (0x7<<0) |
|---|
| 737 | #define M98925_ALC_RLS_RATE_SHIFT 0 |
|---|
| 738 | #define M98925_ALC_RLS_RATE_WIDTH 3 |
|---|
| 739 | |
|---|
| 740 | /* MAX98925_R033_ALC_HOLD_RLS */ |
|---|
| 741 | #define M98925_ALC_RLS_TGR_MASK (1<<0) |
|---|
| 742 | #define M98925_ALC_RLS_TGR_SHIFT 0 |
|---|
| 743 | #define M98925_ALC_RLS_TGR_WIDTH 1 |
|---|
| 744 | |
|---|
| 745 | /* MAX98925_R034_ALC_CONFIGURATION */ |
|---|
| 746 | #define M98925_ALC_MUTE_EN_MASK (1<<7) |
|---|
| 747 | #define M98925_ALC_MUTE_EN_SHIFT 7 |
|---|
| 748 | #define M98925_ALC_MUTE_EN_WIDTH 1 |
|---|
| 749 | #define M98925_ALC_MUTE_DLY_MASK (0x07<<4) |
|---|
| 750 | #define M98925_ALC_MUTE_DLY_SHIFT 4 |
|---|
| 751 | #define M98925_ALC_MUTE_DLY_WIDTH 3 |
|---|
| 752 | #define M98925_ALC_RLS_DBT_MASK (0x07<<0) |
|---|
| 753 | #define M98925_ALC_RLS_DBT_SHIFT 0 |
|---|
| 754 | #define M98925_ALC_RLS_DBT_WIDTH 3 |
|---|
| 755 | |
|---|
| 756 | /* MAX98925_R035_BOOST_CONVERTER */ |
|---|
| 757 | #define M98925_BST_SYNC_MASK (1<<7) |
|---|
| 758 | #define M98925_BST_SYNC_SHIFT 7 |
|---|
| 759 | #define M98925_BST_SYNC_WIDTH 1 |
|---|
| 760 | #define M98925_BST_PHASE_MASK (0x03<<4) |
|---|
| 761 | #define M98925_BST_PHASE_SHIFT 4 |
|---|
| 762 | #define M98925_BST_PHASE_WIDTH 2 |
|---|
| 763 | #define M98925_BST_SKIP_MODE_MASK (0x03<<0) |
|---|
| 764 | #define M98925_BST_SKIP_MODE_SHIFT 0 |
|---|
| 765 | #define M98925_BST_SKIP_MODE_WIDTH 2 |
|---|
| 766 | |
|---|
| 767 | /* MAX98925_R036_BLOCK_ENABLE */ |
|---|
| 768 | #define M98925_BST_EN_MASK (1<<7) |
|---|
| 769 | #define M98925_BST_EN_SHIFT 7 |
|---|
| 770 | #define M98925_BST_EN_WIDTH 1 |
|---|
| 771 | #define M98925_WATCH_EN_MASK (1<<6) |
|---|
| 772 | #define M98925_WATCH_EN_SHIFT 6 |
|---|
| 773 | #define M98925_WATCH_EN_WIDTH 1 |
|---|
| 774 | #define M98925_CLKMON_EN_MASK (1<<5) |
|---|
| 775 | #define M98925_CLKMON_EN_SHIFT 5 |
|---|
| 776 | #define M98925_CLKMON_EN_WIDTH 1 |
|---|
| 777 | #define M98925_SPK_EN_MASK (1<<4) |
|---|
| 778 | #define M98925_SPK_EN_SHIFT 4 |
|---|
| 779 | #define M98925_SPK_EN_WIDTH 1 |
|---|
| 780 | #define M98925_ADC_VBST_EN_MASK (1<<3) |
|---|
| 781 | #define M98925_ADC_VBST_EN_SHIFT 3 |
|---|
| 782 | #define M98925_ADC_VBST_EN_WIDTH 1 |
|---|
| 783 | #define M98925_ADC_VBAT_EN_MASK (1<<2) |
|---|
| 784 | #define M98925_ADC_VBAT_EN_SHIFT 2 |
|---|
| 785 | #define M98925_ADC_VBAT_EN_WIDTH 1 |
|---|
| 786 | #define M98925_ADC_IMON_EN_MASK (1<<1) |
|---|
| 787 | #define M98925_ADC_IMON_EN_SHIFT 1 |
|---|
| 788 | #define M98925_ADC_IMON_EN_WIDTH 1 |
|---|
| 789 | #define M98925_ADC_VMON_EN_MASK (1<<0) |
|---|
| 790 | #define M98925_ADC_VMON_EN_SHIFT 0 |
|---|
| 791 | #define M98925_ADC_VMON_EN_WIDTH 1 |
|---|
| 792 | |
|---|
| 793 | /* MAX98925_R037_CONFIGURATION */ |
|---|
| 794 | #define M98925_BST_VOUT_MASK (0x0F<<4) |
|---|
| 795 | #define M98925_BST_VOUT_SHIFT 4 |
|---|
| 796 | #define M98925_BST_VOUT_WIDTH 4 |
|---|
| 797 | #define M98925_THERMWARN_LEVEL_MASK (0x03<<2) |
|---|
| 798 | #define M98925_THERMWARN_LEVEL_SHIFT 2 |
|---|
| 799 | #define M98925_THERMWARN_LEVEL_WIDTH 2 |
|---|
| 800 | #define M98925_WATCH_TIME_MASK (0x03<<0) |
|---|
| 801 | #define M98925_WATCH_TIME_SHIFT 0 |
|---|
| 802 | #define M98925_WATCH_TIME_WIDTH 2 |
|---|
| 803 | |
|---|
| 804 | /* MAX98925_R038_GLOBAL_ENABLE */ |
|---|
| 805 | #define M98925_EN_MASK (1<<7) |
|---|
| 806 | #define M98925_EN_SHIFT 7 |
|---|
| 807 | #define M98925_EN_WIDTH 1 |
|---|
| 808 | |
|---|
| 809 | /* MAX98925_R03A_BOOST_LIMITER */ |
|---|
| 810 | #define M98925_BST_ILIM_MASK (0x1F<<3) |
|---|
| 811 | #define M98925_BST_ILIM_SHIFT 3 |
|---|
| 812 | #define M98925_BST_ILIM_WIDTH 5 |
|---|
| 813 | |
|---|
| 814 | /* MAX98925_R0FF_VERSION */ |
|---|
| 815 | #define M98925_REV_ID_MASK (0xFF<<0) |
|---|
| 816 | #define M98925_REV_ID_SHIFT 0 |
|---|
| 817 | #define M98925_REV_ID_WIDTH 8 |
|---|
| 818 | |
|---|
| 819 | struct max98925_priv { |
|---|
| 820 | struct regmap *regmap; |
|---|
| 821 | struct snd_soc_component *component; |
|---|
| 822 | struct max98925_pdata *pdata; |
|---|
| 823 | unsigned int sysclk; |
|---|
| 824 | unsigned int v_slot; |
|---|
| 825 | unsigned int i_slot; |
|---|
| 826 | unsigned int spk_gain; |
|---|
| 827 | unsigned int ch_size; |
|---|
| 828 | }; |
|---|
| 829 | #endif |
|---|
| 830 | |
|---|
