| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * mt6351.h -- mt6351 ALSA SoC audio codec driver |
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| 4 | * |
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| 5 | * Copyright (c) 2018 MediaTek Inc. |
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| 6 | * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __MT6351_H__ |
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| 10 | #define __MT6351_H__ |
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| 11 | |
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| 12 | #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000) |
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| 13 | #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002) |
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| 14 | #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004) |
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| 15 | #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006) |
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| 16 | #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008) |
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| 17 | #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a) |
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| 18 | #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c) |
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| 19 | #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e) |
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| 20 | #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010) |
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| 21 | #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012) |
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| 22 | #define MT6351_AUDIO_TOP_CON0 (0x2000 + 0x0014) |
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| 23 | #define MT6351_AFE_DL_SRC_MON0 (0x2000 + 0x0016) |
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| 24 | #define MT6351_AFE_DL_SDM_TEST0 (0x2000 + 0x0018) |
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| 25 | #define MT6351_AFE_MON_DEBUG0 (0x2000 + 0x001a) |
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| 26 | #define MT6351_AFUNC_AUD_CON0 (0x2000 + 0x001c) |
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| 27 | #define MT6351_AFUNC_AUD_CON1 (0x2000 + 0x001e) |
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| 28 | #define MT6351_AFUNC_AUD_CON2 (0x2000 + 0x0020) |
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| 29 | #define MT6351_AFUNC_AUD_CON3 (0x2000 + 0x0022) |
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| 30 | #define MT6351_AFUNC_AUD_CON4 (0x2000 + 0x0024) |
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| 31 | #define MT6351_AFUNC_AUD_MON0 (0x2000 + 0x0026) |
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| 32 | #define MT6351_AFUNC_AUD_MON1 (0x2000 + 0x0028) |
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| 33 | #define MT6351_AFE_UP8X_FIFO_CFG0 (0x2000 + 0x002c) |
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| 34 | #define MT6351_AFE_UP8X_FIFO_LOG_MON0 (0x2000 + 0x002e) |
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| 35 | #define MT6351_AFE_UP8X_FIFO_LOG_MON1 (0x2000 + 0x0030) |
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| 36 | #define MT6351_AFE_DL_DC_COMP_CFG0 (0x2000 + 0x0032) |
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| 37 | #define MT6351_AFE_DL_DC_COMP_CFG1 (0x2000 + 0x0034) |
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| 38 | #define MT6351_AFE_DL_DC_COMP_CFG2 (0x2000 + 0x0036) |
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| 39 | #define MT6351_AFE_PMIC_NEWIF_CFG0 (0x2000 + 0x0038) |
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| 40 | #define MT6351_AFE_PMIC_NEWIF_CFG1 (0x2000 + 0x003a) |
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| 41 | #define MT6351_AFE_PMIC_NEWIF_CFG2 (0x2000 + 0x003c) |
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| 42 | #define MT6351_AFE_PMIC_NEWIF_CFG3 (0x2000 + 0x003e) |
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| 43 | #define MT6351_AFE_SGEN_CFG0 (0x2000 + 0x0040) |
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| 44 | #define MT6351_AFE_SGEN_CFG1 (0x2000 + 0x0042) |
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| 45 | #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON0 (0x2000 + 0x004c) |
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| 46 | #define MT6351_AFE_ADDA2_UP8X_FIFO_LOG_MON1 (0x2000 + 0x004e) |
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| 47 | #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG0 (0x2000 + 0x0050) |
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| 48 | #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG1 (0x2000 + 0x0052) |
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| 49 | #define MT6351_AFE_ADDA2_PMIC_NEWIF_CFG2 (0x2000 + 0x0054) |
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| 50 | #define MT6351_AFE_DCCLK_CFG0 (0x2000 + 0x0090) |
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| 51 | #define MT6351_AFE_DCCLK_CFG1 (0x2000 + 0x0092) |
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| 52 | #define MT6351_AFE_HPANC_CFG0 (0x2000 + 0x0094) |
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| 53 | #define MT6351_AFE_NCP_CFG0 (0x2000 + 0x0096) |
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| 54 | #define MT6351_AFE_NCP_CFG1 (0x2000 + 0x0098) |
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| 55 | |
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| 56 | #define MT6351_TOP_CKPDN_CON0 0x023A |
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| 57 | #define MT6351_TOP_CKPDN_CON0_SET 0x023C |
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| 58 | #define MT6351_TOP_CKPDN_CON0_CLR 0x023E |
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| 59 | |
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| 60 | #define MT6351_TOP_CLKSQ 0x029A |
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| 61 | #define MT6351_TOP_CLKSQ_SET 0x029C |
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| 62 | #define MT6351_TOP_CLKSQ_CLR 0x029E |
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| 63 | |
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| 64 | #define MT6351_ZCD_CON0 0x0800 |
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| 65 | #define MT6351_ZCD_CON1 0x0802 |
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| 66 | #define MT6351_ZCD_CON2 0x0804 |
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| 67 | #define MT6351_ZCD_CON3 0x0806 |
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| 68 | #define MT6351_ZCD_CON4 0x0808 |
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| 69 | #define MT6351_ZCD_CON5 0x080A |
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| 70 | |
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| 71 | #define MT6351_LDO_VA18_CON0 0x0A00 |
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| 72 | #define MT6351_LDO_VA18_CON1 0x0A02 |
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| 73 | #define MT6351_LDO_VUSB33_CON0 0x0A16 |
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| 74 | #define MT6351_LDO_VUSB33_CON1 0x0A18 |
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| 75 | |
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| 76 | #define MT6351_AUDDEC_ANA_CON0 0x0CF2 |
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| 77 | #define MT6351_AUDDEC_ANA_CON1 0x0CF4 |
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| 78 | #define MT6351_AUDDEC_ANA_CON2 0x0CF6 |
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| 79 | #define MT6351_AUDDEC_ANA_CON3 0x0CF8 |
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| 80 | #define MT6351_AUDDEC_ANA_CON4 0x0CFA |
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| 81 | #define MT6351_AUDDEC_ANA_CON5 0x0CFC |
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| 82 | #define MT6351_AUDDEC_ANA_CON6 0x0CFE |
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| 83 | #define MT6351_AUDDEC_ANA_CON7 0x0D00 |
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| 84 | #define MT6351_AUDDEC_ANA_CON8 0x0D02 |
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| 85 | #define MT6351_AUDDEC_ANA_CON9 0x0D04 |
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| 86 | #define MT6351_AUDDEC_ANA_CON10 0x0D06 |
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| 87 | |
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| 88 | #define MT6351_AUDENC_ANA_CON0 0x0D08 |
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| 89 | #define MT6351_AUDENC_ANA_CON1 0x0D0A |
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| 90 | #define MT6351_AUDENC_ANA_CON2 0x0D0C |
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| 91 | #define MT6351_AUDENC_ANA_CON3 0x0D0E |
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| 92 | #define MT6351_AUDENC_ANA_CON4 0x0D10 |
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| 93 | #define MT6351_AUDENC_ANA_CON5 0x0D12 |
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| 94 | #define MT6351_AUDENC_ANA_CON6 0x0D14 |
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| 95 | #define MT6351_AUDENC_ANA_CON7 0x0D16 |
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| 96 | #define MT6351_AUDENC_ANA_CON8 0x0D18 |
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| 97 | #define MT6351_AUDENC_ANA_CON9 0x0D1A |
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| 98 | #define MT6351_AUDENC_ANA_CON10 0x0D1C |
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| 99 | #define MT6351_AUDENC_ANA_CON11 0x0D1E |
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| 100 | #define MT6351_AUDENC_ANA_CON12 0x0D20 |
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| 101 | #define MT6351_AUDENC_ANA_CON13 0x0D22 |
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| 102 | #define MT6351_AUDENC_ANA_CON14 0x0D24 |
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| 103 | #define MT6351_AUDENC_ANA_CON15 0x0D26 |
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| 104 | #define MT6351_AUDENC_ANA_CON16 0x0D28 |
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| 105 | #endif |
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| 106 | |
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