1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * NAU85L40 ALSA SoC audio driver |
4 | * |
5 | * Copyright 2016 Nuvoton Technology Corp. |
6 | * Author: John Hsu <KCHSU0@nuvoton.com> |
7 | */ |
8 | |
9 | #ifndef __NAU8540_H__ |
10 | #define __NAU8540_H__ |
11 | |
12 | #define NAU8540_REG_SW_RESET 0x00 |
13 | #define NAU8540_REG_POWER_MANAGEMENT 0x01 |
14 | #define NAU8540_REG_CLOCK_CTRL 0x02 |
15 | #define NAU8540_REG_CLOCK_SRC 0x03 |
16 | #define NAU8540_REG_FLL1 0x04 |
17 | #define NAU8540_REG_FLL2 0x05 |
18 | #define NAU8540_REG_FLL3 0x06 |
19 | #define NAU8540_REG_FLL4 0x07 |
20 | #define NAU8540_REG_FLL5 0x08 |
21 | #define NAU8540_REG_FLL6 0x09 |
22 | #define NAU8540_REG_FLL_VCO_RSV 0x0A |
23 | #define NAU8540_REG_PCM_CTRL0 0x10 |
24 | #define NAU8540_REG_PCM_CTRL1 0x11 |
25 | #define NAU8540_REG_PCM_CTRL2 0x12 |
26 | #define NAU8540_REG_PCM_CTRL3 0x13 |
27 | #define NAU8540_REG_PCM_CTRL4 0x14 |
28 | #define NAU8540_REG_ALC_CONTROL_1 0x20 |
29 | #define NAU8540_REG_ALC_CONTROL_2 0x21 |
30 | #define NAU8540_REG_ALC_CONTROL_3 0x22 |
31 | #define NAU8540_REG_ALC_CONTROL_4 0x23 |
32 | #define NAU8540_REG_ALC_CONTROL_5 0x24 |
33 | #define NAU8540_REG_ALC_GAIN_CH12 0x2D |
34 | #define NAU8540_REG_ALC_GAIN_CH34 0x2E |
35 | #define NAU8540_REG_ALC_STATUS 0x2F |
36 | #define NAU8540_REG_NOTCH_FIL1_CH1 0x30 |
37 | #define NAU8540_REG_NOTCH_FIL2_CH1 0x31 |
38 | #define NAU8540_REG_NOTCH_FIL1_CH2 0x32 |
39 | #define NAU8540_REG_NOTCH_FIL2_CH2 0x33 |
40 | #define NAU8540_REG_NOTCH_FIL1_CH3 0x34 |
41 | #define NAU8540_REG_NOTCH_FIL2_CH3 0x35 |
42 | #define NAU8540_REG_NOTCH_FIL1_CH4 0x36 |
43 | #define NAU8540_REG_NOTCH_FIL2_CH4 0x37 |
44 | #define NAU8540_REG_HPF_FILTER_CH12 0x38 |
45 | #define NAU8540_REG_HPF_FILTER_CH34 0x39 |
46 | #define NAU8540_REG_ADC_SAMPLE_RATE 0x3A |
47 | #define NAU8540_REG_DIGITAL_GAIN_CH1 0x40 |
48 | #define NAU8540_REG_DIGITAL_GAIN_CH2 0x41 |
49 | #define NAU8540_REG_DIGITAL_GAIN_CH3 0x42 |
50 | #define NAU8540_REG_DIGITAL_GAIN_CH4 0x43 |
51 | #define NAU8540_REG_DIGITAL_MUX 0x44 |
52 | #define NAU8540_REG_P2P_CH1 0x48 |
53 | #define NAU8540_REG_P2P_CH2 0x49 |
54 | #define NAU8540_REG_P2P_CH3 0x4A |
55 | #define NAU8540_REG_P2P_CH4 0x4B |
56 | #define NAU8540_REG_PEAK_CH1 0x4C |
57 | #define NAU8540_REG_PEAK_CH2 0x4D |
58 | #define NAU8540_REG_PEAK_CH3 0x4E |
59 | #define NAU8540_REG_PEAK_CH4 0x4F |
60 | #define NAU8540_REG_GPIO_CTRL 0x50 |
61 | #define NAU8540_REG_MISC_CTRL 0x51 |
62 | #define NAU8540_REG_I2C_CTRL 0x52 |
63 | #define NAU8540_REG_I2C_DEVICE_ID 0x58 |
64 | #define NAU8540_REG_RST 0x5A |
65 | #define NAU8540_REG_VMID_CTRL 0x60 |
66 | #define NAU8540_REG_MUTE 0x61 |
67 | #define NAU8540_REG_ANALOG_ADC1 0x64 |
68 | #define NAU8540_REG_ANALOG_ADC2 0x65 |
69 | #define NAU8540_REG_ANALOG_PWR 0x66 |
70 | #define NAU8540_REG_MIC_BIAS 0x67 |
71 | #define NAU8540_REG_REFERENCE 0x68 |
72 | #define NAU8540_REG_FEPGA1 0x69 |
73 | #define NAU8540_REG_FEPGA2 0x6A |
74 | #define NAU8540_REG_FEPGA3 0x6B |
75 | #define NAU8540_REG_FEPGA4 0x6C |
76 | #define NAU8540_REG_PWR 0x6D |
77 | #define NAU8540_REG_MAX NAU8540_REG_PWR |
78 | |
79 | |
80 | /* POWER_MANAGEMENT (0x01) */ |
81 | #define NAU8540_ADC_ALL_EN 0xf |
82 | #define NAU8540_ADC4_EN (0x1 << 3) |
83 | #define NAU8540_ADC3_EN (0x1 << 2) |
84 | #define NAU8540_ADC2_EN (0x1 << 1) |
85 | #define NAU8540_ADC1_EN 0x1 |
86 | |
87 | /* CLOCK_CTRL (0x02) */ |
88 | #define NAU8540_CLK_ADC_EN (0x1 << 15) |
89 | #define NAU8540_CLK_AGC_EN (0x1 << 3) |
90 | #define NAU8540_CLK_I2S_EN (0x1 << 1) |
91 | |
92 | /* CLOCK_SRC (0x03) */ |
93 | #define NAU8540_CLK_SRC_SFT 15 |
94 | #define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT) |
95 | #define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT) |
96 | #define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT) |
97 | #define NAU8540_CLK_ADC_SRC_SFT 6 |
98 | #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT) |
99 | #define NAU8540_CLK_MCLK_SRC_MASK 0xf |
100 | |
101 | /* FLL1 (0x04) */ |
102 | #define NAU8540_ICTRL_LATCH_SFT 10 |
103 | #define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT) |
104 | #define NAU8540_FLL_RATIO_MASK 0x7f |
105 | |
106 | /* FLL3 (0x06) */ |
107 | #define NAU8540_GAIN_ERR_SFT 12 |
108 | #define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT) |
109 | #define NAU8540_FLL_CLK_SRC_SFT 10 |
110 | #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) |
111 | #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) |
112 | #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT) |
113 | #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT) |
114 | #define NAU8540_FLL_INTEGER_MASK 0x3ff |
115 | |
116 | /* FLL4 (0x07) */ |
117 | #define NAU8540_FLL_REF_DIV_SFT 10 |
118 | #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT) |
119 | |
120 | /* FLL5 (0x08) */ |
121 | #define NAU8540_FLL_PDB_DAC_EN (0x1 << 15) |
122 | #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14) |
123 | #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13) |
124 | #define NAU8540_FLL_CLK_SW_N2 (0x1 << 13) |
125 | #define NAU8540_FLL_CLK_SW_REF (0x0 << 13) |
126 | #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12) |
127 | #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12) |
128 | #define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12) |
129 | |
130 | /* FLL6 (0x9) */ |
131 | #define NAU8540_DCO_EN (0x1 << 15) |
132 | #define NAU8540_SDM_EN (0x1 << 14) |
133 | #define NAU8540_CUTOFF500 (0x1 << 13) |
134 | |
135 | /* PCM_CTRL0 (0x10) */ |
136 | #define NAU8540_I2S_BP_SFT 7 |
137 | #define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT) |
138 | #define NAU8540_I2S_PCMB_SFT 6 |
139 | #define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT) |
140 | #define NAU8540_I2S_DL_SFT 2 |
141 | #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT) |
142 | #define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT) |
143 | #define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT) |
144 | #define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT) |
145 | #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT) |
146 | #define NAU8540_I2S_DF_MASK 0x3 |
147 | #define NAU8540_I2S_DF_RIGTH 0 |
148 | #define NAU8540_I2S_DF_LEFT 0x1 |
149 | #define NAU8540_I2S_DF_I2S 0x2 |
150 | #define NAU8540_I2S_DF_PCM_AB 0x3 |
151 | |
152 | /* PCM_CTRL1 (0x11) */ |
153 | #define NAU8540_I2S_DO12_TRI (0x1 << 15) |
154 | #define NAU8540_I2S_LRC_DIV_SFT 12 |
155 | #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) |
156 | #define NAU8540_I2S_DO12_OE (0x1 << 4) |
157 | #define NAU8540_I2S_MS_SFT 3 |
158 | #define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT) |
159 | #define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT) |
160 | #define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT) |
161 | #define NAU8540_I2S_BLK_DIV_MASK 0x7 |
162 | |
163 | /* PCM_CTRL1 (0x12) */ |
164 | #define NAU8540_I2S_DO34_TRI (0x1 << 15) |
165 | #define NAU8540_I2S_DO34_OE (0x1 << 11) |
166 | #define NAU8540_I2S_TSLOT_L_MASK 0x3ff |
167 | |
168 | /* PCM_CTRL4 (0x14) */ |
169 | #define NAU8540_TDM_MODE (0x1 << 15) |
170 | #define NAU8540_TDM_OFFSET_EN (0x1 << 14) |
171 | #define NAU8540_TDM_TX_MASK 0xf |
172 | |
173 | /* ALC_CONTROL_3 (0x22) */ |
174 | #define NAU8540_ALC_CH1_EN (0x1 << 12) |
175 | #define NAU8540_ALC_CH2_EN (0x1 << 13) |
176 | #define NAU8540_ALC_CH3_EN (0x1 << 14) |
177 | #define NAU8540_ALC_CH4_EN (0x1 << 15) |
178 | #define NAU8540_ALC_CH_ALL_EN (0xf << 12) |
179 | |
180 | /* ADC_SAMPLE_RATE (0x3A) */ |
181 | #define NAU8540_CH_SYNC (0x1 << 14) |
182 | #define NAU8540_ADC_OSR_MASK 0x3 |
183 | #define NAU8540_ADC_OSR_256 0x3 |
184 | #define NAU8540_ADC_OSR_128 0x2 |
185 | #define NAU8540_ADC_OSR_64 0x1 |
186 | #define NAU8540_ADC_OSR_32 0x0 |
187 | |
188 | /* VMID_CTRL (0x60) */ |
189 | #define NAU8540_VMID_EN (1 << 6) |
190 | #define NAU8540_VMID_SEL_SFT 4 |
191 | #define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT) |
192 | |
193 | /* MUTE (0x61) */ |
194 | #define NAU8540_PGA_CH1_MUTE 0x1 |
195 | #define NAU8540_PGA_CH2_MUTE 0x2 |
196 | #define NAU8540_PGA_CH3_MUTE 0x4 |
197 | #define NAU8540_PGA_CH4_MUTE 0x8 |
198 | #define NAU8540_PGA_CH_ALL_MUTE 0xf |
199 | |
200 | /* MIC_BIAS (0x67) */ |
201 | #define NAU8540_PU_PRE (0x1 << 8) |
202 | |
203 | /* REFERENCE (0x68) */ |
204 | #define NAU8540_PRECHARGE_DIS (0x1 << 13) |
205 | #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) |
206 | #define NAU8540_DISCHRG_EN (0x1 << 11) |
207 | |
208 | /* FEPGA1 (0x69) */ |
209 | #define NAU8540_FEPGA1_MODCH2_SHT_SFT 7 |
210 | #define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT) |
211 | #define NAU8540_FEPGA1_MODCH1_SHT_SFT 3 |
212 | #define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT) |
213 | |
214 | /* FEPGA2 (0x6A) */ |
215 | #define NAU8540_FEPGA2_MODCH4_SHT_SFT 7 |
216 | #define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT) |
217 | #define NAU8540_FEPGA2_MODCH3_SHT_SFT 3 |
218 | #define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT) |
219 | #define NAU8540_ACDC_CTL_SFT 8 |
220 | #define NAU8540_ACDC_CTL_MASK (0xff << NAU8540_ACDC_CTL_SFT) |
221 | #define NAU8540_ACDC_CTL_MIC4N_VREF (0x1 << 15) |
222 | #define NAU8540_ACDC_CTL_MIC4P_VREF (0x1 << 14) |
223 | #define NAU8540_ACDC_CTL_MIC3N_VREF (0x1 << 13) |
224 | #define NAU8540_ACDC_CTL_MIC3P_VREF (0x1 << 12) |
225 | #define NAU8540_ACDC_CTL_MIC2N_VREF (0x1 << 11) |
226 | #define NAU8540_ACDC_CTL_MIC2P_VREF (0x1 << 10) |
227 | #define NAU8540_ACDC_CTL_MIC1N_VREF (0x1 << 9) |
228 | #define NAU8540_ACDC_CTL_MIC1P_VREF (0x1 << 8) |
229 | |
230 | /* System Clock Source */ |
231 | enum { |
232 | NAU8540_CLK_DIS, |
233 | NAU8540_CLK_MCLK, |
234 | NAU8540_CLK_INTERNAL, |
235 | NAU8540_CLK_FLL_MCLK, |
236 | NAU8540_CLK_FLL_BLK, |
237 | NAU8540_CLK_FLL_FS, |
238 | }; |
239 | |
240 | struct nau8540 { |
241 | struct device *dev; |
242 | struct regmap *regmap; |
243 | }; |
244 | |
245 | struct nau8540_fll { |
246 | int mclk_src; |
247 | int ratio; |
248 | int fll_frac; |
249 | int fll_int; |
250 | int clk_ref_div; |
251 | }; |
252 | |
253 | struct nau8540_fll_attr { |
254 | unsigned int param; |
255 | unsigned int val; |
256 | }; |
257 | |
258 | /* over sampling rate */ |
259 | struct nau8540_osr_attr { |
260 | unsigned int osr; |
261 | unsigned int clk_src; |
262 | }; |
263 | |
264 | |
265 | #endif /* __NAU8540_H__ */ |
266 | |