| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * rt1011.h -- RT1011 ALSA SoC amplifier component driver header |
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| 4 | * |
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| 5 | * Copyright(c) 2019 Realtek Semiconductor Corp. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _RT1011_H_ |
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| 9 | #define _RT1011_H_ |
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| 10 | |
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| 11 | #define RT1011_DEVICE_ID_NUM 0x1011 |
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| 12 | |
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| 13 | #define RT1011_RESET 0x0000 |
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| 14 | #define RT1011_CLK_1 0x0002 |
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| 15 | #define RT1011_CLK_2 0x0004 |
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| 16 | #define RT1011_CLK_3 0x0006 |
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| 17 | #define RT1011_CLK_4 0x0008 |
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| 18 | #define RT1011_PLL_1 0x000a |
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| 19 | #define RT1011_PLL_2 0x000c |
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| 20 | #define RT1011_SRC_1 0x000e |
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| 21 | #define RT1011_SRC_2 0x0010 |
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| 22 | #define RT1011_SRC_3 0x0012 |
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| 23 | #define RT1011_CLK_DET 0x0020 |
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| 24 | #define RT1011_SIL_DET 0x0022 |
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| 25 | #define RT1011_PRIV_INDEX 0x006a |
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| 26 | #define RT1011_PRIV_DATA 0x006c |
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| 27 | #define RT1011_CUSTOMER_ID 0x0076 |
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| 28 | #define RT1011_FM_VER 0x0078 |
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| 29 | #define RT1011_VERSION_ID 0x007a |
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| 30 | #define RT1011_VENDOR_ID 0x007c |
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| 31 | #define RT1011_DEVICE_ID 0x007d |
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| 32 | #define RT1011_DUM_RW_0 0x00f0 |
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| 33 | #define RT1011_DUM_YUN 0x00f2 |
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| 34 | #define RT1011_DUM_RW_1 0x00f3 |
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| 35 | #define RT1011_DUM_RO 0x00f4 |
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| 36 | #define RT1011_MAN_I2C_DEV 0x0100 |
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| 37 | #define RT1011_DAC_SET_1 0x0102 |
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| 38 | #define RT1011_DAC_SET_2 0x0104 |
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| 39 | #define RT1011_DAC_SET_3 0x0106 |
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| 40 | #define RT1011_ADC_SET 0x0107 |
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| 41 | #define RT1011_ADC_SET_1 0x0108 |
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| 42 | #define RT1011_ADC_SET_2 0x010a |
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| 43 | #define RT1011_ADC_SET_3 0x010c |
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| 44 | #define RT1011_ADC_SET_4 0x010e |
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| 45 | #define RT1011_ADC_SET_5 0x0110 |
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| 46 | #define RT1011_TDM_TOTAL_SET 0x0111 |
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| 47 | #define RT1011_TDM1_SET_TCON 0x0112 |
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| 48 | #define RT1011_TDM1_SET_1 0x0114 |
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| 49 | #define RT1011_TDM1_SET_2 0x0116 |
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| 50 | #define RT1011_TDM1_SET_3 0x0118 |
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| 51 | #define RT1011_TDM1_SET_4 0x011a |
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| 52 | #define RT1011_TDM1_SET_5 0x011c |
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| 53 | #define RT1011_TDM2_SET_1 0x011e |
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| 54 | #define RT1011_TDM2_SET_2 0x0120 |
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| 55 | #define RT1011_TDM2_SET_3 0x0122 |
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| 56 | #define RT1011_TDM2_SET_4 0x0124 |
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| 57 | #define RT1011_TDM2_SET_5 0x0126 |
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| 58 | #define RT1011_PWM_CAL 0x0200 |
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| 59 | #define RT1011_MIXER_1 0x0300 |
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| 60 | #define RT1011_MIXER_2 0x0302 |
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| 61 | #define RT1011_ADRC_LIMIT 0x0310 |
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| 62 | #define RT1011_A_PRO 0x0311 |
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| 63 | #define RT1011_A_TIMING_1 0x0313 |
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| 64 | #define RT1011_A_TIMING_2 0x0314 |
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| 65 | #define RT1011_A_TEMP_SEN 0x0316 |
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| 66 | #define RT1011_SPK_VOL_DET_1 0x0319 |
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| 67 | #define RT1011_SPK_VOL_DET_2 0x031a |
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| 68 | #define RT1011_SPK_VOL_TEST_OUT 0x031b |
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| 69 | #define RT1011_VBAT_VOL_DET_1 0x031c |
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| 70 | #define RT1011_VBAT_VOL_DET_2 0x031d |
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| 71 | #define RT1011_VBAT_TEST_OUT_1 0x031e |
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| 72 | #define RT1011_VBAT_TEST_OUT_2 0x031f |
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| 73 | #define RT1011_VBAT_PROTECTION 0x0320 |
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| 74 | #define RT1011_VBAT_DET 0x0321 |
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| 75 | #define RT1011_POWER_1 0x0322 |
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| 76 | #define RT1011_POWER_2 0x0324 |
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| 77 | #define RT1011_POWER_3 0x0326 |
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| 78 | #define RT1011_POWER_4 0x0328 |
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| 79 | #define RT1011_POWER_5 0x0329 |
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| 80 | #define RT1011_POWER_6 0x032a |
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| 81 | #define RT1011_POWER_7 0x032b |
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| 82 | #define RT1011_POWER_8 0x032c |
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| 83 | #define RT1011_POWER_9 0x032d |
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| 84 | #define RT1011_CLASS_D_POS 0x032e |
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| 85 | #define RT1011_BOOST_CON_1 0x0330 |
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| 86 | #define RT1011_BOOST_CON_2 0x0332 |
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| 87 | #define RT1011_ANALOG_CTRL 0x0334 |
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| 88 | #define RT1011_POWER_SEQ 0x0340 |
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| 89 | #define RT1011_SHORT_CIRCUIT_DET_1 0x0508 |
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| 90 | #define RT1011_SHORT_CIRCUIT_DET_2 0x050a |
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| 91 | #define RT1011_SPK_TEMP_PROTECT_0 0x050c |
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| 92 | #define RT1011_SPK_TEMP_PROTECT_1 0x050d |
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| 93 | #define RT1011_SPK_TEMP_PROTECT_2 0x050e |
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| 94 | #define RT1011_SPK_TEMP_PROTECT_3 0x050f |
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| 95 | #define RT1011_SPK_TEMP_PROTECT_4 0x0510 |
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| 96 | #define RT1011_SPK_TEMP_PROTECT_5 0x0511 |
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| 97 | #define RT1011_SPK_TEMP_PROTECT_6 0x0512 |
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| 98 | #define RT1011_SPK_TEMP_PROTECT_7 0x0516 |
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| 99 | #define RT1011_SPK_TEMP_PROTECT_8 0x0517 |
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| 100 | #define RT1011_SPK_TEMP_PROTECT_9 0x0518 |
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| 101 | #define RT1011_SPK_PRO_DC_DET_1 0x0519 |
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| 102 | #define RT1011_SPK_PRO_DC_DET_2 0x051a |
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| 103 | #define RT1011_SPK_PRO_DC_DET_3 0x051b |
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| 104 | #define RT1011_SPK_PRO_DC_DET_4 0x051c |
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| 105 | #define RT1011_SPK_PRO_DC_DET_5 0x051d |
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| 106 | #define RT1011_SPK_PRO_DC_DET_6 0x051e |
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| 107 | #define RT1011_SPK_PRO_DC_DET_7 0x051f |
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| 108 | #define RT1011_SPK_PRO_DC_DET_8 0x0520 |
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| 109 | #define RT1011_SPL_1 0x0521 |
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| 110 | #define RT1011_SPL_2 0x0522 |
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| 111 | #define RT1011_SPL_3 0x0524 |
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| 112 | #define RT1011_SPL_4 0x0526 |
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| 113 | #define RT1011_THER_FOLD_BACK_1 0x0528 |
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| 114 | #define RT1011_THER_FOLD_BACK_2 0x052a |
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| 115 | #define RT1011_EXCUR_PROTECT_1 0x0530 |
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| 116 | #define RT1011_EXCUR_PROTECT_2 0x0532 |
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| 117 | #define RT1011_EXCUR_PROTECT_3 0x0534 |
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| 118 | #define RT1011_EXCUR_PROTECT_4 0x0535 |
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| 119 | #define RT1011_BAT_GAIN_1 0x0536 |
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| 120 | #define RT1011_BAT_GAIN_2 0x0538 |
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| 121 | #define RT1011_BAT_GAIN_3 0x053a |
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| 122 | #define RT1011_BAT_GAIN_4 0x053c |
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| 123 | #define RT1011_BAT_GAIN_5 0x053d |
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| 124 | #define RT1011_BAT_GAIN_6 0x053e |
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| 125 | #define RT1011_BAT_GAIN_7 0x053f |
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| 126 | #define RT1011_BAT_GAIN_8 0x0540 |
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| 127 | #define RT1011_BAT_GAIN_9 0x0541 |
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| 128 | #define RT1011_BAT_GAIN_10 0x0542 |
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| 129 | #define RT1011_BAT_GAIN_11 0x0543 |
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| 130 | #define RT1011_BAT_RT_THMAX_1 0x0544 |
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| 131 | #define RT1011_BAT_RT_THMAX_2 0x0545 |
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| 132 | #define RT1011_BAT_RT_THMAX_3 0x0546 |
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| 133 | #define RT1011_BAT_RT_THMAX_4 0x0547 |
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| 134 | #define RT1011_BAT_RT_THMAX_5 0x0548 |
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| 135 | #define RT1011_BAT_RT_THMAX_6 0x0549 |
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| 136 | #define RT1011_BAT_RT_THMAX_7 0x054a |
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| 137 | #define RT1011_BAT_RT_THMAX_8 0x054b |
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| 138 | #define RT1011_BAT_RT_THMAX_9 0x054c |
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| 139 | #define RT1011_BAT_RT_THMAX_10 0x054d |
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| 140 | #define RT1011_BAT_RT_THMAX_11 0x054e |
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| 141 | #define RT1011_BAT_RT_THMAX_12 0x054f |
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| 142 | #define RT1011_SPREAD_SPECTURM 0x0568 |
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| 143 | #define RT1011_PRO_GAIN_MODE 0x056a |
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| 144 | #define RT1011_RT_DRC_CROSS 0x0600 |
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| 145 | #define RT1011_RT_DRC_HB_1 0x0611 |
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| 146 | #define RT1011_RT_DRC_HB_2 0x0612 |
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| 147 | #define RT1011_RT_DRC_HB_3 0x0613 |
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| 148 | #define RT1011_RT_DRC_HB_4 0x0614 |
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| 149 | #define RT1011_RT_DRC_HB_5 0x0615 |
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| 150 | #define RT1011_RT_DRC_HB_6 0x0616 |
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| 151 | #define RT1011_RT_DRC_HB_7 0x0617 |
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| 152 | #define RT1011_RT_DRC_HB_8 0x0618 |
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| 153 | #define RT1011_RT_DRC_BB_1 0x0621 |
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| 154 | #define RT1011_RT_DRC_BB_2 0x0622 |
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| 155 | #define RT1011_RT_DRC_BB_3 0x0623 |
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| 156 | #define RT1011_RT_DRC_BB_4 0x0624 |
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| 157 | #define RT1011_RT_DRC_BB_5 0x0625 |
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| 158 | #define RT1011_RT_DRC_BB_6 0x0626 |
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| 159 | #define RT1011_RT_DRC_BB_7 0x0627 |
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| 160 | #define RT1011_RT_DRC_BB_8 0x0628 |
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| 161 | #define RT1011_RT_DRC_POS_1 0x0631 |
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| 162 | #define RT1011_RT_DRC_POS_2 0x0632 |
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| 163 | #define RT1011_RT_DRC_POS_3 0x0633 |
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| 164 | #define RT1011_RT_DRC_POS_4 0x0634 |
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| 165 | #define RT1011_RT_DRC_POS_5 0x0635 |
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| 166 | #define RT1011_RT_DRC_POS_6 0x0636 |
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| 167 | #define RT1011_RT_DRC_POS_7 0x0637 |
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| 168 | #define RT1011_RT_DRC_POS_8 0x0638 |
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| 169 | #define RT1011_CROSS_BQ_SET_1 0x0702 |
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| 170 | #define RT1011_CROSS_BQ_SET_2 0x0704 |
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| 171 | #define RT1011_BQ_SET_0 0x0706 |
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| 172 | #define RT1011_BQ_SET_1 0x0708 |
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| 173 | #define RT1011_BQ_SET_2 0x070a |
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| 174 | #define RT1011_BQ_PRE_GAIN_28_16 0x0710 |
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| 175 | #define RT1011_BQ_PRE_GAIN_15_0 0x0711 |
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| 176 | #define RT1011_BQ_POST_GAIN_28_16 0x0712 |
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| 177 | #define RT1011_BQ_POST_GAIN_15_0 0x0713 |
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| 178 | |
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| 179 | #define RT1011_BQ_H0_28_16 0x0720 |
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| 180 | #define RT1011_BQ_A2_15_0 0x0729 |
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| 181 | #define RT1011_BQ_1_H0_28_16 0x0730 |
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| 182 | #define RT1011_BQ_1_A2_15_0 0x0739 |
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| 183 | #define RT1011_BQ_2_H0_28_16 0x0740 |
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| 184 | #define RT1011_BQ_2_A2_15_0 0x0749 |
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| 185 | #define RT1011_BQ_3_H0_28_16 0x0750 |
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| 186 | #define RT1011_BQ_3_A2_15_0 0x0759 |
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| 187 | #define RT1011_BQ_4_H0_28_16 0x0760 |
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| 188 | #define RT1011_BQ_4_A2_15_0 0x0769 |
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| 189 | #define RT1011_BQ_5_H0_28_16 0x0770 |
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| 190 | #define RT1011_BQ_5_A2_15_0 0x0779 |
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| 191 | #define RT1011_BQ_6_H0_28_16 0x0780 |
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| 192 | #define RT1011_BQ_6_A2_15_0 0x0789 |
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| 193 | #define RT1011_BQ_7_H0_28_16 0x0790 |
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| 194 | #define RT1011_BQ_7_A2_15_0 0x0799 |
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| 195 | #define RT1011_BQ_8_H0_28_16 0x07a0 |
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| 196 | #define RT1011_BQ_8_A2_15_0 0x07a9 |
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| 197 | #define RT1011_BQ_9_H0_28_16 0x07b0 |
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| 198 | #define RT1011_BQ_9_A2_15_0 0x07b9 |
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| 199 | #define RT1011_BQ_10_H0_28_16 0x07c0 |
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| 200 | #define RT1011_BQ_10_A2_15_0 0x07c9 |
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| 201 | #define RT1011_TEST_PAD_STATUS 0x1000 |
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| 202 | #define RT1011_SYSTEM_RESET_1 0x1007 |
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| 203 | #define RT1011_SYSTEM_RESET_2 0x1008 |
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| 204 | #define RT1011_SYSTEM_RESET_3 0x1009 |
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| 205 | #define RT1011_ADCDAT_OUT_SOURCE 0x100D |
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| 206 | #define RT1011_PLL_INTERNAL_SET 0x1010 |
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| 207 | #define RT1011_TEST_OUT_1 0x1020 |
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| 208 | #define RT1011_TEST_OUT_3 0x1024 |
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| 209 | #define RT1011_DC_CALIB_CLASSD_1 0x1200 |
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| 210 | #define RT1011_DC_CALIB_CLASSD_2 0x1202 |
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| 211 | #define RT1011_DC_CALIB_CLASSD_3 0x1204 |
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| 212 | #define RT1011_DC_CALIB_CLASSD_5 0x1208 |
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| 213 | #define RT1011_DC_CALIB_CLASSD_6 0x120a |
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| 214 | #define RT1011_DC_CALIB_CLASSD_7 0x120c |
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| 215 | #define RT1011_DC_CALIB_CLASSD_8 0x120e |
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| 216 | #define RT1011_DC_CALIB_CLASSD_10 0x1212 |
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| 217 | #define RT1011_CLASSD_INTERNAL_SET_1 0x1300 |
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| 218 | #define RT1011_CLASSD_INTERNAL_SET_3 0x1304 |
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| 219 | #define RT1011_CLASSD_INTERNAL_SET_8 0x130c |
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| 220 | #define RT1011_VREF_LV_1 0x131a |
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| 221 | #define RT1011_SMART_BOOST_TIMING_1 0x1322 |
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| 222 | #define RT1011_SMART_BOOST_TIMING_36 0x1349 |
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| 223 | #define RT1011_SINE_GEN_REG_1 0x1500 |
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| 224 | #define RT1011_SINE_GEN_REG_2 0x1502 |
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| 225 | #define RT1011_SINE_GEN_REG_3 0x1504 |
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| 226 | #define RT1011_STP_INITIAL_RS_TEMP 0x1510 |
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| 227 | #define RT1011_STP_CALIB_RS_TEMP 0x152a |
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| 228 | #define RT1011_INIT_RECIPROCAL_REG_24_16 0x1538 |
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| 229 | #define RT1011_INIT_RECIPROCAL_REG_15_0 0x1539 |
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| 230 | #define RT1011_STP_INITIAL_RESISTANCE_TEMP 0x153c |
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| 231 | #define RT1011_STP_ALPHA_RECIPROCAL_MSB 0x153e |
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| 232 | #define RT1011_SPK_RESISTANCE_1 0x1544 |
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| 233 | #define RT1011_SPK_RESISTANCE_2 0x1546 |
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| 234 | #define RT1011_SPK_THERMAL 0x1548 |
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| 235 | #define RT1011_STP_OTP_TH 0x1552 |
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| 236 | #define RT1011_ALC_BK_GAIN_O 0x1554 |
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| 237 | #define RT1011_ALC_BK_GAIN_O_PRE 0x1556 |
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| 238 | #define RT1011_SPK_DC_O_23_16 0x155a |
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| 239 | #define RT1011_SPK_DC_O_15_0 0x155c |
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| 240 | #define RT1011_INIT_RECIPROCAL_SYN_24_16 0x1560 |
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| 241 | #define RT1011_INIT_RECIPROCAL_SYN_15_0 0x1562 |
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| 242 | #define RT1011_STP_BQ_1_A1_L_28_16 0x1570 |
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| 243 | #define RT1011_STP_BQ_1_H0_R_15_0 0x1583 |
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| 244 | #define RT1011_STP_BQ_2_A1_L_28_16 0x1590 |
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| 245 | #define RT1011_SPK_EXCURSION_23_16 0x15be |
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| 246 | #define RT1011_SPK_EXCURSION_15_0 0x15bf |
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| 247 | #define RT1011_SEP_MAIN_OUT_23_16 0x15c0 |
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| 248 | #define RT1011_SEP_MAIN_OUT_15_0 0x15c1 |
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| 249 | #define RT1011_SEP_RE_REG_15_0 0x15f9 |
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| 250 | #define RT1011_DRC_CF_PARAMS_1 0x1600 |
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| 251 | #define RT1011_DRC_CF_PARAMS_12 0x160b |
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| 252 | #define RT1011_ALC_DRC_HB_INTERNAL_1 0x1611 |
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| 253 | #define RT1011_ALC_DRC_HB_INTERNAL_5 0x1615 |
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| 254 | #define RT1011_ALC_DRC_HB_INTERNAL_6 0x1616 |
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| 255 | #define RT1011_ALC_DRC_HB_INTERNAL_7 0x1617 |
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| 256 | #define RT1011_ALC_DRC_BB_INTERNAL_1 0x1621 |
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| 257 | #define RT1011_ALC_DRC_BB_INTERNAL_5 0x1625 |
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| 258 | #define RT1011_ALC_DRC_BB_INTERNAL_6 0x1626 |
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| 259 | #define RT1011_ALC_DRC_BB_INTERNAL_7 0x1627 |
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| 260 | #define RT1011_ALC_DRC_POS_INTERNAL_1 0x1631 |
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| 261 | #define RT1011_ALC_DRC_POS_INTERNAL_5 0x1635 |
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| 262 | #define RT1011_ALC_DRC_POS_INTERNAL_6 0x1636 |
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| 263 | #define RT1011_ALC_DRC_POS_INTERNAL_7 0x1637 |
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| 264 | #define RT1011_ALC_DRC_POS_INTERNAL_8 0x1638 |
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| 265 | #define RT1011_ALC_DRC_POS_INTERNAL_9 0x163a |
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| 266 | #define RT1011_ALC_DRC_POS_INTERNAL_10 0x163c |
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| 267 | #define RT1011_ALC_DRC_POS_INTERNAL_11 0x163e |
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| 268 | #define RT1011_BQ_1_PARAMS_CHECK_5 0x1648 |
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| 269 | #define RT1011_BQ_2_PARAMS_CHECK_1 0x1650 |
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| 270 | #define RT1011_BQ_2_PARAMS_CHECK_5 0x1658 |
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| 271 | #define RT1011_BQ_3_PARAMS_CHECK_1 0x1660 |
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| 272 | #define RT1011_BQ_3_PARAMS_CHECK_5 0x1668 |
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| 273 | #define RT1011_BQ_4_PARAMS_CHECK_1 0x1670 |
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| 274 | #define RT1011_BQ_4_PARAMS_CHECK_5 0x1678 |
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| 275 | #define RT1011_BQ_5_PARAMS_CHECK_1 0x1680 |
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| 276 | #define RT1011_BQ_5_PARAMS_CHECK_5 0x1688 |
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| 277 | #define RT1011_BQ_6_PARAMS_CHECK_1 0x1690 |
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| 278 | #define RT1011_BQ_6_PARAMS_CHECK_5 0x1698 |
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| 279 | #define RT1011_BQ_7_PARAMS_CHECK_1 0x1700 |
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| 280 | #define RT1011_BQ_7_PARAMS_CHECK_5 0x1708 |
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| 281 | #define RT1011_BQ_8_PARAMS_CHECK_1 0x1710 |
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| 282 | #define RT1011_BQ_8_PARAMS_CHECK_5 0x1718 |
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| 283 | #define RT1011_BQ_9_PARAMS_CHECK_1 0x1720 |
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| 284 | #define RT1011_BQ_9_PARAMS_CHECK_5 0x1728 |
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| 285 | #define RT1011_BQ_10_PARAMS_CHECK_1 0x1730 |
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| 286 | #define RT1011_BQ_10_PARAMS_CHECK_5 0x1738 |
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| 287 | #define RT1011_IRQ_1 0x173a |
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| 288 | #define RT1011_PART_NUMBER_EFUSE 0x173e |
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| 289 | #define RT1011_EFUSE_CONTROL_1 0x17bb |
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| 290 | #define RT1011_EFUSE_CONTROL_2 0x17bd |
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| 291 | #define RT1011_EFUSE_MATCH_DONE 0x17cb |
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| 292 | #define RT1011_EFUSE_ADC_OFFSET_18_16 0x17e5 |
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| 293 | #define RT1011_EFUSE_ADC_OFFSET_15_0 0x17e7 |
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| 294 | #define RT1011_EFUSE_DAC_OFFSET_G0_20_16 0x17e9 |
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| 295 | #define RT1011_EFUSE_DAC_OFFSET_G0_15_0 0x17eb |
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| 296 | #define RT1011_EFUSE_DAC_OFFSET_G1_20_16 0x17ed |
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| 297 | #define RT1011_EFUSE_DAC_OFFSET_G1_15_0 0x17ef |
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| 298 | #define RT1011_EFUSE_READ_R0_3_15_0 0x1803 |
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| 299 | #define RT1011_MAX_REG 0x1803 |
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| 300 | #define RT1011_REG_DISP_LEN 23 |
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| 301 | |
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| 302 | |
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| 303 | /* CLOCK-2 (0x0004) */ |
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| 304 | #define RT1011_FS_SYS_PRE_MASK (0x3 << 14) |
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| 305 | #define RT1011_FS_SYS_PRE_SFT 14 |
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| 306 | #define RT1011_FS_SYS_PRE_MCLK (0x0 << 14) |
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| 307 | #define RT1011_FS_SYS_PRE_BCLK (0x1 << 14) |
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| 308 | #define RT1011_FS_SYS_PRE_PLL1 (0x2 << 14) |
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| 309 | #define RT1011_FS_SYS_PRE_RCCLK (0x3 << 14) |
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| 310 | #define RT1011_PLL1_SRC_MASK (0x1 << 13) |
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| 311 | #define RT1011_PLL1_SRC_SFT 13 |
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| 312 | #define RT1011_PLL1_SRC_PLL2 (0x0 << 13) |
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| 313 | #define RT1011_PLL1_SRC_BCLK (0x1 << 13) |
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| 314 | #define RT1011_PLL2_SRC_MASK (0x1 << 12) |
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| 315 | #define RT1011_PLL2_SRC_SFT 12 |
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| 316 | #define RT1011_PLL2_SRC_MCLK (0x0 << 12) |
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| 317 | #define RT1011_PLL2_SRC_RCCLK (0x1 << 12) |
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| 318 | #define RT1011_PLL2_SRC_DIV_MASK (0x3 << 10) |
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| 319 | #define RT1011_PLL2_SRC_DIV_SFT 10 |
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| 320 | #define RT1011_SRCIN_DIV_MASK (0x3 << 8) |
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| 321 | #define RT1011_SRCIN_DIV_SFT 8 |
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| 322 | #define RT1011_FS_SYS_DIV_MASK (0x7 << 4) |
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| 323 | #define RT1011_FS_SYS_DIV_SFT 4 |
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| 324 | |
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| 325 | /* PLL-1 (0x000a) */ |
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| 326 | #define RT1011_PLL1_QM_MASK (0xf << 12) |
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| 327 | #define RT1011_PLL1_QM_SFT 12 |
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| 328 | #define RT1011_PLL1_BPM_MASK (0x1 << 11) |
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| 329 | #define RT1011_PLL1_BPM_SFT 11 |
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| 330 | #define RT1011_PLL1_BPM (0x1 << 11) |
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| 331 | #define RT1011_PLL1_QN_MASK (0x1ff << 0) |
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| 332 | #define RT1011_PLL1_QN_SFT 0 |
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| 333 | |
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| 334 | /* PLL-2 (0x000c) */ |
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| 335 | #define RT1011_PLL2_BPK_MASK (0x1 << 5) |
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| 336 | #define RT1011_PLL2_BPK_SFT 5 |
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| 337 | #define RT1011_PLL2_BPK (0x1 << 5) |
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| 338 | #define RT1011_PLL2_QK_MASK (0x1f << 0) |
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| 339 | #define RT1011_PLL2_QK_SFT 0 |
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| 340 | |
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| 341 | /* Clock Detect (0x0020) */ |
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| 342 | #define RT1011_EN_MCLK_DET_MASK (0x1 << 15) |
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| 343 | #define RT1011_EN_MCLK_DET_SFT 15 |
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| 344 | #define RT1011_EN_MCLK_DET (0x1 << 15) |
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| 345 | |
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| 346 | /* DAC Setting-2 (0x0104) */ |
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| 347 | #define RT1011_EN_CKGEN_DAC_MASK (0x1 << 13) |
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| 348 | #define RT1011_EN_CKGEN_DAC_SFT 13 |
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| 349 | #define RT1011_EN_CKGEN_DAC (0x1 << 13) |
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| 350 | |
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| 351 | /* DAC Setting-3 (0x0106) */ |
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| 352 | #define RT1011_DA_MUTE_EN_MASK (0x1 << 15) |
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| 353 | #define RT1011_DA_MUTE_EN_SFT 15 |
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| 354 | |
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| 355 | /* ADC Setting-5 (0x0110) */ |
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| 356 | #define RT1011_AD_EN_CKGEN_ADC_MASK (0x1 << 9) |
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| 357 | #define RT1011_AD_EN_CKGEN_ADC_SFT 9 |
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| 358 | #define RT1011_AD_EN_CKGEN_ADC (0x1 << 9) |
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| 359 | |
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| 360 | /* TDM Total Setting (0x0111) */ |
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| 361 | #define RT1011_I2S_TDM_MS_MASK (0x1 << 14) |
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| 362 | #define RT1011_I2S_TDM_MS_SFT 14 |
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| 363 | #define RT1011_I2S_TDM_MS_S (0x0 << 14) |
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| 364 | #define RT1011_I2S_TDM_MS_M (0x1 << 14) |
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| 365 | #define RT1011_I2S_TX_DL_MASK (0x7 << 8) |
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| 366 | #define RT1011_I2S_TX_DL_SFT 8 |
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| 367 | #define RT1011_I2S_TX_DL_16B (0x0 << 8) |
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| 368 | #define RT1011_I2S_TX_DL_20B (0x1 << 8) |
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| 369 | #define RT1011_I2S_TX_DL_24B (0x2 << 8) |
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| 370 | #define RT1011_I2S_TX_DL_32B (0x3 << 8) |
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| 371 | #define RT1011_I2S_TX_DL_8B (0x4 << 8) |
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| 372 | #define RT1011_I2S_RX_DL_MASK (0x7 << 5) |
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| 373 | #define RT1011_I2S_RX_DL_SFT 5 |
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| 374 | #define RT1011_I2S_RX_DL_16B (0x0 << 5) |
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| 375 | #define RT1011_I2S_RX_DL_20B (0x1 << 5) |
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| 376 | #define RT1011_I2S_RX_DL_24B (0x2 << 5) |
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| 377 | #define RT1011_I2S_RX_DL_32B (0x3 << 5) |
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| 378 | #define RT1011_I2S_RX_DL_8B (0x4 << 5) |
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| 379 | #define RT1011_ADCDAT1_PIN_CONFIG (0x1 << 4) |
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| 380 | #define RT1011_ADCDAT1_OUTPUT (0x0 << 4) |
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| 381 | #define RT1011_ADCDAT1_INPUT (0x1 << 4) |
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| 382 | #define RT1011_ADCDAT2_PIN_CONFIG (0x1 << 3) |
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| 383 | #define RT1011_ADCDAT2_OUTPUT (0x0 << 3) |
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| 384 | #define RT1011_ADCDAT2_INPUT (0x1 << 3) |
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| 385 | #define RT1011_I2S_TDM_DF_MASK (0x7 << 0) |
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| 386 | #define RT1011_I2S_TDM_DF_SFT 0 |
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| 387 | #define RT1011_I2S_TDM_DF_I2S (0x0) |
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| 388 | #define RT1011_I2S_TDM_DF_LEFT (0x1) |
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| 389 | #define RT1011_I2S_TDM_DF_PCM_A (0x2) |
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| 390 | #define RT1011_I2S_TDM_DF_PCM_B (0x3) |
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| 391 | #define RT1011_I2S_TDM_DF_PCM_A_N (0x6) |
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| 392 | #define RT1011_I2S_TDM_DF_PCM_B_N (0x7) |
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| 393 | |
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| 394 | /* TDM_tcon Setting (0x0112) */ |
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| 395 | #define RT1011_TCON_DF_MASK (0x7 << 13) |
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| 396 | #define RT1011_TCON_DF_SFT 13 |
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| 397 | #define RT1011_TCON_DF_I2S (0x0 << 13) |
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| 398 | #define RT1011_TCON_DF_LEFT (0x1 << 13) |
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| 399 | #define RT1011_TCON_DF_PCM_A (0x2 << 13) |
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| 400 | #define RT1011_TCON_DF_PCM_B (0x3 << 13) |
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| 401 | #define RT1011_TCON_DF_PCM_A_N (0x6 << 13) |
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| 402 | #define RT1011_TCON_DF_PCM_B_N (0x7 << 13) |
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| 403 | #define RT1011_TCON_BCLK_SEL_MASK (0x3 << 10) |
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| 404 | #define RT1011_TCON_BCLK_SEL_SFT 10 |
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| 405 | #define RT1011_TCON_BCLK_SEL_32FS (0x0 << 10) |
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| 406 | #define RT1011_TCON_BCLK_SEL_64FS (0x1 << 10) |
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| 407 | #define RT1011_TCON_BCLK_SEL_128FS (0x2 << 10) |
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| 408 | #define RT1011_TCON_BCLK_SEL_256FS (0x3 << 10) |
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| 409 | #define RT1011_TCON_CH_LEN_MASK (0x3 << 5) |
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| 410 | #define RT1011_TCON_CH_LEN_SFT 5 |
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| 411 | #define RT1011_TCON_CH_LEN_16B (0x0 << 5) |
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| 412 | #define RT1011_TCON_CH_LEN_20B (0x1 << 5) |
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| 413 | #define RT1011_TCON_CH_LEN_24B (0x2 << 5) |
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| 414 | #define RT1011_TCON_CH_LEN_32B (0x3 << 5) |
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| 415 | #define RT1011_TCON_BCLK_MST_MASK (0x1 << 4) |
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| 416 | #define RT1011_TCON_BCLK_MST_SFT 4 |
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| 417 | #define RT1011_TCON_BCLK_MST_INV (0x1 << 4) |
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| 418 | |
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| 419 | /* TDM1 Setting-1 (0x0114) */ |
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| 420 | #define RT1011_TDM_INV_BCLK_MASK (0x1 << 15) |
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| 421 | #define RT1011_TDM_INV_BCLK_SFT 15 |
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| 422 | #define RT1011_TDM_INV_BCLK (0x1 << 15) |
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| 423 | #define RT1011_I2S_CH_TX_MASK (0x3 << 10) |
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| 424 | #define RT1011_I2S_CH_TX_SFT 10 |
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| 425 | #define RT1011_I2S_TX_2CH (0x0 << 10) |
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| 426 | #define RT1011_I2S_TX_4CH (0x1 << 10) |
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| 427 | #define RT1011_I2S_TX_6CH (0x2 << 10) |
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| 428 | #define RT1011_I2S_TX_8CH (0x3 << 10) |
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| 429 | #define RT1011_I2S_CH_RX_MASK (0x3 << 8) |
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| 430 | #define RT1011_I2S_CH_RX_SFT 8 |
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| 431 | #define RT1011_I2S_RX_2CH (0x0 << 8) |
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| 432 | #define RT1011_I2S_RX_4CH (0x1 << 8) |
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| 433 | #define RT1011_I2S_RX_6CH (0x2 << 8) |
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| 434 | #define RT1011_I2S_RX_8CH (0x3 << 8) |
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| 435 | #define RT1011_I2S_LR_CH_SEL_MASK (0x1 << 7) |
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| 436 | #define RT1011_I2S_LR_CH_SEL_SFT 7 |
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| 437 | #define RT1011_I2S_LEFT_CH_SEL (0x0 << 7) |
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| 438 | #define RT1011_I2S_RIGHT_CH_SEL (0x1 << 7) |
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| 439 | #define RT1011_I2S_CH_TX_LEN_MASK (0x7 << 4) |
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| 440 | #define RT1011_I2S_CH_TX_LEN_SFT 4 |
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| 441 | #define RT1011_I2S_CH_TX_LEN_16B (0x0 << 4) |
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| 442 | #define RT1011_I2S_CH_TX_LEN_20B (0x1 << 4) |
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| 443 | #define RT1011_I2S_CH_TX_LEN_24B (0x2 << 4) |
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| 444 | #define RT1011_I2S_CH_TX_LEN_32B (0x3 << 4) |
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| 445 | #define RT1011_I2S_CH_TX_LEN_8B (0x4 << 4) |
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| 446 | #define RT1011_I2S_CH_RX_LEN_MASK (0x7 << 0) |
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| 447 | #define RT1011_I2S_CH_RX_LEN_SFT 0 |
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| 448 | #define RT1011_I2S_CH_RX_LEN_16B (0x0 << 0) |
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| 449 | #define RT1011_I2S_CH_RX_LEN_20B (0x1 << 0) |
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| 450 | #define RT1011_I2S_CH_RX_LEN_24B (0x2 << 0) |
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| 451 | #define RT1011_I2S_CH_RX_LEN_32B (0x3 << 0) |
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| 452 | #define RT1011_I2S_CH_RX_LEN_8B (0x4 << 0) |
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| 453 | |
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| 454 | /* TDM1 Setting-2 (0x0116) */ |
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| 455 | #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK (0x7 << 13) |
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| 456 | #define RT1011_TDM_I2S_DOCK_ADCDAT_2CH (0x1 << 13) |
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| 457 | #define RT1011_TDM_I2S_DOCK_ADCDAT_4CH (0x3 << 13) |
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| 458 | #define RT1011_TDM_I2S_DOCK_ADCDAT_6CH (0x5 << 13) |
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| 459 | #define RT1011_TDM_I2S_DOCK_ADCDAT_8CH (0x7 << 13) |
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| 460 | #define RT1011_TDM_I2S_DOCK_EN_1_MASK (0x1 << 3) |
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| 461 | #define RT1011_TDM_I2S_DOCK_EN_1_SFT 3 |
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| 462 | #define RT1011_TDM_I2S_DOCK_EN_1 (0x1 << 3) |
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| 463 | #define RT1011_TDM_ADCDAT1_DATA_LOCATION (0x7 << 0) |
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| 464 | |
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| 465 | /* TDM1 Setting-3 (0x0118) */ |
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| 466 | #define RT1011_TDM_I2S_RX_ADC1_1_MASK (0x3 << 6) |
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| 467 | #define RT1011_TDM_I2S_RX_ADC2_1_MASK (0x3 << 4) |
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| 468 | #define RT1011_TDM_I2S_RX_ADC3_1_MASK (0x3 << 2) |
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| 469 | #define RT1011_TDM_I2S_RX_ADC4_1_MASK (0x3 << 0) |
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| 470 | #define RT1011_TDM_I2S_RX_ADC1_1_LL (0x2 << 6) |
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| 471 | #define RT1011_TDM_I2S_RX_ADC2_1_LL (0x2 << 4) |
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| 472 | #define RT1011_TDM_I2S_RX_ADC3_1_LL (0x2 << 2) |
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| 473 | #define RT1011_TDM_I2S_RX_ADC4_1_LL (0x2 << 0) |
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| 474 | |
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| 475 | /* TDM1 Setting-4 (0x011a) */ |
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| 476 | #define RT1011_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12) |
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| 477 | #define RT1011_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8) |
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| 478 | #define RT1011_TDM_I2S_TX_L_DAC1_1_SFT 12 |
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| 479 | #define RT1011_TDM_I2S_TX_R_DAC1_1_SFT 8 |
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| 480 | |
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| 481 | /* TDM2 Setting-2 (0x0120) */ |
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| 482 | #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_2_MASK (0x7 << 13) |
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| 483 | #define RT1011_TDM_I2S_DOCK_EN_2_MASK (0x1 << 3) |
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| 484 | #define RT1011_TDM_I2S_DOCK_EN_2_SFT 3 |
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| 485 | #define RT1011_TDM_I2S_DOCK_EN_2 (0x1 << 3) |
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| 486 | |
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| 487 | /* MIXER 1 (0x0300) */ |
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| 488 | #define RT1011_MIXER_MUTE_MIX_I_MASK (0x1 << 15) |
|---|
| 489 | #define RT1011_MIXER_MUTE_MIX_I_SFT 15 |
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| 490 | #define RT1011_MIXER_MUTE_MIX_I (0x1 << 15) |
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| 491 | #define RT1011_MIXER_MUTE_SUM_I_MASK (0x1 << 14) |
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| 492 | #define RT1011_MIXER_MUTE_SUM_I_SFT 14 |
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| 493 | #define RT1011_MIXER_MUTE_SUM_I (0x1 << 14) |
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| 494 | #define RT1011_MIXER_MUTE_MIX_V_MASK (0x1 << 7) |
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| 495 | #define RT1011_MIXER_MUTE_MIX_V_SFT 7 |
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| 496 | #define RT1011_MIXER_MUTE_MIX_V (0x1 << 7) |
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| 497 | #define RT1011_MIXER_MUTE_SUM_V_MASK (0x1 << 6) |
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| 498 | #define RT1011_MIXER_MUTE_SUM_V_SFT 6 |
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| 499 | #define RT1011_MIXER_MUTE_SUM_V (0x1 << 6) |
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| 500 | |
|---|
| 501 | /* Analog Temperature Sensor (0x0316) */ |
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| 502 | #define RT1011_POW_TEMP_REG (0x1 << 2) |
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| 503 | #define RT1011_POW_TEMP_REG_BIT 2 |
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| 504 | |
|---|
| 505 | /* POWER-1 (0x0322) */ |
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| 506 | #define RT1011_POW_LDO2 (0x1 << 15) |
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| 507 | #define RT1011_POW_LDO2_BIT 15 |
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| 508 | #define RT1011_POW_DAC (0x1 << 14) |
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| 509 | #define RT1011_POW_DAC_BIT 14 |
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| 510 | #define RT1011_POW_CLK12M (0x1 << 13) |
|---|
| 511 | #define RT1011_POW_CLK12M_BIT 13 |
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| 512 | #define RT1011_POW_TEMP (0x1 << 12) |
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| 513 | #define RT1011_POW_TEMP_BIT 12 |
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| 514 | #define RT1011_POW_ISENSE_SPK (0x1 << 7) |
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| 515 | #define RT1011_POW_ISENSE_SPK_BIT 7 |
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| 516 | #define RT1011_POW_LPF_SPK (0x1 << 6) |
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| 517 | #define RT1011_POW_LPF_SPK_BIT 6 |
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| 518 | #define RT1011_POW_VSENSE_SPK (0x1 << 5) |
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| 519 | #define RT1011_POW_VSENSE_SPK_BIT 5 |
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| 520 | #define RT1011_POW_TWO_BATTERY_SPK (0x1 << 4) |
|---|
| 521 | #define RT1011_POW_TWO_BATTERY_SPK_BIT 4 |
|---|
| 522 | |
|---|
| 523 | /* POWER-2 (0x0324) */ |
|---|
| 524 | #define RT1011_PLLEN (0x1 << 2) |
|---|
| 525 | #define RT1011_PLLEN_BIT 2 |
|---|
| 526 | #define RT1011_POW_BG (0x1 << 1) |
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| 527 | #define RT1011_POW_BG_BIT 1 |
|---|
| 528 | #define RT1011_POW_BG_MBIAS_LV (0x1 << 0) |
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| 529 | #define RT1011_POW_BG_MBIAS_LV_BIT 0 |
|---|
| 530 | |
|---|
| 531 | /* POWER-3 (0x0326) */ |
|---|
| 532 | #define RT1011_POW_DET_SPKVDD (0x1 << 15) |
|---|
| 533 | #define RT1011_POW_DET_SPKVDD_BIT 15 |
|---|
| 534 | #define RT1011_POW_DET_VBAT (0x1 << 14) |
|---|
| 535 | #define RT1011_POW_DET_VBAT_BIT 14 |
|---|
| 536 | #define RT1011_POW_FC (0x1 << 13) |
|---|
| 537 | #define RT1011_POW_FC_BIT 13 |
|---|
| 538 | #define RT1011_POW_MBIAS_LV (0x1 << 12) |
|---|
| 539 | #define RT1011_POW_MBIAS_LV_BIT 12 |
|---|
| 540 | #define RT1011_POW_ADC_I (0x1 << 11) |
|---|
| 541 | #define RT1011_POW_ADC_I_BIT 11 |
|---|
| 542 | #define RT1011_POW_ADC_V (0x1 << 10) |
|---|
| 543 | #define RT1011_POW_ADC_V_BIT 10 |
|---|
| 544 | #define RT1011_POW_ADC_T (0x1 << 9) |
|---|
| 545 | #define RT1011_POW_ADC_T_BIT 9 |
|---|
| 546 | #define RT1011_POWD_ADC_T (0x1 << 8) |
|---|
| 547 | #define RT1011_POWD_ADC_T_BIT 8 |
|---|
| 548 | #define RT1011_POW_MIX_I (0x1 << 7) |
|---|
| 549 | #define RT1011_POW_MIX_I_BIT 7 |
|---|
| 550 | #define RT1011_POW_MIX_V (0x1 << 6) |
|---|
| 551 | #define RT1011_POW_MIX_V_BIT 6 |
|---|
| 552 | #define RT1011_POW_SUM_I (0x1 << 5) |
|---|
| 553 | #define RT1011_POW_SUM_I_BIT 5 |
|---|
| 554 | #define RT1011_POW_SUM_V (0x1 << 4) |
|---|
| 555 | #define RT1011_POW_SUM_V_BIT 4 |
|---|
| 556 | #define RT1011_POW_MIX_T (0x1 << 2) |
|---|
| 557 | #define RT1011_POW_MIX_T_BIT 2 |
|---|
| 558 | #define RT1011_BYPASS_MIX_T (0x1 << 1) |
|---|
| 559 | #define RT1011_BYPASS_MIX_T_BIT 1 |
|---|
| 560 | #define RT1011_POW_VREF_LV (0x1 << 0) |
|---|
| 561 | #define RT1011_POW_VREF_LV_BIT 0 |
|---|
| 562 | |
|---|
| 563 | /* POWER-4 (0x0328) */ |
|---|
| 564 | #define RT1011_POW_EN_SWR (0x1 << 12) |
|---|
| 565 | #define RT1011_POW_EN_SWR_BIT 12 |
|---|
| 566 | #define RT1011_POW_EN_PASS_BGOK_SWR (0x1 << 10) |
|---|
| 567 | #define RT1011_POW_EN_PASS_BGOK_SWR_BIT 10 |
|---|
| 568 | #define RT1011_POW_EN_PASS_VPOK_SWR (0x1 << 9) |
|---|
| 569 | #define RT1011_POW_EN_PASS_VPOK_SWR_BIT 9 |
|---|
| 570 | |
|---|
| 571 | /* POWER-9 (0x032d) */ |
|---|
| 572 | #define RT1011_POW_SDB_REG_MASK (0x1 << 9) |
|---|
| 573 | #define RT1011_POW_SDB_REG_BIT 9 |
|---|
| 574 | #define RT1011_POW_SDB_REG (0x1 << 9) |
|---|
| 575 | #define RT1011_POW_SEL_SDB_MODE_MASK (0x1 << 6) |
|---|
| 576 | #define RT1011_POW_SEL_SDB_MODE_BIT 6 |
|---|
| 577 | #define RT1011_POW_SEL_SDB_MODE (0x1 << 6) |
|---|
| 578 | #define RT1011_POW_MNL_SDB_MASK (0x1 << 5) |
|---|
| 579 | #define RT1011_POW_MNL_SDB_BIT 5 |
|---|
| 580 | #define RT1011_POW_MNL_SDB (0x1 << 5) |
|---|
| 581 | |
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| 582 | /* SPK Protection-Temperature Protection (0x050c) */ |
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| 583 | #define RT1011_STP_EN_MASK (0x1 << 15) |
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| 584 | #define RT1011_STP_EN_BIT 15 |
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| 585 | #define RT1011_STP_EN (0x1 << 15) |
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| 586 | #define RT1011_STP_RS_CLB_EN_MASK (0x1 << 14) |
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| 587 | #define RT1011_STP_RS_CLB_EN_BIT 14 |
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| 588 | #define RT1011_STP_RS_CLB_EN (0x1 << 14) |
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| 589 | |
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| 590 | /* SPK Protection-Temperature Protection-4 (0x0510) */ |
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| 591 | #define RT1011_STP_R0_SELECT_MASK (0x3 << 6) |
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| 592 | #define RT1011_STP_R0_SELECT_EFUSE (0x0 << 6) |
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| 593 | #define RT1011_STP_R0_SELECT_START_VAL (0x1 << 6) |
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| 594 | #define RT1011_STP_R0_SELECT_REG (0x2 << 6) |
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| 595 | #define RT1011_STP_R0_SELECT_FORCE_ZERO (0x3 << 6) |
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| 596 | |
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| 597 | /* SPK Protection-Temperature Protection-6 (0x0512) */ |
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| 598 | #define RT1011_STP_R0_EN_MASK (0x1 << 7) |
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| 599 | #define RT1011_STP_R0_EN_BIT 7 |
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| 600 | #define RT1011_STP_R0_EN (0x1 << 7) |
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| 601 | #define RT1011_STP_T0_EN_MASK (0x1 << 6) |
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| 602 | #define RT1011_STP_T0_EN_BIT 6 |
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| 603 | #define RT1011_STP_T0_EN (0x1 << 6) |
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| 604 | |
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| 605 | /* Cross Biquad Setting-1 (0x0702) */ |
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| 606 | #define RT1011_MONO_LR_SEL_MASK (0x3 << 5) |
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| 607 | #define RT1011_MONO_L_CHANNEL (0x0 << 5) |
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| 608 | #define RT1011_MONO_R_CHANNEL (0x1 << 5) |
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| 609 | #define RT1011_MONO_LR_MIX_CHANNEL (0x2 << 5) |
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| 610 | |
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| 611 | /* ClassD Internal Setting-1 (0x1300) */ |
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| 612 | #define RT1011_DRIVER_READY_SPK (0x1 << 12) |
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| 613 | #define RT1011_DRIVER_READY_SPK_BIT 12 |
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| 614 | #define RT1011_RECV_MODE_SPK_MASK (0x1 << 5) |
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| 615 | #define RT1011_SPK_MODE (0x0 << 5) |
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| 616 | #define RT1011_RECV_MODE (0x1 << 5) |
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| 617 | #define RT1011_RECV_MODE_SPK_BIT 5 |
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| 618 | |
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| 619 | /* ClassD Internal Setting-3 (0x1304) */ |
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| 620 | #define RT1011_REG_GAIN_CLASSD_RI_SPK_MASK (0x7 << 12) |
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| 621 | #define RT1011_REG_GAIN_CLASSD_RI_410K (0x0 << 12) |
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| 622 | #define RT1011_REG_GAIN_CLASSD_RI_95K (0x1 << 12) |
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| 623 | #define RT1011_REG_GAIN_CLASSD_RI_82P5K (0x2 << 12) |
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| 624 | #define RT1011_REG_GAIN_CLASSD_RI_72P5K (0x3 << 12) |
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| 625 | #define RT1011_REG_GAIN_CLASSD_RI_62P5K (0x4 << 12) |
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| 626 | |
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| 627 | /* ClassD Internal Setting-8 (0x130c) */ |
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| 628 | #define RT1011_TM_PORPVDD_SPK (0x1 << 1) |
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| 629 | #define RT1011_TM_PORPVDD_SPK_BIT 1 |
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| 630 | |
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| 631 | /* SPK Protection-Temperature Protection-SINE_GEN_REG-1 (0x1500) */ |
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| 632 | #define RT1011_STP_SIN_GEN_EN_MASK (0x1 << 13) |
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| 633 | #define RT1011_STP_SIN_GEN_EN (0x1 << 13) |
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| 634 | #define RT1011_STP_SIN_GEN_EN_BIT 13 |
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| 635 | |
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| 636 | |
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| 637 | /* System Clock Source */ |
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| 638 | enum { |
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| 639 | RT1011_FS_SYS_PRE_S_MCLK, |
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| 640 | RT1011_FS_SYS_PRE_S_BCLK, |
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| 641 | RT1011_FS_SYS_PRE_S_PLL1, |
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| 642 | RT1011_FS_SYS_PRE_S_RCCLK, /* 12M Hz */ |
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| 643 | }; |
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| 644 | |
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| 645 | /* PLL Source 1/2 */ |
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| 646 | enum { |
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| 647 | RT1011_PLL1_S_BCLK, |
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| 648 | RT1011_PLL2_S_MCLK, |
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| 649 | RT1011_PLL2_S_RCCLK, /* 12M Hz */ |
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| 650 | }; |
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| 651 | |
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| 652 | enum { |
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| 653 | RT1011_AIF1, |
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| 654 | RT1011_AIFS |
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| 655 | }; |
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| 656 | |
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| 657 | enum { |
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| 658 | RT1011_I2S_REF_NONE, |
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| 659 | RT1011_I2S_REF_LEFT_CH, |
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| 660 | RT1011_I2S_REF_RIGHT_CH, |
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| 661 | }; |
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| 662 | |
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| 663 | /* BiQual & DRC related settings */ |
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| 664 | #define RT1011_BQ_DRC_NUM 128 |
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| 665 | struct rt1011_bq_drc_params { |
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| 666 | unsigned short val; |
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| 667 | unsigned short reg; |
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| 668 | #ifdef CONFIG_64BIT |
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| 669 | unsigned int reserved; |
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| 670 | #endif |
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| 671 | }; |
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| 672 | enum { |
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| 673 | RT1011_ADVMODE_INITIAL_SET, |
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| 674 | RT1011_ADVMODE_SEP_BQ_COEFF, |
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| 675 | RT1011_ADVMODE_EQ_BQ_COEFF, |
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| 676 | RT1011_ADVMODE_BQ_UI_COEFF, |
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| 677 | RT1011_ADVMODE_SMARTBOOST_COEFF, |
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| 678 | RT1011_ADVMODE_NUM, |
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| 679 | }; |
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| 680 | |
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| 681 | struct rt1011_priv { |
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| 682 | struct snd_soc_component *component; |
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| 683 | struct regmap *regmap; |
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| 684 | struct work_struct cali_work; |
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| 685 | struct rt1011_bq_drc_params **bq_drc_params; |
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| 686 | |
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| 687 | int sysclk; |
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| 688 | int sysclk_src; |
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| 689 | int lrck; |
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| 690 | int bclk; |
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| 691 | int id; |
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| 692 | |
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| 693 | int pll_src; |
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| 694 | int pll_in; |
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| 695 | int pll_out; |
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| 696 | |
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| 697 | int bq_drc_set; |
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| 698 | unsigned int r0_reg, cali_done; |
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| 699 | unsigned int r0_calib, temperature_calib; |
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| 700 | int recv_spk_mode; |
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| 701 | int i2s_ref; |
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| 702 | }; |
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| 703 | |
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| 704 | #endif /* end of _RT1011_H_ */ |
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| 705 | |
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