| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * rt1308.h -- RT1308 ALSA SoC amplifier component driver |
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| 4 | * |
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| 5 | * Copyright 2019 Realtek Semiconductor Corp. |
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| 6 | * Author: Derek Fang <derek.fang@realtek.com> |
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| 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef _RT1308_H_ |
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| 11 | #define _RT1308_H_ |
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| 12 | |
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| 13 | #define RT1308_DEVICE_ID_NUM 0x10ec1300 |
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| 14 | |
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| 15 | #define RT1308_RESET 0x00 |
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| 16 | #define RT1308_RESET_N 0x01 |
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| 17 | #define RT1308_CLK_GATING 0x02 |
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| 18 | #define RT1308_PLL_1 0x03 |
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| 19 | #define RT1308_PLL_2 0x04 |
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| 20 | #define RT1308_PLL_INT 0x05 |
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| 21 | #define RT1308_CLK_1 0x06 |
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| 22 | #define RT1308_DATA_PATH 0x07 |
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| 23 | #define RT1308_CLK_2 0x08 |
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| 24 | #define RT1308_SIL_DET 0x09 |
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| 25 | #define RT1308_CLK_DET 0x0a |
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| 26 | #define RT1308_DC_DET 0x0b |
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| 27 | #define RT1308_DC_DET_THRES 0x0c |
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| 28 | #define RT1308_DAC_SET 0x10 |
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| 29 | #define RT1308_SRC_SET 0x11 |
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| 30 | #define RT1308_DAC_BUF 0x12 |
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| 31 | #define RT1308_ADC_SET 0x13 |
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| 32 | #define RT1308_ADC_SET_INT 0x14 |
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| 33 | #define RT1308_I2S_SET_1 0x15 |
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| 34 | #define RT1308_I2S_SET_2 0x16 |
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| 35 | #define RT1308_I2C_I2S_SDW_SET 0x17 |
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| 36 | #define RT1308_SDW_REG_RW 0x18 |
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| 37 | #define RT1308_SDW_REG_RDATA 0x19 |
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| 38 | #define RT1308_IV_SENSE 0x1a |
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| 39 | #define RT1308_I2S_TX_DAC_SET 0x1b |
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| 40 | #define RT1308_AD_FILTER_SET 0x1c |
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| 41 | #define RT1308_DC_CAL_1 0x20 |
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| 42 | #define RT1308_DC_CAL_2 0x21 |
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| 43 | #define RT1308_DC_CAL_L_OFFSET 0x22 |
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| 44 | #define RT1308_DC_CAL_R_OFFSET 0x23 |
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| 45 | #define RT1308_PVDD_OFFSET_CTL 0x24 |
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| 46 | #define RT1308_PVDD_OFFSET_L 0x25 |
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| 47 | #define RT1308_PVDD_OFFSET_R 0x26 |
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| 48 | #define RT1308_PVDD_OFFSET_PBTL 0x27 |
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| 49 | #define RT1308_PVDD_OFFSET_PVDD 0x28 |
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| 50 | #define RT1308_CAL_OFFSET_DAC_PBTL 0x29 |
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| 51 | #define RT1308_CAL_OFFSET_DAC_L 0x2a |
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| 52 | #define RT1308_CAL_OFFSET_DAC_R 0x2b |
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| 53 | #define RT1308_CAL_OFFSET_PWM_L 0x2c |
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| 54 | #define RT1308_CAL_OFFSET_PWM_R 0x2d |
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| 55 | #define RT1308_CAL_PWM_VOS_ADC_L 0x2e |
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| 56 | #define RT1308_CAL_PWM_VOS_ADC_R 0x2f |
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| 57 | #define RT1308_CLASS_D_SET_1 0x30 |
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| 58 | #define RT1308_CLASS_D_SET_2 0x31 |
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| 59 | #define RT1308_POWER 0x32 |
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| 60 | #define RT1308_LDO 0x33 |
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| 61 | #define RT1308_VREF 0x34 |
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| 62 | #define RT1308_MBIAS 0x35 |
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| 63 | #define RT1308_POWER_STATUS 0x36 |
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| 64 | #define RT1308_POWER_INT 0x37 |
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| 65 | #define RT1308_SINE_TONE_GEN_1 0x50 |
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| 66 | #define RT1308_SINE_TONE_GEN_2 0x51 |
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| 67 | #define RT1308_BQ_SET 0x54 |
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| 68 | #define RT1308_BQ_PARA_UPDATE 0x55 |
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| 69 | #define RT1308_BQ_PRE_VOL_L 0x56 |
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| 70 | #define RT1308_BQ_PRE_VOL_R 0x57 |
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| 71 | #define RT1308_BQ_POST_VOL_L 0x58 |
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| 72 | #define RT1308_BQ_POST_VOL_R 0x59 |
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| 73 | #define RT1308_BQ1_L_H0 0x5b |
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| 74 | #define RT1308_BQ1_L_B1 0x5c |
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| 75 | #define RT1308_BQ1_L_B2 0x5d |
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| 76 | #define RT1308_BQ1_L_A1 0x5e |
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| 77 | #define RT1308_BQ1_L_A2 0x5f |
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| 78 | #define RT1308_BQ1_R_H0 0x60 |
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| 79 | #define RT1308_BQ1_R_B1 0x61 |
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| 80 | #define RT1308_BQ1_R_B2 0x62 |
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| 81 | #define RT1308_BQ1_R_A1 0x63 |
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| 82 | #define RT1308_BQ1_R_A2 0x64 |
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| 83 | #define RT1308_BQ2_L_H0 0x65 |
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| 84 | #define RT1308_BQ2_L_B1 0x66 |
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| 85 | #define RT1308_BQ2_L_B2 0x67 |
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| 86 | #define RT1308_BQ2_L_A1 0x68 |
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| 87 | #define RT1308_BQ2_L_A2 0x69 |
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| 88 | #define RT1308_BQ2_R_H0 0x6a |
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| 89 | #define RT1308_BQ2_R_B1 0x6b |
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| 90 | #define RT1308_BQ2_R_B2 0x6c |
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| 91 | #define RT1308_BQ2_R_A1 0x6d |
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| 92 | #define RT1308_BQ2_R_A2 0x6e |
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| 93 | #define RT1308_VEN_DEV_ID 0x70 |
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| 94 | #define RT1308_VERSION_ID 0x71 |
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| 95 | #define RT1308_SPK_BOUND 0x72 |
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| 96 | #define RT1308_BQ1_EQ_L_1 0x73 |
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| 97 | #define RT1308_BQ1_EQ_L_2 0x74 |
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| 98 | #define RT1308_BQ1_EQ_L_3 0x75 |
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| 99 | #define RT1308_BQ1_EQ_R_1 0x76 |
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| 100 | #define RT1308_BQ1_EQ_R_2 0x77 |
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| 101 | #define RT1308_BQ1_EQ_R_3 0x78 |
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| 102 | #define RT1308_BQ2_EQ_L_1 0x79 |
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| 103 | #define RT1308_BQ2_EQ_L_2 0x7a |
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| 104 | #define RT1308_BQ2_EQ_L_3 0x7b |
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| 105 | #define RT1308_BQ2_EQ_R_1 0x7c |
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| 106 | #define RT1308_BQ2_EQ_R_2 0x7d |
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| 107 | #define RT1308_BQ2_EQ_R_3 0x7e |
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| 108 | #define RT1308_EFUSE_1 0x7f |
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| 109 | #define RT1308_EFUSE_2 0x80 |
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| 110 | #define RT1308_EFUSE_PROG_PVDD_L 0x81 |
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| 111 | #define RT1308_EFUSE_PROG_PVDD_R 0x82 |
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| 112 | #define RT1308_EFUSE_PROG_R0_L 0x83 |
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| 113 | #define RT1308_EFUSE_PROG_R0_R 0x84 |
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| 114 | #define RT1308_EFUSE_PROG_DEV 0x85 |
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| 115 | #define RT1308_EFUSE_READ_PVDD_L 0x86 |
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| 116 | #define RT1308_EFUSE_READ_PVDD_R 0x87 |
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| 117 | #define RT1308_EFUSE_READ_PVDD_PTBL 0x88 |
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| 118 | #define RT1308_EFUSE_READ_DEV 0x89 |
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| 119 | #define RT1308_EFUSE_READ_R0 0x8a |
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| 120 | #define RT1308_EFUSE_READ_ADC_L 0x8b |
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| 121 | #define RT1308_EFUSE_READ_ADC_R 0x8c |
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| 122 | #define RT1308_EFUSE_READ_ADC_PBTL 0x8d |
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| 123 | #define RT1308_EFUSE_RESERVE 0x8e |
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| 124 | #define RT1308_PADS_1 0x90 |
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| 125 | #define RT1308_PADS_2 0x91 |
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| 126 | #define RT1308_TEST_MODE 0xa0 |
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| 127 | #define RT1308_TEST_1 0xa1 |
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| 128 | #define RT1308_TEST_2 0xa2 |
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| 129 | #define RT1308_TEST_3 0xa3 |
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| 130 | #define RT1308_TEST_4 0xa4 |
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| 131 | #define RT1308_EFUSE_DATA_0_MSB 0xb0 |
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| 132 | #define RT1308_EFUSE_DATA_0_LSB 0xb1 |
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| 133 | #define RT1308_EFUSE_DATA_1_MSB 0xb2 |
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| 134 | #define RT1308_EFUSE_DATA_1_LSB 0xb3 |
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| 135 | #define RT1308_EFUSE_DATA_2_MSB 0xb4 |
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| 136 | #define RT1308_EFUSE_DATA_2_LSB 0xb5 |
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| 137 | #define RT1308_EFUSE_DATA_3_MSB 0xb6 |
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| 138 | #define RT1308_EFUSE_DATA_3_LSB 0xb7 |
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| 139 | #define RT1308_EFUSE_DATA_TEST_MSB 0xb8 |
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| 140 | #define RT1308_EFUSE_DATA_TEST_LSB 0xb9 |
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| 141 | #define RT1308_EFUSE_STATUS_1 0xba |
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| 142 | #define RT1308_EFUSE_STATUS_2 0xbb |
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| 143 | #define RT1308_TCON_1 0xc0 |
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| 144 | #define RT1308_TCON_2 0xc1 |
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| 145 | #define RT1308_DUMMY_REG 0xf0 |
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| 146 | #define RT1308_MAX_REG 0xff |
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| 147 | |
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| 148 | /* PLL1 M/N/K Code-1 (0x03) */ |
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| 149 | #define RT1308_PLL1_K_SFT 24 |
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| 150 | #define RT1308_PLL1_K_MASK (0x1f << 24) |
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| 151 | #define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23) |
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| 152 | #define RT1308_PLL1_M_BYPASS_SFT 23 |
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| 153 | #define RT1308_PLL1_M_BYPASS (0x1 << 23) |
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| 154 | #define RT1308_PLL1_M_MASK (0x3f << 16) |
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| 155 | #define RT1308_PLL1_M_SFT 16 |
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| 156 | #define RT1308_PLL1_N_MASK (0x7f << 8) |
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| 157 | #define RT1308_PLL1_N_SFT 8 |
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| 158 | |
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| 159 | /* CLOCK-1 (0x06) */ |
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| 160 | #define RT1308_DIV_FS_SYS_MASK (0xf << 28) |
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| 161 | #define RT1308_DIV_FS_SYS_SFT 28 |
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| 162 | #define RT1308_SEL_FS_SYS_MASK (0x7 << 24) |
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| 163 | #define RT1308_SEL_FS_SYS_SFT 24 |
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| 164 | #define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24) |
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| 165 | #define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24) |
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| 166 | #define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24) |
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| 167 | #define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24) |
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| 168 | |
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| 169 | /* CLOCK-2 (0x08) */ |
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| 170 | #define RT1308_DIV_PRE_PLL_MASK (0xf << 28) |
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| 171 | #define RT1308_DIV_PRE_PLL_SFT 28 |
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| 172 | #define RT1308_SEL_PLL_SRC_MASK (0x7 << 24) |
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| 173 | #define RT1308_SEL_PLL_SRC_SFT 24 |
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| 174 | #define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24) |
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| 175 | #define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24) |
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| 176 | #define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24) |
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| 177 | |
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| 178 | /* Clock Detect (0x0a) */ |
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| 179 | #define RT1308_MCLK_DET_EN_MASK (0x1 << 25) |
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| 180 | #define RT1308_MCLK_DET_EN_SFT 25 |
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| 181 | #define RT1308_MCLK_DET_EN (0x1 << 25) |
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| 182 | #define RT1308_BCLK_DET_EN_MASK (0x1 << 24) |
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| 183 | #define RT1308_BCLK_DET_EN_SFT 24 |
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| 184 | #define RT1308_BCLK_DET_EN (0x1 << 24) |
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| 185 | |
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| 186 | /* DAC Setting (0x10) */ |
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| 187 | #define RT1308_DVOL_MUTE_R_EN_SFT 7 |
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| 188 | #define RT1308_DVOL_MUTE_L_EN_SFT 6 |
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| 189 | |
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| 190 | /* I2S Setting-1 (0x15) */ |
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| 191 | #define RT1308_I2S_DF_SEL_MASK (0x3 << 12) |
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| 192 | #define RT1308_I2S_DF_SEL_SFT 12 |
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| 193 | #define RT1308_I2S_DF_SEL_I2S (0x0 << 12) |
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| 194 | #define RT1308_I2S_DF_SEL_LEFT (0x1 << 12) |
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| 195 | #define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12) |
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| 196 | #define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12) |
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| 197 | #define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4) |
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| 198 | #define RT1308_I2S_DL_RX_SEL_SFT 4 |
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| 199 | #define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4) |
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| 200 | #define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4) |
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| 201 | #define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4) |
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| 202 | #define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4) |
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| 203 | #define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4) |
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| 204 | #define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0) |
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| 205 | #define RT1308_I2S_DL_TX_SEL_SFT 0 |
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| 206 | #define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0) |
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| 207 | #define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0) |
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| 208 | #define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0) |
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| 209 | #define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0) |
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| 210 | #define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0) |
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| 211 | |
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| 212 | /* I2S Setting-2 (0x16) */ |
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| 213 | #define RT1308_I2S_DL_SEL_MASK (0x7 << 24) |
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| 214 | #define RT1308_I2S_DL_SEL_SFT 24 |
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| 215 | #define RT1308_I2S_DL_SEL_16B (0x0 << 24) |
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| 216 | #define RT1308_I2S_DL_SEL_20B (0x1 << 24) |
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| 217 | #define RT1308_I2S_DL_SEL_24B (0x2 << 24) |
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| 218 | #define RT1308_I2S_DL_SEL_32B (0x3 << 24) |
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| 219 | #define RT1308_I2S_DL_SEL_8B (0x4 << 24) |
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| 220 | #define RT1308_I2S_BCLK_MASK (0x1 << 14) |
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| 221 | #define RT1308_I2S_BCLK_SFT 14 |
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| 222 | #define RT1308_I2S_BCLK_NORMAL (0x0 << 14) |
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| 223 | #define RT1308_I2S_BCLK_INV (0x1 << 14) |
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| 224 | |
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| 225 | /* Power Control-1 (0x32) */ |
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| 226 | #define RT1308_POW_MBIAS20U (0x1 << 31) |
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| 227 | #define RT1308_POW_MBIAS20U_BIT 31 |
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| 228 | #define RT1308_POW_ALDO (0x1 << 30) |
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| 229 | #define RT1308_POW_ALDO_BIT 30 |
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| 230 | #define RT1308_POW_DBG (0x1 << 29) |
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| 231 | #define RT1308_POW_DBG_BIT 29 |
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| 232 | #define RT1308_POW_DACL (0x1 << 28) |
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| 233 | #define RT1308_POW_DACL_BIT 28 |
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| 234 | #define RT1308_POW_DAC1 (0x1 << 27) |
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| 235 | #define RT1308_POW_DAC1_BIT 27 |
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| 236 | #define RT1308_POW_CLK25M (0x1 << 26) |
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| 237 | #define RT1308_POW_CLK25M_BIT 26 |
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| 238 | #define RT1308_POW_ADC_R (0x1 << 25) |
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| 239 | #define RT1308_POW_ADC_R_BIT 25 |
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| 240 | #define RT1308_POW_ADC_L (0x1 << 24) |
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| 241 | #define RT1308_POW_ADC_L_BIT 24 |
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| 242 | #define RT1308_POW_DLDO (0x1 << 21) |
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| 243 | #define RT1308_POW_DLDO_BIT 21 |
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| 244 | #define RT1308_POW_VREF (0x1 << 20) |
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| 245 | #define RT1308_POW_VREF_BIT 20 |
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| 246 | #define RT1308_POW_MIXER_R (0x1 << 18) |
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| 247 | #define RT1308_POW_MIXER_R_BIT 18 |
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| 248 | #define RT1308_POW_MIXER_L (0x1 << 17) |
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| 249 | #define RT1308_POW_MIXER_L_BIT 17 |
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| 250 | #define RT1308_POW_MBIAS4U (0x1 << 16) |
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| 251 | #define RT1308_POW_MBIAS4U_BIT 16 |
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| 252 | #define RT1308_POW_PLL2_LDO_EN (0x1 << 12) |
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| 253 | #define RT1308_POW_PLL2_LDO_EN_BIT 12 |
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| 254 | #define RT1308_POW_PLL2B_EN (0x1 << 11) |
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| 255 | #define RT1308_POW_PLL2B_EN_BIT 11 |
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| 256 | #define RT1308_POW_PLL2F_EN (0x1 << 10) |
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| 257 | #define RT1308_POW_PLL2F_EN_BIT 10 |
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| 258 | #define RT1308_POW_PLL2F2_EN (0x1 << 9) |
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| 259 | #define RT1308_POW_PLL2F2_EN_BIT 9 |
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| 260 | #define RT1308_POW_PLL2B2_EN (0x1 << 8) |
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| 261 | #define RT1308_POW_PLL2B2_EN_BIT 8 |
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| 262 | |
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| 263 | /* Power Control-2 (0x36) */ |
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| 264 | #define RT1308_POW_PDB_SRC_BIT (0x1 << 27) |
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| 265 | #define RT1308_POW_PDB_MN_BIT (0x1 << 25) |
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| 266 | #define RT1308_POW_PDB_REG_BIT (0x1 << 24) |
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| 267 | |
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| 268 | |
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| 269 | /* System Clock Source */ |
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| 270 | enum { |
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| 271 | RT1308_FS_SYS_S_MCLK, |
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| 272 | RT1308_FS_SYS_S_BCLK, |
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| 273 | RT1308_FS_SYS_S_PLL, |
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| 274 | RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */ |
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| 275 | }; |
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| 276 | |
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| 277 | /* PLL Source */ |
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| 278 | enum { |
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| 279 | RT1308_PLL_S_MCLK, |
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| 280 | RT1308_PLL_S_BCLK, |
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| 281 | RT1308_PLL_S_RCCLK, |
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| 282 | }; |
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| 283 | |
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| 284 | enum { |
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| 285 | RT1308_AIF1, |
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| 286 | RT1308_AIFS |
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| 287 | }; |
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| 288 | |
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| 289 | enum rt1308_hw_ver { |
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| 290 | RT1308_VER_C = 2, |
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| 291 | RT1308_VER_D |
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| 292 | }; |
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| 293 | |
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| 294 | #endif /* end of _RT1308_H_ */ |
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| 295 | |
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