1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * rt274.h -- RT274 ALSA SoC audio driver |
4 | * |
5 | * Copyright 2016 Realtek Microelectronics |
6 | * Author: Bard Liao <bardliao@realtek.com> |
7 | */ |
8 | |
9 | #ifndef __RT274_H__ |
10 | #define __RT274_H__ |
11 | |
12 | #define VERB_CMD(V, N, D) ((N << 20) | (V << 8) | D) |
13 | |
14 | #define RT274_AUDIO_FUNCTION_GROUP 0x01 |
15 | #define RT274_DAC_OUT0 0x02 |
16 | #define RT274_DAC_OUT1 0x03 |
17 | #define RT274_ADC_IN2 0x08 |
18 | #define RT274_ADC_IN1 0x09 |
19 | #define RT274_DIG_CVT 0x0a |
20 | #define RT274_DMIC1 0x12 |
21 | #define RT274_DMIC2 0x13 |
22 | #define RT274_MIC 0x19 |
23 | #define RT274_LINE1 0x1a |
24 | #define RT274_LINE2 0x1b |
25 | #define RT274_LINE3 0x16 |
26 | #define RT274_SPDIF 0x1e |
27 | #define RT274_VENDOR_REGISTERS 0x20 |
28 | #define RT274_HP_OUT 0x21 |
29 | #define RT274_MIXER_IN1 0x22 |
30 | #define RT274_MIXER_IN2 0x23 |
31 | #define RT274_INLINE_CMD 0x55 |
32 | |
33 | #define RT274_SET_PIN_SFT 6 |
34 | #define RT274_SET_PIN_ENABLE 0x40 |
35 | #define RT274_SET_PIN_DISABLE 0 |
36 | #define RT274_SET_EAPD_HIGH 0x2 |
37 | #define RT274_SET_EAPD_LOW 0 |
38 | |
39 | #define RT274_MUTE_SFT 7 |
40 | |
41 | /* Verb commands */ |
42 | #define RT274_RESET\ |
43 | VERB_CMD(AC_VERB_SET_CODEC_RESET, RT274_AUDIO_FUNCTION_GROUP, 0) |
44 | #define RT274_GET_PARAM(NID, PARAM) VERB_CMD(AC_VERB_PARAMETERS, NID, PARAM) |
45 | #define RT274_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0) |
46 | #define RT274_SET_AUDIO_POWER RT274_SET_POWER(RT274_AUDIO_FUNCTION_GROUP) |
47 | #define RT274_SET_HPO_POWER RT274_SET_POWER(RT274_HP_OUT) |
48 | #define RT274_SET_DMIC1_POWER RT274_SET_POWER(RT274_DMIC1) |
49 | #define RT274_LOUT_MUX\ |
50 | VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_LINE3, 0) |
51 | #define RT274_HPO_MUX\ |
52 | VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_HP_OUT, 0) |
53 | #define RT274_ADC0_MUX\ |
54 | VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_MIXER_IN1, 0) |
55 | #define RT274_ADC1_MUX\ |
56 | VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT274_MIXER_IN2, 0) |
57 | #define RT274_SET_MIC\ |
58 | VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_MIC, 0) |
59 | #define RT274_SET_PIN_LOUT3\ |
60 | VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_LINE3, 0) |
61 | #define RT274_SET_PIN_HPO\ |
62 | VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0) |
63 | #define RT274_SET_PIN_DMIC1\ |
64 | VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0) |
65 | #define RT274_SET_PIN_SPDIF\ |
66 | VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT274_SPDIF, 0) |
67 | #define RT274_SET_PIN_DIG_CVT\ |
68 | VERB_CMD(AC_VERB_SET_DIGI_CONVERT_1, RT274_DIG_CVT, 0) |
69 | #define RT274_SET_AMP_GAIN_HPO\ |
70 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0) |
71 | #define RT274_SET_AMP_GAIN_ADC_IN1\ |
72 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0) |
73 | #define RT274_SET_AMP_GAIN_ADC_IN2\ |
74 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0) |
75 | #define RT274_GET_HP_SENSE\ |
76 | VERB_CMD(AC_VERB_GET_PIN_SENSE, RT274_HP_OUT, 0) |
77 | #define RT274_GET_MIC_SENSE\ |
78 | VERB_CMD(AC_VERB_GET_PIN_SENSE, RT274_MIC, 0) |
79 | #define RT274_SET_DMIC2_DEFAULT\ |
80 | VERB_CMD(AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, RT274_DMIC2, 0) |
81 | #define RT274_SET_SPDIF_DEFAULT\ |
82 | VERB_CMD(AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, RT274_SPDIF, 0) |
83 | #define RT274_DAC0L_GAIN\ |
84 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0xa000) |
85 | #define RT274_DAC0R_GAIN\ |
86 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0x9000) |
87 | #define RT274_DAC1L_GAIN\ |
88 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0xa000) |
89 | #define RT274_DAC1R_GAIN\ |
90 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0x9000) |
91 | #define RT274_ADCL_GAIN\ |
92 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0x6000) |
93 | #define RT274_ADCR_GAIN\ |
94 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0x5000) |
95 | #define RT274_MIC_GAIN\ |
96 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_MIC, 0x7000) |
97 | #define RT274_LOUTL_GAIN\ |
98 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_LINE3, 0xa000) |
99 | #define RT274_LOUTR_GAIN\ |
100 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_LINE3, 0x9000) |
101 | #define RT274_HPOL_GAIN\ |
102 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0xa000) |
103 | #define RT274_HPOR_GAIN\ |
104 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT274_HP_OUT, 0x9000) |
105 | #define RT274_DAC_FORMAT\ |
106 | VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT274_DAC_OUT0, 0) |
107 | #define RT274_ADC_FORMAT\ |
108 | VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT274_ADC_IN1, 0) |
109 | #define RT274_COEF_INDEX\ |
110 | VERB_CMD(AC_VERB_SET_COEF_INDEX, RT274_VENDOR_REGISTERS, 0) |
111 | #define RT274_PROC_COEF\ |
112 | VERB_CMD(AC_VERB_SET_PROC_COEF, RT274_VENDOR_REGISTERS, 0) |
113 | #define RT274_UNSOLICITED_INLINE_CMD\ |
114 | VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_INLINE_CMD, 0) |
115 | #define RT274_UNSOLICITED_HP_OUT\ |
116 | VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_HP_OUT, 0) |
117 | #define RT274_UNSOLICITED_MIC\ |
118 | VERB_CMD(AC_VERB_SET_UNSOLICITED_ENABLE, RT274_MIC, 0) |
119 | #define RT274_COEF58_INDEX\ |
120 | VERB_CMD(AC_VERB_SET_COEF_INDEX, 0x58, 0) |
121 | #define RT274_COEF58_COEF\ |
122 | VERB_CMD(AC_VERB_SET_PROC_COEF, 0x58, 0) |
123 | #define RT274_COEF5b_INDEX\ |
124 | VERB_CMD(AC_VERB_SET_COEF_INDEX, 0x5b, 0) |
125 | #define RT274_COEF5b_COEF\ |
126 | VERB_CMD(AC_VERB_SET_PROC_COEF, 0x5b, 0) |
127 | #define RT274_SET_STREAMID_DAC0\ |
128 | VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_DAC_OUT0, 0) |
129 | #define RT274_SET_STREAMID_DAC1\ |
130 | VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_DAC_OUT1, 0) |
131 | #define RT274_SET_STREAMID_ADC1\ |
132 | VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_ADC_IN1, 0) |
133 | #define RT274_SET_STREAMID_ADC2\ |
134 | VERB_CMD(AC_VERB_SET_CHANNEL_STREAMID, RT274_ADC_IN2, 0) |
135 | |
136 | /* Index registers */ |
137 | #define RT274_EAPD_GPIO_IRQ_CTRL 0x10 |
138 | #define RT274_PAD_CTRL12 0x35 |
139 | #define RT274_I2S_CTRL1 0x63 |
140 | #define RT274_I2S_CTRL2 0x64 |
141 | #define RT274_MCLK_CTRL 0x71 |
142 | #define RT274_CLK_CTRL 0x72 |
143 | #define RT274_PLL2_CTRL 0x7b |
144 | |
145 | |
146 | /* EAPD GPIO IRQ control (Index 0x10) */ |
147 | #define RT274_IRQ_DIS (0x0 << 13) |
148 | #define RT274_IRQ_EN (0x1 << 13) |
149 | #define RT274_IRQ_CLR (0x1 << 12) |
150 | #define RT274_GPI2_SEL_MASK (0x3 << 7) |
151 | #define RT274_GPI2_SEL_GPIO2 (0x0 << 7) |
152 | #define RT274_GPI2_SEL_I2S (0x1 << 7) |
153 | #define RT274_GPI2_SEL_DMIC_CLK (0x2 << 7) |
154 | #define RT274_GPI2_SEL_CBJ (0x3 << 7) |
155 | |
156 | /* Front I2S_Interface control 1 (Index 0x63) */ |
157 | #define RT274_I2S_MODE_MASK (0x1 << 11) |
158 | #define RT274_I2S_MODE_S (0x0 << 11) |
159 | #define RT274_I2S_MODE_M (0x1 << 11) |
160 | #define RT274_TDM_DIS (0x0 << 10) |
161 | #define RT274_TDM_EN (0x1 << 10) |
162 | #define RT274_TDM_CH_NUM (0x1 << 7) |
163 | #define RT274_TDM_2CH (0x0 << 7) |
164 | #define RT274_TDM_4CH (0x1 << 7) |
165 | #define RT274_I2S_FMT_MASK (0x3 << 8) |
166 | #define RT274_I2S_FMT_I2S (0x0 << 8) |
167 | #define RT274_I2S_FMT_LJ (0x1 << 8) |
168 | #define RT274_I2S_FMT_PCMA (0x2 << 8) |
169 | #define RT274_I2S_FMT_PCMB (0x3 << 8) |
170 | |
171 | /* MCLK clock domain control (Index 0x71) */ |
172 | #define RT274_MCLK_MODE_MASK (0x1 << 14) |
173 | #define RT274_MCLK_MODE_DIS (0x0 << 14) |
174 | #define RT274_MCLK_MODE_EN (0x1 << 14) |
175 | |
176 | /* Clock control (Index 0x72) */ |
177 | #define RT274_CLK_SRC_MASK (0x7 << 3) |
178 | #define RT274_CLK_SRC_MCLK (0x0 << 3) |
179 | #define RT274_CLK_SRC_PLL2 (0x3 << 3) |
180 | |
181 | /* PLL2 control (Index 0x7b) */ |
182 | #define RT274_PLL2_SRC_MASK (0x1 << 13) |
183 | #define RT274_PLL2_SRC_MCLK (0x0 << 13) |
184 | #define RT274_PLL2_SRC_BCLK (0x1 << 13) |
185 | |
186 | /* HP-OUT (0x21) */ |
187 | #define RT274_M_HP_MUX_SFT 14 |
188 | #define RT274_HP_SEL_MASK 0x1 |
189 | #define RT274_HP_SEL_SFT 0 |
190 | #define RT274_HP_SEL_F 0 |
191 | #define RT274_HP_SEL_S 1 |
192 | |
193 | /* ADC (0x22) (0x23) */ |
194 | #define RT274_ADC_SEL_MASK 0x7 |
195 | #define RT274_ADC_SEL_SFT 0 |
196 | #define RT274_ADC_SEL_MIC 0 |
197 | #define RT274_ADC_SEL_LINE1 1 |
198 | #define RT274_ADC_SEL_LINE2 2 |
199 | #define RT274_ADC_SEL_DMIC 3 |
200 | |
201 | #define RT274_SCLK_S_MCLK 0 |
202 | #define RT274_SCLK_S_PLL1 1 |
203 | #define RT274_SCLK_S_PLL2 2 |
204 | |
205 | #define RT274_PLL2_S_MCLK 0 |
206 | #define RT274_PLL2_S_BCLK 1 |
207 | |
208 | enum { |
209 | RT274_AIF1, |
210 | RT274_AIFS, |
211 | }; |
212 | |
213 | #endif /* __RT274_H__ */ |
214 | |
215 | |