1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver |
4 | * |
5 | * Copyright 2015 Realtek Microelectronics |
6 | * Author: Bard Liao <bardliao@realtek.com> |
7 | */ |
8 | |
9 | #ifndef __RT5659_H__ |
10 | #define __RT5659_H__ |
11 | |
12 | #include <sound/rt5659.h> |
13 | |
14 | #define DEVICE_ID 0x6311 |
15 | |
16 | /* Info */ |
17 | #define RT5659_RESET 0x0000 |
18 | #define RT5659_VENDOR_ID 0x00fd |
19 | #define RT5659_VENDOR_ID_1 0x00fe |
20 | #define RT5659_DEVICE_ID 0x00ff |
21 | /* I/O - Output */ |
22 | #define RT5659_SPO_VOL 0x0001 |
23 | #define RT5659_HP_VOL 0x0002 |
24 | #define RT5659_LOUT 0x0003 |
25 | #define RT5659_MONO_OUT 0x0004 |
26 | #define RT5659_HPL_GAIN 0x0005 |
27 | #define RT5659_HPR_GAIN 0x0006 |
28 | #define RT5659_MONO_GAIN 0x0007 |
29 | #define RT5659_SPDIF_CTRL_1 0x0008 |
30 | #define RT5659_SPDIF_CTRL_2 0x0009 |
31 | /* I/O - Input */ |
32 | #define RT5659_CAL_BST_CTRL 0x000a |
33 | #define RT5659_IN1_IN2 0x000c |
34 | #define RT5659_IN3_IN4 0x000d |
35 | #define RT5659_INL1_INR1_VOL 0x000f |
36 | /* I/O - Speaker */ |
37 | #define RT5659_EJD_CTRL_1 0x0010 |
38 | #define RT5659_EJD_CTRL_2 0x0011 |
39 | #define RT5659_EJD_CTRL_3 0x0012 |
40 | #define RT5659_SILENCE_CTRL 0x0015 |
41 | #define RT5659_PSV_CTRL 0x0016 |
42 | /* I/O - Sidetone */ |
43 | #define RT5659_SIDETONE_CTRL 0x0018 |
44 | /* I/O - ADC/DAC/DMIC */ |
45 | #define RT5659_DAC1_DIG_VOL 0x0019 |
46 | #define RT5659_DAC2_DIG_VOL 0x001a |
47 | #define RT5659_DAC_CTRL 0x001b |
48 | #define RT5659_STO1_ADC_DIG_VOL 0x001c |
49 | #define RT5659_MONO_ADC_DIG_VOL 0x001d |
50 | #define RT5659_STO2_ADC_DIG_VOL 0x001e |
51 | #define RT5659_STO1_BOOST 0x001f |
52 | #define RT5659_MONO_BOOST 0x0020 |
53 | #define RT5659_STO2_BOOST 0x0021 |
54 | #define RT5659_HP_IMP_GAIN_1 0x0022 |
55 | #define RT5659_HP_IMP_GAIN_2 0x0023 |
56 | /* Mixer - D-D */ |
57 | #define RT5659_STO1_ADC_MIXER 0x0026 |
58 | #define RT5659_MONO_ADC_MIXER 0x0027 |
59 | #define RT5659_AD_DA_MIXER 0x0029 |
60 | #define RT5659_STO_DAC_MIXER 0x002a |
61 | #define RT5659_MONO_DAC_MIXER 0x002b |
62 | #define RT5659_DIG_MIXER 0x002c |
63 | #define RT5659_A_DAC_MUX 0x002d |
64 | #define RT5659_DIG_INF23_DATA 0x002f |
65 | /* Mixer - PDM */ |
66 | #define RT5659_PDM_OUT_CTRL 0x0031 |
67 | #define RT5659_PDM_DATA_CTRL_1 0x0032 |
68 | #define RT5659_PDM_DATA_CTRL_2 0x0033 |
69 | #define RT5659_PDM_DATA_CTRL_3 0x0034 |
70 | #define RT5659_PDM_DATA_CTRL_4 0x0035 |
71 | #define RT5659_SPDIF_CTRL 0x0036 |
72 | |
73 | /* Mixer - ADC */ |
74 | #define RT5659_REC1_GAIN 0x003a |
75 | #define RT5659_REC1_L1_MIXER 0x003b |
76 | #define RT5659_REC1_L2_MIXER 0x003c |
77 | #define RT5659_REC1_R1_MIXER 0x003d |
78 | #define RT5659_REC1_R2_MIXER 0x003e |
79 | #define RT5659_CAL_REC 0x0040 |
80 | #define RT5659_REC2_L1_MIXER 0x009b |
81 | #define RT5659_REC2_L2_MIXER 0x009c |
82 | #define RT5659_REC2_R1_MIXER 0x009d |
83 | #define RT5659_REC2_R2_MIXER 0x009e |
84 | #define RT5659_RC_CLK_CTRL 0x009f |
85 | /* Mixer - DAC */ |
86 | #define RT5659_SPK_L_MIXER 0x0046 |
87 | #define RT5659_SPK_R_MIXER 0x0047 |
88 | #define RT5659_SPO_AMP_GAIN 0x0048 |
89 | #define RT5659_ALC_BACK_GAIN 0x0049 |
90 | #define RT5659_MONOMIX_GAIN 0x004a |
91 | #define RT5659_MONOMIX_IN_GAIN 0x004b |
92 | #define RT5659_OUT_L_GAIN 0x004d |
93 | #define RT5659_OUT_L_MIXER 0x004e |
94 | #define RT5659_OUT_R_GAIN 0x004f |
95 | #define RT5659_OUT_R_MIXER 0x0050 |
96 | #define RT5659_LOUT_MIXER 0x0052 |
97 | |
98 | #define RT5659_HAPTIC_GEN_CTRL_1 0x0053 |
99 | #define RT5659_HAPTIC_GEN_CTRL_2 0x0054 |
100 | #define RT5659_HAPTIC_GEN_CTRL_3 0x0055 |
101 | #define RT5659_HAPTIC_GEN_CTRL_4 0x0056 |
102 | #define RT5659_HAPTIC_GEN_CTRL_5 0x0057 |
103 | #define RT5659_HAPTIC_GEN_CTRL_6 0x0058 |
104 | #define RT5659_HAPTIC_GEN_CTRL_7 0x0059 |
105 | #define RT5659_HAPTIC_GEN_CTRL_8 0x005a |
106 | #define RT5659_HAPTIC_GEN_CTRL_9 0x005b |
107 | #define RT5659_HAPTIC_GEN_CTRL_10 0x005c |
108 | #define RT5659_HAPTIC_GEN_CTRL_11 0x005d |
109 | #define RT5659_HAPTIC_LPF_CTRL_1 0x005e |
110 | #define RT5659_HAPTIC_LPF_CTRL_2 0x005f |
111 | #define RT5659_HAPTIC_LPF_CTRL_3 0x0060 |
112 | /* Power */ |
113 | #define RT5659_PWR_DIG_1 0x0061 |
114 | #define RT5659_PWR_DIG_2 0x0062 |
115 | #define RT5659_PWR_ANLG_1 0x0063 |
116 | #define RT5659_PWR_ANLG_2 0x0064 |
117 | #define RT5659_PWR_ANLG_3 0x0065 |
118 | #define RT5659_PWR_MIXER 0x0066 |
119 | #define RT5659_PWR_VOL 0x0067 |
120 | /* Private Register Control */ |
121 | #define RT5659_PRIV_INDEX 0x006a |
122 | #define RT5659_CLK_DET 0x006b |
123 | #define RT5659_PRIV_DATA 0x006c |
124 | /* System Clock Pre Divider Gating Control */ |
125 | #define RT5659_PRE_DIV_1 0x006e |
126 | #define RT5659_PRE_DIV_2 0x006f |
127 | /* Format - ADC/DAC */ |
128 | #define RT5659_I2S1_SDP 0x0070 |
129 | #define RT5659_I2S2_SDP 0x0071 |
130 | #define RT5659_I2S3_SDP 0x0072 |
131 | #define RT5659_ADDA_CLK_1 0x0073 |
132 | #define RT5659_ADDA_CLK_2 0x0074 |
133 | #define RT5659_DMIC_CTRL_1 0x0075 |
134 | #define RT5659_DMIC_CTRL_2 0x0076 |
135 | /* Format - TDM Control */ |
136 | #define RT5659_TDM_CTRL_1 0x0077 |
137 | #define RT5659_TDM_CTRL_2 0x0078 |
138 | #define RT5659_TDM_CTRL_3 0x0079 |
139 | #define RT5659_TDM_CTRL_4 0x007a |
140 | #define RT5659_TDM_CTRL_5 0x007b |
141 | |
142 | /* Function - Analog */ |
143 | #define RT5659_GLB_CLK 0x0080 |
144 | #define RT5659_PLL_CTRL_1 0x0081 |
145 | #define RT5659_PLL_CTRL_2 0x0082 |
146 | #define RT5659_ASRC_1 0x0083 |
147 | #define RT5659_ASRC_2 0x0084 |
148 | #define RT5659_ASRC_3 0x0085 |
149 | #define RT5659_ASRC_4 0x0086 |
150 | #define RT5659_ASRC_5 0x0087 |
151 | #define RT5659_ASRC_6 0x0088 |
152 | #define RT5659_ASRC_7 0x0089 |
153 | #define RT5659_ASRC_8 0x008a |
154 | #define RT5659_ASRC_9 0x008b |
155 | #define RT5659_ASRC_10 0x008c |
156 | #define RT5659_DEPOP_1 0x008e |
157 | #define RT5659_DEPOP_2 0x008f |
158 | #define RT5659_DEPOP_3 0x0090 |
159 | #define RT5659_HP_CHARGE_PUMP_1 0x0091 |
160 | #define RT5659_HP_CHARGE_PUMP_2 0x0092 |
161 | #define RT5659_MICBIAS_1 0x0093 |
162 | #define RT5659_MICBIAS_2 0x0094 |
163 | #define RT5659_ASRC_11 0x0097 |
164 | #define RT5659_ASRC_12 0x0098 |
165 | #define RT5659_ASRC_13 0x0099 |
166 | #define RT5659_REC_M1_M2_GAIN_CTRL 0x009a |
167 | #define RT5659_CLASSD_CTRL_1 0x00a0 |
168 | #define RT5659_CLASSD_CTRL_2 0x00a1 |
169 | |
170 | /* Function - Digital */ |
171 | #define RT5659_ADC_EQ_CTRL_1 0x00ae |
172 | #define RT5659_ADC_EQ_CTRL_2 0x00af |
173 | #define RT5659_DAC_EQ_CTRL_1 0x00b0 |
174 | #define RT5659_DAC_EQ_CTRL_2 0x00b1 |
175 | #define RT5659_DAC_EQ_CTRL_3 0x00b2 |
176 | |
177 | #define RT5659_IRQ_CTRL_1 0x00b6 |
178 | #define RT5659_IRQ_CTRL_2 0x00b7 |
179 | #define RT5659_IRQ_CTRL_3 0x00b8 |
180 | #define RT5659_IRQ_CTRL_4 0x00ba |
181 | #define RT5659_IRQ_CTRL_5 0x00bb |
182 | #define RT5659_IRQ_CTRL_6 0x00bc |
183 | #define RT5659_INT_ST_1 0x00be |
184 | #define RT5659_INT_ST_2 0x00bf |
185 | #define RT5659_GPIO_CTRL_1 0x00c0 |
186 | #define RT5659_GPIO_CTRL_2 0x00c1 |
187 | #define RT5659_GPIO_CTRL_3 0x00c2 |
188 | #define RT5659_GPIO_CTRL_4 0x00c3 |
189 | #define RT5659_GPIO_CTRL_5 0x00c4 |
190 | #define RT5659_GPIO_STA 0x00c5 |
191 | #define RT5659_SINE_GEN_CTRL_1 0x00cb |
192 | #define RT5659_SINE_GEN_CTRL_2 0x00cc |
193 | #define RT5659_SINE_GEN_CTRL_3 0x00cd |
194 | #define RT5659_HP_AMP_DET_CTRL_1 0x00d6 |
195 | #define RT5659_HP_AMP_DET_CTRL_2 0x00d7 |
196 | #define RT5659_SV_ZCD_1 0x00d9 |
197 | #define RT5659_SV_ZCD_2 0x00da |
198 | #define RT5659_IL_CMD_1 0x00db |
199 | #define RT5659_IL_CMD_2 0x00dc |
200 | #define RT5659_IL_CMD_3 0x00dd |
201 | #define RT5659_IL_CMD_4 0x00de |
202 | #define RT5659_4BTN_IL_CMD_1 0x00df |
203 | #define RT5659_4BTN_IL_CMD_2 0x00e0 |
204 | #define RT5659_4BTN_IL_CMD_3 0x00e1 |
205 | #define RT5659_PSV_IL_CMD_1 0x00e4 |
206 | #define RT5659_PSV_IL_CMD_2 0x00e5 |
207 | |
208 | #define RT5659_ADC_STO1_HP_CTRL_1 0x00ea |
209 | #define RT5659_ADC_STO1_HP_CTRL_2 0x00eb |
210 | #define RT5659_ADC_MONO_HP_CTRL_1 0x00ec |
211 | #define RT5659_ADC_MONO_HP_CTRL_2 0x00ed |
212 | #define RT5659_AJD1_CTRL 0x00f0 |
213 | #define RT5659_AJD2_AJD3_CTRL 0x00f1 |
214 | #define RT5659_JD1_THD 0x00f2 |
215 | #define RT5659_JD2_THD 0x00f3 |
216 | #define RT5659_JD3_THD 0x00f4 |
217 | #define RT5659_JD_CTRL_1 0x00f6 |
218 | #define RT5659_JD_CTRL_2 0x00f7 |
219 | #define RT5659_JD_CTRL_3 0x00f8 |
220 | #define RT5659_JD_CTRL_4 0x00f9 |
221 | /* General Control */ |
222 | #define RT5659_DIG_MISC 0x00fa |
223 | #define RT5659_DUMMY_2 0x00fb |
224 | #define RT5659_DUMMY_3 0x00fc |
225 | |
226 | #define RT5659_DAC_ADC_DIG_VOL 0x0100 |
227 | #define RT5659_BIAS_CUR_CTRL_1 0x010a |
228 | #define RT5659_BIAS_CUR_CTRL_2 0x010b |
229 | #define RT5659_BIAS_CUR_CTRL_3 0x010c |
230 | #define RT5659_BIAS_CUR_CTRL_4 0x010d |
231 | #define RT5659_BIAS_CUR_CTRL_5 0x010e |
232 | #define RT5659_BIAS_CUR_CTRL_6 0x010f |
233 | #define RT5659_BIAS_CUR_CTRL_7 0x0110 |
234 | #define RT5659_BIAS_CUR_CTRL_8 0x0111 |
235 | #define RT5659_BIAS_CUR_CTRL_9 0x0112 |
236 | #define RT5659_BIAS_CUR_CTRL_10 0x0113 |
237 | #define RT5659_MEMORY_TEST 0x0116 |
238 | #define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117 |
239 | #define RT5659_CLASSD_0 0x011a |
240 | #define RT5659_CLASSD_1 0x011b |
241 | #define RT5659_CLASSD_2 0x011c |
242 | #define RT5659_CLASSD_3 0x011d |
243 | #define RT5659_CLASSD_4 0x011e |
244 | #define RT5659_CLASSD_5 0x011f |
245 | #define RT5659_CLASSD_6 0x0120 |
246 | #define RT5659_CLASSD_7 0x0121 |
247 | #define RT5659_CLASSD_8 0x0122 |
248 | #define RT5659_CLASSD_9 0x0123 |
249 | #define RT5659_CLASSD_10 0x0124 |
250 | #define RT5659_CHARGE_PUMP_1 0x0125 |
251 | #define RT5659_CHARGE_PUMP_2 0x0126 |
252 | #define RT5659_DIG_IN_CTRL_1 0x0132 |
253 | #define RT5659_DIG_IN_CTRL_2 0x0133 |
254 | #define RT5659_PAD_DRIVING_CTRL 0x0137 |
255 | #define RT5659_SOFT_RAMP_DEPOP 0x0138 |
256 | #define RT5659_PLL 0x0139 |
257 | #define RT5659_CHOP_DAC 0x013a |
258 | #define RT5659_CHOP_ADC 0x013b |
259 | #define RT5659_CALIB_ADC_CTRL 0x013c |
260 | #define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e |
261 | #define RT5659_VOL_TEST 0x013f |
262 | #define RT5659_TEST_MODE_CTRL_1 0x0145 |
263 | #define RT5659_TEST_MODE_CTRL_2 0x0146 |
264 | #define RT5659_TEST_MODE_CTRL_3 0x0147 |
265 | #define RT5659_TEST_MODE_CTRL_4 0x0148 |
266 | #define RT5659_BASSBACK_CTRL 0x0150 |
267 | #define RT5659_MP3_PLUS_CTRL_1 0x0151 |
268 | #define RT5659_MP3_PLUS_CTRL_2 0x0152 |
269 | #define RT5659_MP3_HPF_A1 0x0153 |
270 | #define RT5659_MP3_HPF_A2 0x0154 |
271 | #define RT5659_MP3_HPF_H0 0x0155 |
272 | #define RT5659_MP3_LPF_H0 0x0156 |
273 | #define RT5659_3D_SPK_CTRL 0x0157 |
274 | #define RT5659_3D_SPK_COEF_1 0x0158 |
275 | #define RT5659_3D_SPK_COEF_2 0x0159 |
276 | #define RT5659_3D_SPK_COEF_3 0x015a |
277 | #define RT5659_3D_SPK_COEF_4 0x015b |
278 | #define RT5659_3D_SPK_COEF_5 0x015c |
279 | #define RT5659_3D_SPK_COEF_6 0x015d |
280 | #define RT5659_3D_SPK_COEF_7 0x015e |
281 | #define RT5659_STO_NG2_CTRL_1 0x0160 |
282 | #define RT5659_STO_NG2_CTRL_2 0x0161 |
283 | #define RT5659_STO_NG2_CTRL_3 0x0162 |
284 | #define RT5659_STO_NG2_CTRL_4 0x0163 |
285 | #define RT5659_STO_NG2_CTRL_5 0x0164 |
286 | #define RT5659_STO_NG2_CTRL_6 0x0165 |
287 | #define RT5659_STO_NG2_CTRL_7 0x0166 |
288 | #define RT5659_STO_NG2_CTRL_8 0x0167 |
289 | #define RT5659_MONO_NG2_CTRL_1 0x0170 |
290 | #define RT5659_MONO_NG2_CTRL_2 0x0171 |
291 | #define RT5659_MONO_NG2_CTRL_3 0x0172 |
292 | #define RT5659_MONO_NG2_CTRL_4 0x0173 |
293 | #define RT5659_MONO_NG2_CTRL_5 0x0174 |
294 | #define RT5659_MONO_NG2_CTRL_6 0x0175 |
295 | #define RT5659_MID_HP_AMP_DET 0x0190 |
296 | #define RT5659_LOW_HP_AMP_DET 0x0191 |
297 | #define RT5659_LDO_CTRL 0x0192 |
298 | #define RT5659_HP_DECROSS_CTRL_1 0x01b0 |
299 | #define RT5659_HP_DECROSS_CTRL_2 0x01b1 |
300 | #define RT5659_HP_DECROSS_CTRL_3 0x01b2 |
301 | #define RT5659_HP_DECROSS_CTRL_4 0x01b3 |
302 | #define RT5659_HP_IMP_SENS_CTRL_1 0x01c0 |
303 | #define RT5659_HP_IMP_SENS_CTRL_2 0x01c1 |
304 | #define RT5659_HP_IMP_SENS_CTRL_3 0x01c2 |
305 | #define RT5659_HP_IMP_SENS_CTRL_4 0x01c3 |
306 | #define RT5659_HP_IMP_SENS_MAP_1 0x01c7 |
307 | #define RT5659_HP_IMP_SENS_MAP_2 0x01c8 |
308 | #define RT5659_HP_IMP_SENS_MAP_3 0x01c9 |
309 | #define RT5659_HP_IMP_SENS_MAP_4 0x01ca |
310 | #define RT5659_HP_IMP_SENS_MAP_5 0x01cb |
311 | #define RT5659_HP_IMP_SENS_MAP_6 0x01cc |
312 | #define RT5659_HP_IMP_SENS_MAP_7 0x01cd |
313 | #define RT5659_HP_IMP_SENS_MAP_8 0x01ce |
314 | #define RT5659_HP_LOGIC_CTRL_1 0x01da |
315 | #define RT5659_HP_LOGIC_CTRL_2 0x01db |
316 | #define RT5659_HP_CALIB_CTRL_1 0x01de |
317 | #define RT5659_HP_CALIB_CTRL_2 0x01df |
318 | #define RT5659_HP_CALIB_CTRL_3 0x01e0 |
319 | #define RT5659_HP_CALIB_CTRL_4 0x01e1 |
320 | #define RT5659_HP_CALIB_CTRL_5 0x01e2 |
321 | #define RT5659_HP_CALIB_CTRL_6 0x01e3 |
322 | #define RT5659_HP_CALIB_CTRL_7 0x01e4 |
323 | #define RT5659_HP_CALIB_CTRL_9 0x01e6 |
324 | #define RT5659_HP_CALIB_CTRL_10 0x01e7 |
325 | #define RT5659_HP_CALIB_CTRL_11 0x01e8 |
326 | #define RT5659_HP_CALIB_STA_1 0x01ea |
327 | #define RT5659_HP_CALIB_STA_2 0x01eb |
328 | #define RT5659_HP_CALIB_STA_3 0x01ec |
329 | #define RT5659_HP_CALIB_STA_4 0x01ed |
330 | #define RT5659_HP_CALIB_STA_5 0x01ee |
331 | #define RT5659_HP_CALIB_STA_6 0x01ef |
332 | #define RT5659_HP_CALIB_STA_7 0x01f0 |
333 | #define RT5659_HP_CALIB_STA_8 0x01f1 |
334 | #define RT5659_HP_CALIB_STA_9 0x01f2 |
335 | #define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6 |
336 | #define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7 |
337 | #define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8 |
338 | #define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9 |
339 | #define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa |
340 | #define RT5659_MONO_AMP_CALIB_STA_1 0x01fb |
341 | #define RT5659_MONO_AMP_CALIB_STA_2 0x01fc |
342 | #define RT5659_MONO_AMP_CALIB_STA_3 0x01fd |
343 | #define RT5659_MONO_AMP_CALIB_STA_4 0x01fe |
344 | #define RT5659_SPK_PWR_LMT_CTRL_1 0x0200 |
345 | #define RT5659_SPK_PWR_LMT_CTRL_2 0x0201 |
346 | #define RT5659_SPK_PWR_LMT_CTRL_3 0x0202 |
347 | #define RT5659_SPK_PWR_LMT_STA_1 0x0203 |
348 | #define RT5659_SPK_PWR_LMT_STA_2 0x0204 |
349 | #define RT5659_SPK_PWR_LMT_STA_3 0x0205 |
350 | #define RT5659_SPK_PWR_LMT_STA_4 0x0206 |
351 | #define RT5659_SPK_PWR_LMT_STA_5 0x0207 |
352 | #define RT5659_SPK_PWR_LMT_STA_6 0x0208 |
353 | #define RT5659_FLEX_SPK_BST_CTRL_1 0x0256 |
354 | #define RT5659_FLEX_SPK_BST_CTRL_2 0x0257 |
355 | #define RT5659_FLEX_SPK_BST_CTRL_3 0x0258 |
356 | #define RT5659_FLEX_SPK_BST_CTRL_4 0x0259 |
357 | #define RT5659_SPK_EX_LMT_CTRL_1 0x025a |
358 | #define RT5659_SPK_EX_LMT_CTRL_2 0x025b |
359 | #define RT5659_SPK_EX_LMT_CTRL_3 0x025c |
360 | #define RT5659_SPK_EX_LMT_CTRL_4 0x025d |
361 | #define RT5659_SPK_EX_LMT_CTRL_5 0x025e |
362 | #define RT5659_SPK_EX_LMT_CTRL_6 0x025f |
363 | #define RT5659_SPK_EX_LMT_CTRL_7 0x0260 |
364 | #define RT5659_ADJ_HPF_CTRL_1 0x0261 |
365 | #define RT5659_ADJ_HPF_CTRL_2 0x0262 |
366 | #define RT5659_SPK_DC_CAILB_CTRL_1 0x0265 |
367 | #define RT5659_SPK_DC_CAILB_CTRL_2 0x0266 |
368 | #define RT5659_SPK_DC_CAILB_CTRL_3 0x0267 |
369 | #define RT5659_SPK_DC_CAILB_CTRL_4 0x0268 |
370 | #define RT5659_SPK_DC_CAILB_CTRL_5 0x0269 |
371 | #define RT5659_SPK_DC_CAILB_STA_1 0x026a |
372 | #define RT5659_SPK_DC_CAILB_STA_2 0x026b |
373 | #define RT5659_SPK_DC_CAILB_STA_3 0x026c |
374 | #define RT5659_SPK_DC_CAILB_STA_4 0x026d |
375 | #define RT5659_SPK_DC_CAILB_STA_5 0x026e |
376 | #define RT5659_SPK_DC_CAILB_STA_6 0x026f |
377 | #define RT5659_SPK_DC_CAILB_STA_7 0x0270 |
378 | #define RT5659_SPK_DC_CAILB_STA_8 0x0271 |
379 | #define RT5659_SPK_DC_CAILB_STA_9 0x0272 |
380 | #define RT5659_SPK_DC_CAILB_STA_10 0x0273 |
381 | #define RT5659_SPK_VDD_STA_1 0x0280 |
382 | #define RT5659_SPK_VDD_STA_2 0x0281 |
383 | #define RT5659_SPK_DC_DET_CTRL_1 0x0282 |
384 | #define RT5659_SPK_DC_DET_CTRL_2 0x0283 |
385 | #define RT5659_SPK_DC_DET_CTRL_3 0x0284 |
386 | #define RT5659_PURE_DC_DET_CTRL_1 0x0290 |
387 | #define RT5659_PURE_DC_DET_CTRL_2 0x0291 |
388 | #define RT5659_DUMMY_4 0x02fa |
389 | #define RT5659_DUMMY_5 0x02fb |
390 | #define RT5659_DUMMY_6 0x02fc |
391 | #define RT5659_DRC1_CTRL_1 0x0300 |
392 | #define RT5659_DRC1_CTRL_2 0x0301 |
393 | #define RT5659_DRC1_CTRL_3 0x0302 |
394 | #define RT5659_DRC1_CTRL_4 0x0303 |
395 | #define RT5659_DRC1_CTRL_5 0x0304 |
396 | #define RT5659_DRC1_CTRL_6 0x0305 |
397 | #define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306 |
398 | #define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307 |
399 | #define RT5659_DRC2_CTRL_1 0x0308 |
400 | #define RT5659_DRC2_CTRL_2 0x0309 |
401 | #define RT5659_DRC2_CTRL_3 0x030a |
402 | #define RT5659_DRC2_CTRL_4 0x030b |
403 | #define RT5659_DRC2_CTRL_5 0x030c |
404 | #define RT5659_DRC2_CTRL_6 0x030d |
405 | #define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e |
406 | #define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f |
407 | #define RT5659_DRC1_PRIV_1 0x0310 |
408 | #define RT5659_DRC1_PRIV_2 0x0311 |
409 | #define RT5659_DRC1_PRIV_3 0x0312 |
410 | #define RT5659_DRC1_PRIV_4 0x0313 |
411 | #define RT5659_DRC1_PRIV_5 0x0314 |
412 | #define RT5659_DRC1_PRIV_6 0x0315 |
413 | #define RT5659_DRC1_PRIV_7 0x0316 |
414 | #define RT5659_DRC2_PRIV_1 0x0317 |
415 | #define RT5659_DRC2_PRIV_2 0x0318 |
416 | #define RT5659_DRC2_PRIV_3 0x0319 |
417 | #define RT5659_DRC2_PRIV_4 0x031a |
418 | #define RT5659_DRC2_PRIV_5 0x031b |
419 | #define RT5659_DRC2_PRIV_6 0x031c |
420 | #define RT5659_DRC2_PRIV_7 0x031d |
421 | #define RT5659_MULTI_DRC_CTRL 0x0320 |
422 | #define RT5659_CROSS_OVER_1 0x0321 |
423 | #define RT5659_CROSS_OVER_2 0x0322 |
424 | #define RT5659_CROSS_OVER_3 0x0323 |
425 | #define RT5659_CROSS_OVER_4 0x0324 |
426 | #define RT5659_CROSS_OVER_5 0x0325 |
427 | #define RT5659_CROSS_OVER_6 0x0326 |
428 | #define RT5659_CROSS_OVER_7 0x0327 |
429 | #define RT5659_CROSS_OVER_8 0x0328 |
430 | #define RT5659_CROSS_OVER_9 0x0329 |
431 | #define RT5659_CROSS_OVER_10 0x032a |
432 | #define RT5659_ALC_PGA_CTRL_1 0x0330 |
433 | #define RT5659_ALC_PGA_CTRL_2 0x0331 |
434 | #define RT5659_ALC_PGA_CTRL_3 0x0332 |
435 | #define RT5659_ALC_PGA_CTRL_4 0x0333 |
436 | #define RT5659_ALC_PGA_CTRL_5 0x0334 |
437 | #define RT5659_ALC_PGA_CTRL_6 0x0335 |
438 | #define RT5659_ALC_PGA_CTRL_7 0x0336 |
439 | #define RT5659_ALC_PGA_CTRL_8 0x0337 |
440 | #define RT5659_ALC_PGA_STA_1 0x0338 |
441 | #define RT5659_ALC_PGA_STA_2 0x0339 |
442 | #define RT5659_ALC_PGA_STA_3 0x033a |
443 | #define RT5659_DAC_L_EQ_PRE_VOL 0x0340 |
444 | #define RT5659_DAC_R_EQ_PRE_VOL 0x0341 |
445 | #define RT5659_DAC_L_EQ_POST_VOL 0x0342 |
446 | #define RT5659_DAC_R_EQ_POST_VOL 0x0343 |
447 | #define RT5659_DAC_L_EQ_LPF1_A1 0x0344 |
448 | #define RT5659_DAC_L_EQ_LPF1_H0 0x0345 |
449 | #define RT5659_DAC_R_EQ_LPF1_A1 0x0346 |
450 | #define RT5659_DAC_R_EQ_LPF1_H0 0x0347 |
451 | #define RT5659_DAC_L_EQ_BPF2_A1 0x0348 |
452 | #define RT5659_DAC_L_EQ_BPF2_A2 0x0349 |
453 | #define RT5659_DAC_L_EQ_BPF2_H0 0x034a |
454 | #define RT5659_DAC_R_EQ_BPF2_A1 0x034b |
455 | #define RT5659_DAC_R_EQ_BPF2_A2 0x034c |
456 | #define RT5659_DAC_R_EQ_BPF2_H0 0x034d |
457 | #define RT5659_DAC_L_EQ_BPF3_A1 0x034e |
458 | #define RT5659_DAC_L_EQ_BPF3_A2 0x034f |
459 | #define RT5659_DAC_L_EQ_BPF3_H0 0x0350 |
460 | #define RT5659_DAC_R_EQ_BPF3_A1 0x0351 |
461 | #define RT5659_DAC_R_EQ_BPF3_A2 0x0352 |
462 | #define RT5659_DAC_R_EQ_BPF3_H0 0x0353 |
463 | #define RT5659_DAC_L_EQ_BPF4_A1 0x0354 |
464 | #define RT5659_DAC_L_EQ_BPF4_A2 0x0355 |
465 | #define RT5659_DAC_L_EQ_BPF4_H0 0x0356 |
466 | #define RT5659_DAC_R_EQ_BPF4_A1 0x0357 |
467 | #define RT5659_DAC_R_EQ_BPF4_A2 0x0358 |
468 | #define RT5659_DAC_R_EQ_BPF4_H0 0x0359 |
469 | #define RT5659_DAC_L_EQ_HPF1_A1 0x035a |
470 | #define RT5659_DAC_L_EQ_HPF1_H0 0x035b |
471 | #define RT5659_DAC_R_EQ_HPF1_A1 0x035c |
472 | #define RT5659_DAC_R_EQ_HPF1_H0 0x035d |
473 | #define RT5659_DAC_L_EQ_HPF2_A1 0x035e |
474 | #define RT5659_DAC_L_EQ_HPF2_A2 0x035f |
475 | #define RT5659_DAC_L_EQ_HPF2_H0 0x0360 |
476 | #define RT5659_DAC_R_EQ_HPF2_A1 0x0361 |
477 | #define RT5659_DAC_R_EQ_HPF2_A2 0x0362 |
478 | #define RT5659_DAC_R_EQ_HPF2_H0 0x0363 |
479 | #define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364 |
480 | #define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365 |
481 | #define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366 |
482 | #define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367 |
483 | #define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368 |
484 | #define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369 |
485 | #define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a |
486 | #define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b |
487 | #define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c |
488 | #define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d |
489 | #define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e |
490 | #define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f |
491 | #define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370 |
492 | #define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371 |
493 | #define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372 |
494 | #define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373 |
495 | #define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374 |
496 | #define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375 |
497 | #define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376 |
498 | #define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377 |
499 | #define RT5659_ADC_L_EQ_LPF1_A1 0x03d0 |
500 | #define RT5659_ADC_R_EQ_LPF1_A1 0x03d1 |
501 | #define RT5659_ADC_L_EQ_LPF1_H0 0x03d2 |
502 | #define RT5659_ADC_R_EQ_LPF1_H0 0x03d3 |
503 | #define RT5659_ADC_L_EQ_BPF1_A1 0x03d4 |
504 | #define RT5659_ADC_R_EQ_BPF1_A1 0x03d5 |
505 | #define RT5659_ADC_L_EQ_BPF1_A2 0x03d6 |
506 | #define RT5659_ADC_R_EQ_BPF1_A2 0x03d7 |
507 | #define RT5659_ADC_L_EQ_BPF1_H0 0x03d8 |
508 | #define RT5659_ADC_R_EQ_BPF1_H0 0x03d9 |
509 | #define RT5659_ADC_L_EQ_BPF2_A1 0x03da |
510 | #define RT5659_ADC_R_EQ_BPF2_A1 0x03db |
511 | #define RT5659_ADC_L_EQ_BPF2_A2 0x03dc |
512 | #define RT5659_ADC_R_EQ_BPF2_A2 0x03dd |
513 | #define RT5659_ADC_L_EQ_BPF2_H0 0x03de |
514 | #define RT5659_ADC_R_EQ_BPF2_H0 0x03df |
515 | #define RT5659_ADC_L_EQ_BPF3_A1 0x03e0 |
516 | #define RT5659_ADC_R_EQ_BPF3_A1 0x03e1 |
517 | #define RT5659_ADC_L_EQ_BPF3_A2 0x03e2 |
518 | #define RT5659_ADC_R_EQ_BPF3_A2 0x03e3 |
519 | #define RT5659_ADC_L_EQ_BPF3_H0 0x03e4 |
520 | #define RT5659_ADC_R_EQ_BPF3_H0 0x03e5 |
521 | #define RT5659_ADC_L_EQ_BPF4_A1 0x03e6 |
522 | #define RT5659_ADC_R_EQ_BPF4_A1 0x03e7 |
523 | #define RT5659_ADC_L_EQ_BPF4_A2 0x03e8 |
524 | #define RT5659_ADC_R_EQ_BPF4_A2 0x03e9 |
525 | #define RT5659_ADC_L_EQ_BPF4_H0 0x03ea |
526 | #define RT5659_ADC_R_EQ_BPF4_H0 0x03eb |
527 | #define RT5659_ADC_L_EQ_HPF1_A1 0x03ec |
528 | #define RT5659_ADC_R_EQ_HPF1_A1 0x03ed |
529 | #define RT5659_ADC_L_EQ_HPF1_H0 0x03ee |
530 | #define RT5659_ADC_R_EQ_HPF1_H0 0x03ef |
531 | #define RT5659_ADC_L_EQ_PRE_VOL 0x03f0 |
532 | #define RT5659_ADC_R_EQ_PRE_VOL 0x03f1 |
533 | #define RT5659_ADC_L_EQ_POST_VOL 0x03f2 |
534 | #define RT5659_ADC_R_EQ_POST_VOL 0x03f3 |
535 | |
536 | |
537 | |
538 | /* global definition */ |
539 | #define RT5659_L_MUTE (0x1 << 15) |
540 | #define RT5659_L_MUTE_SFT 15 |
541 | #define RT5659_VOL_L_MUTE (0x1 << 14) |
542 | #define RT5659_VOL_L_SFT 14 |
543 | #define RT5659_R_MUTE (0x1 << 7) |
544 | #define RT5659_R_MUTE_SFT 7 |
545 | #define RT5659_VOL_R_MUTE (0x1 << 6) |
546 | #define RT5659_VOL_R_SFT 6 |
547 | #define RT5659_L_VOL_MASK (0x3f << 8) |
548 | #define RT5659_L_VOL_SFT 8 |
549 | #define RT5659_R_VOL_MASK (0x3f) |
550 | #define RT5659_R_VOL_SFT 0 |
551 | |
552 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ |
553 | #define RT5659_G_HP (0x1f << 8) |
554 | #define RT5659_G_HP_SFT 8 |
555 | #define RT5659_G_STO_DA_DMIX (0x1f) |
556 | #define RT5659_G_STO_DA_SFT 0 |
557 | |
558 | /* IN1/IN2 Control (0x000c) */ |
559 | #define RT5659_IN1_DF_MASK (0x1 << 15) |
560 | #define RT5659_IN1_DF 15 |
561 | #define RT5659_BST1_MASK (0x7f << 8) |
562 | #define RT5659_BST1_SFT 8 |
563 | #define RT5659_BST2_MASK (0x7f) |
564 | #define RT5659_BST2_SFT 0 |
565 | |
566 | /* IN3/IN4 Control (0x000d) */ |
567 | #define RT5659_IN3_DF_MASK (0x1 << 15) |
568 | #define RT5659_IN3_DF 15 |
569 | #define RT5659_BST3_MASK (0x7f << 8) |
570 | #define RT5659_BST3_SFT 8 |
571 | #define RT5659_IN4_DF_MASK (0x1 << 7) |
572 | #define RT5659_IN4_DF 7 |
573 | #define RT5659_BST4_MASK (0x7f) |
574 | #define RT5659_BST4_SFT 0 |
575 | |
576 | /* INL and INR Volume Control (0x000f) */ |
577 | #define RT5659_INL_VOL_MASK (0x1f << 8) |
578 | #define RT5659_INL_VOL_SFT 8 |
579 | #define RT5659_INR_VOL_MASK (0x1f) |
580 | #define RT5659_INR_VOL_SFT 0 |
581 | |
582 | /* Embeeded Jack and Type Detection Control 1 (0x0010) */ |
583 | #define RT5659_EMB_JD_EN (0x1 << 15) |
584 | #define RT5659_EMB_JD_EN_SFT 15 |
585 | #define RT5659_JD_MODE (0x1 << 13) |
586 | #define RT5659_JD_MODE_SFT 13 |
587 | #define RT5659_EXT_JD_EN (0x1 << 11) |
588 | #define RT5659_EXT_JD_EN_SFT 11 |
589 | #define RT5659_EXT_JD_DIG (0x1 << 9) |
590 | |
591 | /* Embeeded Jack and Type Detection Control 2 (0x0011) */ |
592 | #define RT5659_EXT_JD_SRC (0x7 << 4) |
593 | #define RT5659_EXT_JD_SRC_SFT 4 |
594 | #define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) |
595 | #define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) |
596 | #define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4) |
597 | #define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4) |
598 | #define RT5659_EXT_JD_SRC_JD2 (0x4 << 4) |
599 | #define RT5659_EXT_JD_SRC_JD3 (0x5 << 4) |
600 | #define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4) |
601 | |
602 | /* Slience Detection Control (0x0015) */ |
603 | #define RT5659_SIL_DET_MASK (0x1 << 15) |
604 | #define RT5659_SIL_DET_DIS (0x0 << 15) |
605 | #define RT5659_SIL_DET_EN (0x1 << 15) |
606 | |
607 | /* Sidetone Control (0x0018) */ |
608 | #define RT5659_ST_SEL_MASK (0x7 << 9) |
609 | #define RT5659_ST_SEL_SFT 9 |
610 | #define RT5659_ST_EN (0x1 << 6) |
611 | #define RT5659_ST_EN_SFT 6 |
612 | |
613 | /* DAC1 Digital Volume (0x0019) */ |
614 | #define RT5659_DAC_L1_VOL_MASK (0xff << 8) |
615 | #define RT5659_DAC_L1_VOL_SFT 8 |
616 | #define RT5659_DAC_R1_VOL_MASK (0xff) |
617 | #define RT5659_DAC_R1_VOL_SFT 0 |
618 | |
619 | /* DAC2 Digital Volume (0x001a) */ |
620 | #define RT5659_DAC_L2_VOL_MASK (0xff << 8) |
621 | #define RT5659_DAC_L2_VOL_SFT 8 |
622 | #define RT5659_DAC_R2_VOL_MASK (0xff) |
623 | #define RT5659_DAC_R2_VOL_SFT 0 |
624 | |
625 | /* DAC2 Control (0x001b) */ |
626 | #define RT5659_M_DAC2_L_VOL (0x1 << 13) |
627 | #define RT5659_M_DAC2_L_VOL_SFT 13 |
628 | #define RT5659_M_DAC2_R_VOL (0x1 << 12) |
629 | #define RT5659_M_DAC2_R_VOL_SFT 12 |
630 | #define RT5659_DAC_L2_SEL_MASK (0x7 << 4) |
631 | #define RT5659_DAC_L2_SEL_SFT 4 |
632 | #define RT5659_DAC_R2_SEL_MASK (0x7 << 0) |
633 | #define RT5659_DAC_R2_SEL_SFT 0 |
634 | |
635 | /* ADC Digital Volume Control (0x001c) */ |
636 | #define RT5659_ADC_L_VOL_MASK (0x7f << 8) |
637 | #define RT5659_ADC_L_VOL_SFT 8 |
638 | #define RT5659_ADC_R_VOL_MASK (0x7f) |
639 | #define RT5659_ADC_R_VOL_SFT 0 |
640 | |
641 | /* Mono ADC Digital Volume Control (0x001d) */ |
642 | #define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8) |
643 | #define RT5659_MONO_ADC_L_VOL_SFT 8 |
644 | #define RT5659_MONO_ADC_R_VOL_MASK (0x7f) |
645 | #define RT5659_MONO_ADC_R_VOL_SFT 0 |
646 | |
647 | /* Stereo1 ADC Boost Gain Control (0x001f) */ |
648 | #define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14) |
649 | #define RT5659_STO1_ADC_L_BST_SFT 14 |
650 | #define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12) |
651 | #define RT5659_STO1_ADC_R_BST_SFT 12 |
652 | |
653 | /* Mono ADC Boost Gain Control (0x0020) */ |
654 | #define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14) |
655 | #define RT5659_MONO_ADC_L_BST_SFT 14 |
656 | #define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12) |
657 | #define RT5659_MONO_ADC_R_BST_SFT 12 |
658 | |
659 | /* Stereo1 ADC Boost Gain Control (0x001f) */ |
660 | #define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14) |
661 | #define RT5659_STO2_ADC_L_BST_SFT 14 |
662 | #define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12) |
663 | #define RT5659_STO2_ADC_R_BST_SFT 12 |
664 | |
665 | /* Stereo ADC Mixer Control (0x0026) */ |
666 | #define RT5659_M_STO1_ADC_L1 (0x1 << 15) |
667 | #define RT5659_M_STO1_ADC_L1_SFT 15 |
668 | #define RT5659_M_STO1_ADC_L2 (0x1 << 14) |
669 | #define RT5659_M_STO1_ADC_L2_SFT 14 |
670 | #define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13) |
671 | #define RT5659_STO1_ADC1_SRC_SFT 13 |
672 | #define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13) |
673 | #define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13) |
674 | #define RT5659_STO1_ADC_SRC_MASK (0x1 << 12) |
675 | #define RT5659_STO1_ADC_SRC_SFT 12 |
676 | #define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12) |
677 | #define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12) |
678 | #define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11) |
679 | #define RT5659_STO1_ADC2_SRC_SFT 11 |
680 | #define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8) |
681 | #define RT5659_STO1_DMIC_SRC_SFT 8 |
682 | #define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8) |
683 | #define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8) |
684 | #define RT5659_M_STO1_ADC_R1 (0x1 << 6) |
685 | #define RT5659_M_STO1_ADC_R1_SFT 6 |
686 | #define RT5659_M_STO1_ADC_R2 (0x1 << 5) |
687 | #define RT5659_M_STO1_ADC_R2_SFT 5 |
688 | |
689 | /* Mono1 ADC Mixer control (0x0027) */ |
690 | #define RT5659_M_MONO_ADC_L1 (0x1 << 15) |
691 | #define RT5659_M_MONO_ADC_L1_SFT 15 |
692 | #define RT5659_M_MONO_ADC_L2 (0x1 << 14) |
693 | #define RT5659_M_MONO_ADC_L2_SFT 14 |
694 | #define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12) |
695 | #define RT5659_MONO_ADC_L2_SRC_SFT 12 |
696 | #define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11) |
697 | #define RT5659_MONO_ADC_L1_SRC_SFT 11 |
698 | #define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9) |
699 | #define RT5659_MONO_ADC_L_SRC_SFT 9 |
700 | #define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8) |
701 | #define RT5659_MONO_DMIC_L_SRC_SFT 8 |
702 | #define RT5659_M_MONO_ADC_R1 (0x1 << 7) |
703 | #define RT5659_M_MONO_ADC_R1_SFT 7 |
704 | #define RT5659_M_MONO_ADC_R2 (0x1 << 6) |
705 | #define RT5659_M_MONO_ADC_R2_SFT 6 |
706 | #define RT5659_STO2_ADC_SRC_MASK (0x1 << 5) |
707 | #define RT5659_STO2_ADC_SRC_SFT 5 |
708 | #define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4) |
709 | #define RT5659_MONO_ADC_R2_SRC_SFT 4 |
710 | #define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3) |
711 | #define RT5659_MONO_ADC_R1_SRC_SFT 3 |
712 | #define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1) |
713 | #define RT5659_MONO_ADC_R_SRC_SFT 1 |
714 | #define RT5659_MONO_DMIC_R_SRC_MASK 0x1 |
715 | #define RT5659_MONO_DMIC_R_SRC_SFT 0 |
716 | |
717 | /* ADC Mixer to DAC Mixer Control (0x0029) */ |
718 | #define RT5659_M_ADCMIX_L (0x1 << 15) |
719 | #define RT5659_M_ADCMIX_L_SFT 15 |
720 | #define RT5659_M_DAC1_L (0x1 << 14) |
721 | #define RT5659_M_DAC1_L_SFT 14 |
722 | #define RT5659_DAC1_R_SEL_MASK (0x3 << 10) |
723 | #define RT5659_DAC1_R_SEL_SFT 10 |
724 | #define RT5659_DAC1_R_SEL_IF1 (0x0 << 10) |
725 | #define RT5659_DAC1_R_SEL_IF2 (0x1 << 10) |
726 | #define RT5659_DAC1_R_SEL_IF3 (0x2 << 10) |
727 | #define RT5659_DAC1_L_SEL_MASK (0x3 << 8) |
728 | #define RT5659_DAC1_L_SEL_SFT 8 |
729 | #define RT5659_DAC1_L_SEL_IF1 (0x0 << 8) |
730 | #define RT5659_DAC1_L_SEL_IF2 (0x1 << 8) |
731 | #define RT5659_DAC1_L_SEL_IF3 (0x2 << 8) |
732 | #define RT5659_M_ADCMIX_R (0x1 << 7) |
733 | #define RT5659_M_ADCMIX_R_SFT 7 |
734 | #define RT5659_M_DAC1_R (0x1 << 6) |
735 | #define RT5659_M_DAC1_R_SFT 6 |
736 | |
737 | /* Stereo DAC Mixer Control (0x002a) */ |
738 | #define RT5659_M_DAC_L1_STO_L (0x1 << 15) |
739 | #define RT5659_M_DAC_L1_STO_L_SFT 15 |
740 | #define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14) |
741 | #define RT5659_G_DAC_L1_STO_L_SFT 14 |
742 | #define RT5659_M_DAC_R1_STO_L (0x1 << 13) |
743 | #define RT5659_M_DAC_R1_STO_L_SFT 13 |
744 | #define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12) |
745 | #define RT5659_G_DAC_R1_STO_L_SFT 12 |
746 | #define RT5659_M_DAC_L2_STO_L (0x1 << 11) |
747 | #define RT5659_M_DAC_L2_STO_L_SFT 11 |
748 | #define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10) |
749 | #define RT5659_G_DAC_L2_STO_L_SFT 10 |
750 | #define RT5659_M_DAC_R2_STO_L (0x1 << 9) |
751 | #define RT5659_M_DAC_R2_STO_L_SFT 9 |
752 | #define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8) |
753 | #define RT5659_G_DAC_R2_STO_L_SFT 8 |
754 | #define RT5659_M_DAC_L1_STO_R (0x1 << 7) |
755 | #define RT5659_M_DAC_L1_STO_R_SFT 7 |
756 | #define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6) |
757 | #define RT5659_G_DAC_L1_STO_R_SFT 6 |
758 | #define RT5659_M_DAC_R1_STO_R (0x1 << 5) |
759 | #define RT5659_M_DAC_R1_STO_R_SFT 5 |
760 | #define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4) |
761 | #define RT5659_G_DAC_R1_STO_R_SFT 4 |
762 | #define RT5659_M_DAC_L2_STO_R (0x1 << 3) |
763 | #define RT5659_M_DAC_L2_STO_R_SFT 3 |
764 | #define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2) |
765 | #define RT5659_G_DAC_L2_STO_R_SFT 2 |
766 | #define RT5659_M_DAC_R2_STO_R (0x1 << 1) |
767 | #define RT5659_M_DAC_R2_STO_R_SFT 1 |
768 | #define RT5659_G_DAC_R2_STO_R_MASK (0x1) |
769 | #define RT5659_G_DAC_R2_STO_R_SFT 0 |
770 | |
771 | /* Mono DAC Mixer Control (0x002b) */ |
772 | #define RT5659_M_DAC_L1_MONO_L (0x1 << 15) |
773 | #define RT5659_M_DAC_L1_MONO_L_SFT 15 |
774 | #define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14) |
775 | #define RT5659_G_DAC_L1_MONO_L_SFT 14 |
776 | #define RT5659_M_DAC_R1_MONO_L (0x1 << 13) |
777 | #define RT5659_M_DAC_R1_MONO_L_SFT 13 |
778 | #define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12) |
779 | #define RT5659_G_DAC_R1_MONO_L_SFT 12 |
780 | #define RT5659_M_DAC_L2_MONO_L (0x1 << 11) |
781 | #define RT5659_M_DAC_L2_MONO_L_SFT 11 |
782 | #define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10) |
783 | #define RT5659_G_DAC_L2_MONO_L_SFT 10 |
784 | #define RT5659_M_DAC_R2_MONO_L (0x1 << 9) |
785 | #define RT5659_M_DAC_R2_MONO_L_SFT 9 |
786 | #define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8) |
787 | #define RT5659_G_DAC_R2_MONO_L_SFT 8 |
788 | #define RT5659_M_DAC_L1_MONO_R (0x1 << 7) |
789 | #define RT5659_M_DAC_L1_MONO_R_SFT 7 |
790 | #define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6) |
791 | #define RT5659_G_DAC_L1_MONO_R_SFT 6 |
792 | #define RT5659_M_DAC_R1_MONO_R (0x1 << 5) |
793 | #define RT5659_M_DAC_R1_MONO_R_SFT 5 |
794 | #define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4) |
795 | #define RT5659_G_DAC_R1_MONO_R_SFT 4 |
796 | #define RT5659_M_DAC_L2_MONO_R (0x1 << 3) |
797 | #define RT5659_M_DAC_L2_MONO_R_SFT 3 |
798 | #define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2) |
799 | #define RT5659_G_DAC_L2_MONO_R_SFT 2 |
800 | #define RT5659_M_DAC_R2_MONO_R (0x1 << 1) |
801 | #define RT5659_M_DAC_R2_MONO_R_SFT 1 |
802 | #define RT5659_G_DAC_R2_MONO_R_MASK (0x1) |
803 | #define RT5659_G_DAC_R2_MONO_R_SFT 0 |
804 | |
805 | /* Digital Mixer Control (0x002c) */ |
806 | #define RT5659_M_DAC_MIX_L (0x1 << 7) |
807 | #define RT5659_M_DAC_MIX_L_SFT 7 |
808 | #define RT5659_DAC_MIX_L_MASK (0x1 << 6) |
809 | #define RT5659_DAC_MIX_L_SFT 6 |
810 | #define RT5659_M_DAC_MIX_R (0x1 << 5) |
811 | #define RT5659_M_DAC_MIX_R_SFT 5 |
812 | #define RT5659_DAC_MIX_R_MASK (0x1 << 4) |
813 | #define RT5659_DAC_MIX_R_SFT 4 |
814 | |
815 | /* Analog DAC Input Source Control (0x002d) */ |
816 | #define RT5659_A_DACL1_SEL (0x1 << 3) |
817 | #define RT5659_A_DACL1_SFT 3 |
818 | #define RT5659_A_DACR1_SEL (0x1 << 2) |
819 | #define RT5659_A_DACR1_SFT 2 |
820 | #define RT5659_A_DACL2_SEL (0x1 << 1) |
821 | #define RT5659_A_DACL2_SFT 1 |
822 | #define RT5659_A_DACR2_SEL (0x1 << 0) |
823 | #define RT5659_A_DACR2_SFT 0 |
824 | |
825 | /* Digital Interface Data Control (0x002f) */ |
826 | #define RT5659_IF2_ADC3_IN_MASK (0x3 << 14) |
827 | #define RT5659_IF2_ADC3_IN_SFT 14 |
828 | #define RT5659_IF2_ADC_IN_MASK (0x3 << 12) |
829 | #define RT5659_IF2_ADC_IN_SFT 12 |
830 | #define RT5659_IF2_DAC_SEL_MASK (0x3 << 10) |
831 | #define RT5659_IF2_DAC_SEL_SFT 10 |
832 | #define RT5659_IF2_ADC_SEL_MASK (0x3 << 8) |
833 | #define RT5659_IF2_ADC_SEL_SFT 8 |
834 | #define RT5659_IF3_DAC_SEL_MASK (0x3 << 6) |
835 | #define RT5659_IF3_DAC_SEL_SFT 6 |
836 | #define RT5659_IF3_ADC_SEL_MASK (0x3 << 4) |
837 | #define RT5659_IF3_ADC_SEL_SFT 4 |
838 | #define RT5659_IF3_ADC_IN_MASK (0x3 << 0) |
839 | #define RT5659_IF3_ADC_IN_SFT 0 |
840 | |
841 | /* PDM Output Control (0x0031) */ |
842 | #define RT5659_PDM1_L_MASK (0x1 << 15) |
843 | #define RT5659_PDM1_L_SFT 15 |
844 | #define RT5659_M_PDM1_L (0x1 << 14) |
845 | #define RT5659_M_PDM1_L_SFT 14 |
846 | #define RT5659_PDM1_R_MASK (0x1 << 13) |
847 | #define RT5659_PDM1_R_SFT 13 |
848 | #define RT5659_M_PDM1_R (0x1 << 12) |
849 | #define RT5659_M_PDM1_R_SFT 12 |
850 | #define RT5659_PDM2_BUSY (0x1 << 7) |
851 | #define RT5659_PDM1_BUSY (0x1 << 6) |
852 | #define RT5659_PDM_PATTERN (0x1 << 5) |
853 | #define RT5659_PDM_GAIN (0x1 << 4) |
854 | #define RT5659_PDM_DIV_MASK (0x3) |
855 | |
856 | /*S/PDIF Output Control (0x0036) */ |
857 | #define RT5659_SPDIF_SEL_MASK (0x3 << 0) |
858 | #define RT5659_SPDIF_SEL_SFT 0 |
859 | |
860 | /* REC Left Mixer Control 2 (0x003c) */ |
861 | #define RT5659_M_BST1_RM1_L (0x1 << 5) |
862 | #define RT5659_M_BST1_RM1_L_SFT 5 |
863 | #define RT5659_M_BST2_RM1_L (0x1 << 4) |
864 | #define RT5659_M_BST2_RM1_L_SFT 4 |
865 | #define RT5659_M_BST3_RM1_L (0x1 << 3) |
866 | #define RT5659_M_BST3_RM1_L_SFT 3 |
867 | #define RT5659_M_BST4_RM1_L (0x1 << 2) |
868 | #define RT5659_M_BST4_RM1_L_SFT 2 |
869 | #define RT5659_M_INL_RM1_L (0x1 << 1) |
870 | #define RT5659_M_INL_RM1_L_SFT 1 |
871 | #define RT5659_M_SPKVOLL_RM1_L (0x1) |
872 | #define RT5659_M_SPKVOLL_RM1_L_SFT 0 |
873 | |
874 | /* REC Right Mixer Control 2 (0x003e) */ |
875 | #define RT5659_M_BST1_RM1_R (0x1 << 5) |
876 | #define RT5659_M_BST1_RM1_R_SFT 5 |
877 | #define RT5659_M_BST2_RM1_R (0x1 << 4) |
878 | #define RT5659_M_BST2_RM1_R_SFT 4 |
879 | #define RT5659_M_BST3_RM1_R (0x1 << 3) |
880 | #define RT5659_M_BST3_RM1_R_SFT 3 |
881 | #define RT5659_M_BST4_RM1_R (0x1 << 2) |
882 | #define RT5659_M_BST4_RM1_R_SFT 2 |
883 | #define RT5659_M_INR_RM1_R (0x1 << 1) |
884 | #define RT5659_M_INR_RM1_R_SFT 1 |
885 | #define RT5659_M_HPOVOLR_RM1_R (0x1) |
886 | #define RT5659_M_HPOVOLR_RM1_R_SFT 0 |
887 | |
888 | /* SPK Left Mixer Control (0x0046) */ |
889 | #define RT5659_M_BST3_SM_L (0x1 << 4) |
890 | #define RT5659_M_BST3_SM_L_SFT 4 |
891 | #define RT5659_M_IN_R_SM_L (0x1 << 3) |
892 | #define RT5659_M_IN_R_SM_L_SFT 3 |
893 | #define RT5659_M_IN_L_SM_L (0x1 << 2) |
894 | #define RT5659_M_IN_L_SM_L_SFT 2 |
895 | #define RT5659_M_BST1_SM_L (0x1 << 1) |
896 | #define RT5659_M_BST1_SM_L_SFT 1 |
897 | #define RT5659_M_DAC_L2_SM_L (0x1) |
898 | #define RT5659_M_DAC_L2_SM_L_SFT 0 |
899 | |
900 | /* SPK Right Mixer Control (0x0047) */ |
901 | #define RT5659_M_BST3_SM_R (0x1 << 4) |
902 | #define RT5659_M_BST3_SM_R_SFT 4 |
903 | #define RT5659_M_IN_R_SM_R (0x1 << 3) |
904 | #define RT5659_M_IN_R_SM_R_SFT 3 |
905 | #define RT5659_M_IN_L_SM_R (0x1 << 2) |
906 | #define RT5659_M_IN_L_SM_R_SFT 2 |
907 | #define RT5659_M_BST4_SM_R (0x1 << 1) |
908 | #define RT5659_M_BST4_SM_R_SFT 1 |
909 | #define RT5659_M_DAC_R2_SM_R (0x1) |
910 | #define RT5659_M_DAC_R2_SM_R_SFT 0 |
911 | |
912 | /* SPO Amp Input and Gain Control (0x0048) */ |
913 | #define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13) |
914 | #define RT5659_M_DAC_L2_SPKOMIX_SFT 13 |
915 | #define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12) |
916 | #define RT5659_M_SPKVOLL_SPKOMIX_SFT 12 |
917 | #define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9) |
918 | #define RT5659_M_DAC_R2_SPKOMIX_SFT 9 |
919 | #define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8) |
920 | #define RT5659_M_SPKVOLR_SPKOMIX_SFT 8 |
921 | |
922 | /* MONOMIX Input and Gain Control (0x004b) */ |
923 | #define RT5659_M_MONOVOL_MA (0x1 << 9) |
924 | #define RT5659_M_MONOVOL_MA_SFT 9 |
925 | #define RT5659_M_DAC_L2_MA (0x1 << 8) |
926 | #define RT5659_M_DAC_L2_MA_SFT 8 |
927 | #define RT5659_M_BST3_MM (0x1 << 4) |
928 | #define RT5659_M_BST3_MM_SFT 4 |
929 | #define RT5659_M_BST2_MM (0x1 << 3) |
930 | #define RT5659_M_BST2_MM_SFT 3 |
931 | #define RT5659_M_BST1_MM (0x1 << 2) |
932 | #define RT5659_M_BST1_MM_SFT 2 |
933 | #define RT5659_M_DAC_R2_MM (0x1 << 1) |
934 | #define RT5659_M_DAC_R2_MM_SFT 1 |
935 | #define RT5659_M_DAC_L2_MM (0x1) |
936 | #define RT5659_M_DAC_L2_MM_SFT 0 |
937 | |
938 | /* Output Left Mixer Control 1 (0x004d) */ |
939 | #define RT5659_G_BST3_OM_L_MASK (0x7 << 12) |
940 | #define RT5659_G_BST3_OM_L_SFT 12 |
941 | #define RT5659_G_BST2_OM_L_MASK (0x7 << 9) |
942 | #define RT5659_G_BST2_OM_L_SFT 9 |
943 | #define RT5659_G_BST1_OM_L_MASK (0x7 << 6) |
944 | #define RT5659_G_BST1_OM_L_SFT 6 |
945 | #define RT5659_G_IN_L_OM_L_MASK (0x7 << 3) |
946 | #define RT5659_G_IN_L_OM_L_SFT 3 |
947 | #define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0) |
948 | #define RT5659_G_DAC_L2_OM_L_SFT 0 |
949 | |
950 | /* Output Left Mixer Input Control (0x004e) */ |
951 | #define RT5659_M_BST3_OM_L (0x1 << 4) |
952 | #define RT5659_M_BST3_OM_L_SFT 4 |
953 | #define RT5659_M_BST2_OM_L (0x1 << 3) |
954 | #define RT5659_M_BST2_OM_L_SFT 3 |
955 | #define RT5659_M_BST1_OM_L (0x1 << 2) |
956 | #define RT5659_M_BST1_OM_L_SFT 2 |
957 | #define RT5659_M_IN_L_OM_L (0x1 << 1) |
958 | #define RT5659_M_IN_L_OM_L_SFT 1 |
959 | #define RT5659_M_DAC_L2_OM_L (0x1) |
960 | #define RT5659_M_DAC_L2_OM_L_SFT 0 |
961 | |
962 | /* Output Right Mixer Input Control (0x0050) */ |
963 | #define RT5659_M_BST4_OM_R (0x1 << 4) |
964 | #define RT5659_M_BST4_OM_R_SFT 4 |
965 | #define RT5659_M_BST3_OM_R (0x1 << 3) |
966 | #define RT5659_M_BST3_OM_R_SFT 3 |
967 | #define RT5659_M_BST2_OM_R (0x1 << 2) |
968 | #define RT5659_M_BST2_OM_R_SFT 2 |
969 | #define RT5659_M_IN_R_OM_R (0x1 << 1) |
970 | #define RT5659_M_IN_R_OM_R_SFT 1 |
971 | #define RT5659_M_DAC_R2_OM_R (0x1) |
972 | #define RT5659_M_DAC_R2_OM_R_SFT 0 |
973 | |
974 | /* LOUT Mixer Control (0x0052) */ |
975 | #define RT5659_M_DAC_L2_LM (0x1 << 15) |
976 | #define RT5659_M_DAC_L2_LM_SFT 15 |
977 | #define RT5659_M_DAC_R2_LM (0x1 << 14) |
978 | #define RT5659_M_DAC_R2_LM_SFT 14 |
979 | #define RT5659_M_OV_L_LM (0x1 << 13) |
980 | #define RT5659_M_OV_L_LM_SFT 13 |
981 | #define RT5659_M_OV_R_LM (0x1 << 12) |
982 | #define RT5659_M_OV_R_LM_SFT 12 |
983 | |
984 | /* Power Management for Digital 1 (0x0061) */ |
985 | #define RT5659_PWR_I2S1 (0x1 << 15) |
986 | #define RT5659_PWR_I2S1_BIT 15 |
987 | #define RT5659_PWR_I2S2 (0x1 << 14) |
988 | #define RT5659_PWR_I2S2_BIT 14 |
989 | #define RT5659_PWR_I2S3 (0x1 << 13) |
990 | #define RT5659_PWR_I2S3_BIT 13 |
991 | #define RT5659_PWR_SPDIF (0x1 << 12) |
992 | #define RT5659_PWR_SPDIF_BIT 12 |
993 | #define RT5659_PWR_DAC_L1 (0x1 << 11) |
994 | #define RT5659_PWR_DAC_L1_BIT 11 |
995 | #define RT5659_PWR_DAC_R1 (0x1 << 10) |
996 | #define RT5659_PWR_DAC_R1_BIT 10 |
997 | #define RT5659_PWR_DAC_L2 (0x1 << 9) |
998 | #define RT5659_PWR_DAC_L2_BIT 9 |
999 | #define RT5659_PWR_DAC_R2 (0x1 << 8) |
1000 | #define RT5659_PWR_DAC_R2_BIT 8 |
1001 | #define RT5659_PWR_LDO (0x1 << 7) |
1002 | #define RT5659_PWR_LDO_BIT 7 |
1003 | #define RT5659_PWR_ADC_L1 (0x1 << 4) |
1004 | #define RT5659_PWR_ADC_L1_BIT 4 |
1005 | #define RT5659_PWR_ADC_R1 (0x1 << 3) |
1006 | #define RT5659_PWR_ADC_R1_BIT 3 |
1007 | #define RT5659_PWR_ADC_L2 (0x1 << 2) |
1008 | #define RT5659_PWR_ADC_L2_BIT 2 |
1009 | #define RT5659_PWR_ADC_R2 (0x1 << 1) |
1010 | #define RT5659_PWR_ADC_R2_BIT 1 |
1011 | #define RT5659_PWR_CLS_D (0x1) |
1012 | #define RT5659_PWR_CLS_D_BIT 0 |
1013 | |
1014 | /* Power Management for Digital 2 (0x0062) */ |
1015 | #define RT5659_PWR_ADC_S1F (0x1 << 15) |
1016 | #define RT5659_PWR_ADC_S1F_BIT 15 |
1017 | #define RT5659_PWR_ADC_S2F (0x1 << 14) |
1018 | #define RT5659_PWR_ADC_S2F_BIT 14 |
1019 | #define RT5659_PWR_ADC_MF_L (0x1 << 13) |
1020 | #define RT5659_PWR_ADC_MF_L_BIT 13 |
1021 | #define RT5659_PWR_ADC_MF_R (0x1 << 12) |
1022 | #define RT5659_PWR_ADC_MF_R_BIT 12 |
1023 | #define RT5659_PWR_DAC_S1F (0x1 << 10) |
1024 | #define RT5659_PWR_DAC_S1F_BIT 10 |
1025 | #define RT5659_PWR_DAC_MF_L (0x1 << 9) |
1026 | #define RT5659_PWR_DAC_MF_L_BIT 9 |
1027 | #define RT5659_PWR_DAC_MF_R (0x1 << 8) |
1028 | #define RT5659_PWR_DAC_MF_R_BIT 8 |
1029 | #define RT5659_PWR_PDM1 (0x1 << 7) |
1030 | #define RT5659_PWR_PDM1_BIT 7 |
1031 | |
1032 | /* Power Management for Analog 1 (0x0063) */ |
1033 | #define RT5659_PWR_VREF1 (0x1 << 15) |
1034 | #define RT5659_PWR_VREF1_BIT 15 |
1035 | #define RT5659_PWR_FV1 (0x1 << 14) |
1036 | #define RT5659_PWR_FV1_BIT 14 |
1037 | #define RT5659_PWR_VREF2 (0x1 << 13) |
1038 | #define RT5659_PWR_VREF2_BIT 13 |
1039 | #define RT5659_PWR_FV2 (0x1 << 12) |
1040 | #define RT5659_PWR_FV2_BIT 12 |
1041 | #define RT5659_PWR_VREF3 (0x1 << 11) |
1042 | #define RT5659_PWR_VREF3_BIT 11 |
1043 | #define RT5659_PWR_FV3 (0x1 << 10) |
1044 | #define RT5659_PWR_FV3_BIT 10 |
1045 | #define RT5659_PWR_MB (0x1 << 9) |
1046 | #define RT5659_PWR_MB_BIT 9 |
1047 | #define RT5659_PWR_LM (0x1 << 8) |
1048 | #define RT5659_PWR_LM_BIT 8 |
1049 | #define RT5659_PWR_BG (0x1 << 7) |
1050 | #define RT5659_PWR_BG_BIT 7 |
1051 | #define RT5659_PWR_MA (0x1 << 6) |
1052 | #define RT5659_PWR_MA_BIT 6 |
1053 | #define RT5659_PWR_HA_L (0x1 << 5) |
1054 | #define RT5659_PWR_HA_L_BIT 5 |
1055 | #define RT5659_PWR_HA_R (0x1 << 4) |
1056 | #define RT5659_PWR_HA_R_BIT 4 |
1057 | |
1058 | /* Power Management for Analog 2 (0x0064) */ |
1059 | #define RT5659_PWR_BST1 (0x1 << 15) |
1060 | #define RT5659_PWR_BST1_BIT 15 |
1061 | #define RT5659_PWR_BST2 (0x1 << 14) |
1062 | #define RT5659_PWR_BST2_BIT 14 |
1063 | #define RT5659_PWR_BST3 (0x1 << 13) |
1064 | #define RT5659_PWR_BST3_BIT 13 |
1065 | #define RT5659_PWR_BST4 (0x1 << 12) |
1066 | #define RT5659_PWR_BST4_BIT 12 |
1067 | #define RT5659_PWR_MB1 (0x1 << 11) |
1068 | #define RT5659_PWR_MB1_BIT 11 |
1069 | #define RT5659_PWR_MB2 (0x1 << 10) |
1070 | #define RT5659_PWR_MB2_BIT 10 |
1071 | #define RT5659_PWR_MB3 (0x1 << 9) |
1072 | #define RT5659_PWR_MB3_BIT 9 |
1073 | #define RT5659_PWR_BST1_P (0x1 << 6) |
1074 | #define RT5659_PWR_BST1_P_BIT 6 |
1075 | #define RT5659_PWR_BST2_P (0x1 << 5) |
1076 | #define RT5659_PWR_BST2_P_BIT 5 |
1077 | #define RT5659_PWR_BST3_P (0x1 << 4) |
1078 | #define RT5659_PWR_BST3_P_BIT 4 |
1079 | #define RT5659_PWR_BST4_P (0x1 << 3) |
1080 | #define RT5659_PWR_BST4_P_BIT 3 |
1081 | #define RT5659_PWR_JD1 (0x1 << 2) |
1082 | #define RT5659_PWR_JD1_BIT 2 |
1083 | #define RT5659_PWR_JD2 (0x1 << 1) |
1084 | #define RT5659_PWR_JD2_BIT 1 |
1085 | #define RT5659_PWR_JD3 (0x1) |
1086 | #define RT5659_PWR_JD3_BIT 0 |
1087 | |
1088 | /* Power Management for Analog 3 (0x0065) */ |
1089 | #define RT5659_PWR_BST_L (0x1 << 8) |
1090 | #define RT5659_PWR_BST_L_BIT 8 |
1091 | #define RT5659_PWR_BST_R (0x1 << 7) |
1092 | #define RT5659_PWR_BST_R_BIT 7 |
1093 | #define RT5659_PWR_PLL (0x1 << 6) |
1094 | #define RT5659_PWR_PLL_BIT 6 |
1095 | #define RT5659_PWR_LDO5 (0x1 << 5) |
1096 | #define RT5659_PWR_LDO5_BIT 5 |
1097 | #define RT5659_PWR_LDO4 (0x1 << 4) |
1098 | #define RT5659_PWR_LDO4_BIT 4 |
1099 | #define RT5659_PWR_LDO3 (0x1 << 3) |
1100 | #define RT5659_PWR_LDO3_BIT 3 |
1101 | #define RT5659_PWR_LDO2 (0x1 << 2) |
1102 | #define RT5659_PWR_LDO2_BIT 2 |
1103 | #define RT5659_PWR_SVD (0x1 << 1) |
1104 | #define RT5659_PWR_SVD_BIT 1 |
1105 | |
1106 | /* Power Management for Mixer (0x0066) */ |
1107 | #define RT5659_PWR_OM_L (0x1 << 15) |
1108 | #define RT5659_PWR_OM_L_BIT 15 |
1109 | #define RT5659_PWR_OM_R (0x1 << 14) |
1110 | #define RT5659_PWR_OM_R_BIT 14 |
1111 | #define RT5659_PWR_SM_L (0x1 << 13) |
1112 | #define RT5659_PWR_SM_L_BIT 13 |
1113 | #define RT5659_PWR_SM_R (0x1 << 12) |
1114 | #define RT5659_PWR_SM_R_BIT 12 |
1115 | #define RT5659_PWR_RM1_L (0x1 << 11) |
1116 | #define RT5659_PWR_RM1_L_BIT 11 |
1117 | #define RT5659_PWR_RM1_R (0x1 << 10) |
1118 | #define RT5659_PWR_RM1_R_BIT 10 |
1119 | #define RT5659_PWR_MM (0x1 << 8) |
1120 | #define RT5659_PWR_MM_BIT 8 |
1121 | #define RT5659_PWR_RM2_L (0x1 << 3) |
1122 | #define RT5659_PWR_RM2_L_BIT 3 |
1123 | #define RT5659_PWR_RM2_R (0x1 << 2) |
1124 | #define RT5659_PWR_RM2_R_BIT 2 |
1125 | |
1126 | /* Power Management for Volume (0x0067) */ |
1127 | #define RT5659_PWR_SV_L (0x1 << 15) |
1128 | #define RT5659_PWR_SV_L_BIT 15 |
1129 | #define RT5659_PWR_SV_R (0x1 << 14) |
1130 | #define RT5659_PWR_SV_R_BIT 14 |
1131 | #define RT5659_PWR_OV_L (0x1 << 13) |
1132 | #define RT5659_PWR_OV_L_BIT 13 |
1133 | #define RT5659_PWR_OV_R (0x1 << 12) |
1134 | #define RT5659_PWR_OV_R_BIT 12 |
1135 | #define RT5659_PWR_IN_L (0x1 << 9) |
1136 | #define RT5659_PWR_IN_L_BIT 9 |
1137 | #define RT5659_PWR_IN_R (0x1 << 8) |
1138 | #define RT5659_PWR_IN_R_BIT 8 |
1139 | #define RT5659_PWR_MV (0x1 << 7) |
1140 | #define RT5659_PWR_MV_BIT 7 |
1141 | #define RT5659_PWR_MIC_DET (0x1 << 5) |
1142 | #define RT5659_PWR_MIC_DET_BIT 5 |
1143 | |
1144 | /* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */ |
1145 | #define RT5659_I2S_MS_MASK (0x1 << 15) |
1146 | #define RT5659_I2S_MS_SFT 15 |
1147 | #define RT5659_I2S_MS_M (0x0 << 15) |
1148 | #define RT5659_I2S_MS_S (0x1 << 15) |
1149 | #define RT5659_I2S_O_CP_MASK (0x3 << 12) |
1150 | #define RT5659_I2S_O_CP_SFT 12 |
1151 | #define RT5659_I2S_O_CP_OFF (0x0 << 12) |
1152 | #define RT5659_I2S_O_CP_U_LAW (0x1 << 12) |
1153 | #define RT5659_I2S_O_CP_A_LAW (0x2 << 12) |
1154 | #define RT5659_I2S_I_CP_MASK (0x3 << 10) |
1155 | #define RT5659_I2S_I_CP_SFT 10 |
1156 | #define RT5659_I2S_I_CP_OFF (0x0 << 10) |
1157 | #define RT5659_I2S_I_CP_U_LAW (0x1 << 10) |
1158 | #define RT5659_I2S_I_CP_A_LAW (0x2 << 10) |
1159 | #define RT5659_I2S_BP_MASK (0x1 << 8) |
1160 | #define RT5659_I2S_BP_SFT 8 |
1161 | #define RT5659_I2S_BP_NOR (0x0 << 8) |
1162 | #define RT5659_I2S_BP_INV (0x1 << 8) |
1163 | #define RT5659_I2S_DL_MASK (0x3 << 4) |
1164 | #define RT5659_I2S_DL_SFT 4 |
1165 | #define RT5659_I2S_DL_16 (0x0 << 4) |
1166 | #define RT5659_I2S_DL_20 (0x1 << 4) |
1167 | #define RT5659_I2S_DL_24 (0x2 << 4) |
1168 | #define RT5659_I2S_DL_8 (0x3 << 4) |
1169 | #define RT5659_I2S_DF_MASK (0x7) |
1170 | #define RT5659_I2S_DF_SFT 0 |
1171 | #define RT5659_I2S_DF_I2S (0x0) |
1172 | #define RT5659_I2S_DF_LEFT (0x1) |
1173 | #define RT5659_I2S_DF_PCM_A (0x2) |
1174 | #define RT5659_I2S_DF_PCM_B (0x3) |
1175 | #define RT5659_I2S_DF_PCM_A_N (0x6) |
1176 | #define RT5659_I2S_DF_PCM_B_N (0x7) |
1177 | |
1178 | /* ADC/DAC Clock Control 1 (0x0073) */ |
1179 | #define RT5659_I2S_PD1_MASK (0x7 << 12) |
1180 | #define RT5659_I2S_PD1_SFT 12 |
1181 | #define RT5659_I2S_PD1_1 (0x0 << 12) |
1182 | #define RT5659_I2S_PD1_2 (0x1 << 12) |
1183 | #define RT5659_I2S_PD1_3 (0x2 << 12) |
1184 | #define RT5659_I2S_PD1_4 (0x3 << 12) |
1185 | #define RT5659_I2S_PD1_6 (0x4 << 12) |
1186 | #define RT5659_I2S_PD1_8 (0x5 << 12) |
1187 | #define RT5659_I2S_PD1_12 (0x6 << 12) |
1188 | #define RT5659_I2S_PD1_16 (0x7 << 12) |
1189 | #define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11) |
1190 | #define RT5659_I2S_BCLK_MS2_SFT 11 |
1191 | #define RT5659_I2S_BCLK_MS2_32 (0x0 << 11) |
1192 | #define RT5659_I2S_BCLK_MS2_64 (0x1 << 11) |
1193 | #define RT5659_I2S_PD2_MASK (0x7 << 8) |
1194 | #define RT5659_I2S_PD2_SFT 8 |
1195 | #define RT5659_I2S_PD2_1 (0x0 << 8) |
1196 | #define RT5659_I2S_PD2_2 (0x1 << 8) |
1197 | #define RT5659_I2S_PD2_3 (0x2 << 8) |
1198 | #define RT5659_I2S_PD2_4 (0x3 << 8) |
1199 | #define RT5659_I2S_PD2_6 (0x4 << 8) |
1200 | #define RT5659_I2S_PD2_8 (0x5 << 8) |
1201 | #define RT5659_I2S_PD2_12 (0x6 << 8) |
1202 | #define RT5659_I2S_PD2_16 (0x7 << 8) |
1203 | #define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7) |
1204 | #define RT5659_I2S_BCLK_MS3_SFT 7 |
1205 | #define RT5659_I2S_BCLK_MS3_32 (0x0 << 7) |
1206 | #define RT5659_I2S_BCLK_MS3_64 (0x1 << 7) |
1207 | #define RT5659_I2S_PD3_MASK (0x7 << 4) |
1208 | #define RT5659_I2S_PD3_SFT 4 |
1209 | #define RT5659_I2S_PD3_1 (0x0 << 4) |
1210 | #define RT5659_I2S_PD3_2 (0x1 << 4) |
1211 | #define RT5659_I2S_PD3_3 (0x2 << 4) |
1212 | #define RT5659_I2S_PD3_4 (0x3 << 4) |
1213 | #define RT5659_I2S_PD3_6 (0x4 << 4) |
1214 | #define RT5659_I2S_PD3_8 (0x5 << 4) |
1215 | #define RT5659_I2S_PD3_12 (0x6 << 4) |
1216 | #define RT5659_I2S_PD3_16 (0x7 << 4) |
1217 | #define RT5659_DAC_OSR_MASK (0x3 << 2) |
1218 | #define RT5659_DAC_OSR_SFT 2 |
1219 | #define RT5659_DAC_OSR_128 (0x0 << 2) |
1220 | #define RT5659_DAC_OSR_64 (0x1 << 2) |
1221 | #define RT5659_DAC_OSR_32 (0x2 << 2) |
1222 | #define RT5659_DAC_OSR_16 (0x3 << 2) |
1223 | #define RT5659_ADC_OSR_MASK (0x3) |
1224 | #define RT5659_ADC_OSR_SFT 0 |
1225 | #define RT5659_ADC_OSR_128 (0x0) |
1226 | #define RT5659_ADC_OSR_64 (0x1) |
1227 | #define RT5659_ADC_OSR_32 (0x2) |
1228 | #define RT5659_ADC_OSR_16 (0x3) |
1229 | |
1230 | /* Digital Microphone Control (0x0075) */ |
1231 | #define RT5659_DMIC_1_EN_MASK (0x1 << 15) |
1232 | #define RT5659_DMIC_1_EN_SFT 15 |
1233 | #define RT5659_DMIC_1_DIS (0x0 << 15) |
1234 | #define RT5659_DMIC_1_EN (0x1 << 15) |
1235 | #define RT5659_DMIC_2_EN_MASK (0x1 << 14) |
1236 | #define RT5659_DMIC_2_EN_SFT 14 |
1237 | #define RT5659_DMIC_2_DIS (0x0 << 14) |
1238 | #define RT5659_DMIC_2_EN (0x1 << 14) |
1239 | #define RT5659_DMIC_1L_LH_MASK (0x1 << 13) |
1240 | #define RT5659_DMIC_1L_LH_SFT 13 |
1241 | #define RT5659_DMIC_1L_LH_RISING (0x0 << 13) |
1242 | #define RT5659_DMIC_1L_LH_FALLING (0x1 << 13) |
1243 | #define RT5659_DMIC_1R_LH_MASK (0x1 << 12) |
1244 | #define RT5659_DMIC_1R_LH_SFT 12 |
1245 | #define RT5659_DMIC_1R_LH_RISING (0x0 << 12) |
1246 | #define RT5659_DMIC_1R_LH_FALLING (0x1 << 12) |
1247 | #define RT5659_DMIC_2_DP_MASK (0x3 << 10) |
1248 | #define RT5659_DMIC_2_DP_SFT 10 |
1249 | #define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10) |
1250 | #define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10) |
1251 | #define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10) |
1252 | #define RT5659_DMIC_2_DP_IN2P (0x3 << 10) |
1253 | #define RT5659_DMIC_CLK_MASK (0x7 << 5) |
1254 | #define RT5659_DMIC_CLK_SFT 5 |
1255 | #define RT5659_DMIC_1_DP_MASK (0x3 << 0) |
1256 | #define RT5659_DMIC_1_DP_SFT 0 |
1257 | #define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0) |
1258 | #define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0) |
1259 | #define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0) |
1260 | #define RT5659_DMIC_1_DP_IN2N (0x3 << 0) |
1261 | |
1262 | /* TDM control 1 (0x0078)*/ |
1263 | #define RT5659_DS_ADC_SLOT01_SFT 14 |
1264 | #define RT5659_DS_ADC_SLOT23_SFT 12 |
1265 | #define RT5659_DS_ADC_SLOT45_SFT 10 |
1266 | #define RT5659_DS_ADC_SLOT67_SFT 8 |
1267 | #define RT5659_ADCDAT_SRC_MASK 0x1f |
1268 | #define RT5659_ADCDAT_SRC_SFT 0 |
1269 | |
1270 | /* Global Clock Control (0x0080) */ |
1271 | #define RT5659_SCLK_SRC_MASK (0x3 << 14) |
1272 | #define RT5659_SCLK_SRC_SFT 14 |
1273 | #define RT5659_SCLK_SRC_MCLK (0x0 << 14) |
1274 | #define RT5659_SCLK_SRC_PLL1 (0x1 << 14) |
1275 | #define RT5659_SCLK_SRC_RCCLK (0x2 << 14) |
1276 | #define RT5659_PLL1_SRC_MASK (0x7 << 11) |
1277 | #define RT5659_PLL1_SRC_SFT 11 |
1278 | #define RT5659_PLL1_SRC_MCLK (0x0 << 11) |
1279 | #define RT5659_PLL1_SRC_BCLK1 (0x1 << 11) |
1280 | #define RT5659_PLL1_SRC_BCLK2 (0x2 << 11) |
1281 | #define RT5659_PLL1_SRC_BCLK3 (0x3 << 11) |
1282 | #define RT5659_PLL1_PD_MASK (0x1 << 3) |
1283 | #define RT5659_PLL1_PD_SFT 3 |
1284 | #define RT5659_PLL1_PD_1 (0x0 << 3) |
1285 | #define RT5659_PLL1_PD_2 (0x1 << 3) |
1286 | |
1287 | #define RT5659_PLL_INP_MAX 40000000 |
1288 | #define RT5659_PLL_INP_MIN 256000 |
1289 | /* PLL M/N/K Code Control 1 (0x0081) */ |
1290 | #define RT5659_PLL_N_MAX 0x001ff |
1291 | #define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7) |
1292 | #define RT5659_PLL_N_SFT 7 |
1293 | #define RT5659_PLL_K_MAX 0x001f |
1294 | #define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX) |
1295 | #define RT5659_PLL_K_SFT 0 |
1296 | |
1297 | /* PLL M/N/K Code Control 2 (0x0082) */ |
1298 | #define RT5659_PLL_M_MAX 0x00f |
1299 | #define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12) |
1300 | #define RT5659_PLL_M_SFT 12 |
1301 | #define RT5659_PLL_M_BP (0x1 << 11) |
1302 | #define RT5659_PLL_M_BP_SFT 11 |
1303 | |
1304 | /* PLL tracking mode 1 (0x0083) */ |
1305 | #define RT5659_I2S3_ASRC_MASK (0x1 << 13) |
1306 | #define RT5659_I2S3_ASRC_SFT 13 |
1307 | #define RT5659_I2S2_ASRC_MASK (0x1 << 12) |
1308 | #define RT5659_I2S2_ASRC_SFT 12 |
1309 | #define RT5659_I2S1_ASRC_MASK (0x1 << 11) |
1310 | #define RT5659_I2S1_ASRC_SFT 11 |
1311 | #define RT5659_DAC_STO_ASRC_MASK (0x1 << 10) |
1312 | #define RT5659_DAC_STO_ASRC_SFT 10 |
1313 | #define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9) |
1314 | #define RT5659_DAC_MONO_L_ASRC_SFT 9 |
1315 | #define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8) |
1316 | #define RT5659_DAC_MONO_R_ASRC_SFT 8 |
1317 | #define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7) |
1318 | #define RT5659_DMIC_STO1_ASRC_SFT 7 |
1319 | #define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5) |
1320 | #define RT5659_DMIC_MONO_L_ASRC_SFT 5 |
1321 | #define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4) |
1322 | #define RT5659_DMIC_MONO_R_ASRC_SFT 4 |
1323 | #define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3) |
1324 | #define RT5659_ADC_STO1_ASRC_SFT 3 |
1325 | #define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1) |
1326 | #define RT5659_ADC_MONO_L_ASRC_SFT 1 |
1327 | #define RT5659_ADC_MONO_R_ASRC_MASK (0x1) |
1328 | #define RT5659_ADC_MONO_R_ASRC_SFT 0 |
1329 | |
1330 | /* PLL tracking mode 2 (0x0084)*/ |
1331 | #define RT5659_DA_STO_T_MASK (0x7 << 12) |
1332 | #define RT5659_DA_STO_T_SFT 12 |
1333 | #define RT5659_DA_MONO_L_T_MASK (0x7 << 8) |
1334 | #define RT5659_DA_MONO_L_T_SFT 8 |
1335 | #define RT5659_DA_MONO_R_T_MASK (0x7 << 4) |
1336 | #define RT5659_DA_MONO_R_T_SFT 4 |
1337 | #define RT5659_AD_STO1_T_MASK (0x7) |
1338 | #define RT5659_AD_STO1_T_SFT 0 |
1339 | |
1340 | /* PLL tracking mode 3 (0x0085)*/ |
1341 | #define RT5659_AD_STO2_T_MASK (0x7 << 8) |
1342 | #define RT5659_AD_STO2_T_SFT 8 |
1343 | #define RT5659_AD_MONO_L_T_MASK (0x7 << 4) |
1344 | #define RT5659_AD_MONO_L_T_SFT 4 |
1345 | #define RT5659_AD_MONO_R_T_MASK (0x7) |
1346 | #define RT5659_AD_MONO_R_T_SFT 0 |
1347 | |
1348 | /* ASRC Control 4 (0x0086) */ |
1349 | #define RT5659_I2S1_RATE_MASK (0xf << 12) |
1350 | #define RT5659_I2S1_RATE_SFT 12 |
1351 | #define RT5659_I2S2_RATE_MASK (0xf << 8) |
1352 | #define RT5659_I2S2_RATE_SFT 8 |
1353 | #define RT5659_I2S3_RATE_MASK (0xf << 4) |
1354 | #define RT5659_I2S3_RATE_SFT 4 |
1355 | |
1356 | /* Depop Mode Control 1 (0x8e) */ |
1357 | #define RT5659_SMT_TRIG_MASK (0x1 << 15) |
1358 | #define RT5659_SMT_TRIG_SFT 15 |
1359 | #define RT5659_SMT_TRIG_DIS (0x0 << 15) |
1360 | #define RT5659_SMT_TRIG_EN (0x1 << 15) |
1361 | #define RT5659_HP_L_SMT_MASK (0x1 << 9) |
1362 | #define RT5659_HP_L_SMT_SFT 9 |
1363 | #define RT5659_HP_L_SMT_DIS (0x0 << 9) |
1364 | #define RT5659_HP_L_SMT_EN (0x1 << 9) |
1365 | #define RT5659_HP_R_SMT_MASK (0x1 << 8) |
1366 | #define RT5659_HP_R_SMT_SFT 8 |
1367 | #define RT5659_HP_R_SMT_DIS (0x0 << 8) |
1368 | #define RT5659_HP_R_SMT_EN (0x1 << 8) |
1369 | #define RT5659_HP_CD_PD_MASK (0x1 << 7) |
1370 | #define RT5659_HP_CD_PD_SFT 7 |
1371 | #define RT5659_HP_CD_PD_DIS (0x0 << 7) |
1372 | #define RT5659_HP_CD_PD_EN (0x1 << 7) |
1373 | #define RT5659_RSTN_MASK (0x1 << 6) |
1374 | #define RT5659_RSTN_SFT 6 |
1375 | #define RT5659_RSTN_DIS (0x0 << 6) |
1376 | #define RT5659_RSTN_EN (0x1 << 6) |
1377 | #define RT5659_RSTP_MASK (0x1 << 5) |
1378 | #define RT5659_RSTP_SFT 5 |
1379 | #define RT5659_RSTP_DIS (0x0 << 5) |
1380 | #define RT5659_RSTP_EN (0x1 << 5) |
1381 | #define RT5659_HP_CO_MASK (0x1 << 4) |
1382 | #define RT5659_HP_CO_SFT 4 |
1383 | #define RT5659_HP_CO_DIS (0x0 << 4) |
1384 | #define RT5659_HP_CO_EN (0x1 << 4) |
1385 | #define RT5659_HP_CP_MASK (0x1 << 3) |
1386 | #define RT5659_HP_CP_SFT 3 |
1387 | #define RT5659_HP_CP_PD (0x0 << 3) |
1388 | #define RT5659_HP_CP_PU (0x1 << 3) |
1389 | #define RT5659_HP_SG_MASK (0x1 << 2) |
1390 | #define RT5659_HP_SG_SFT 2 |
1391 | #define RT5659_HP_SG_DIS (0x0 << 2) |
1392 | #define RT5659_HP_SG_EN (0x1 << 2) |
1393 | #define RT5659_HP_DP_MASK (0x1 << 1) |
1394 | #define RT5659_HP_DP_SFT 1 |
1395 | #define RT5659_HP_DP_PD (0x0 << 1) |
1396 | #define RT5659_HP_DP_PU (0x1 << 1) |
1397 | #define RT5659_HP_CB_MASK (0x1) |
1398 | #define RT5659_HP_CB_SFT 0 |
1399 | #define RT5659_HP_CB_PD (0x0) |
1400 | #define RT5659_HP_CB_PU (0x1) |
1401 | |
1402 | /* Depop Mode Control 2 (0x8f) */ |
1403 | #define RT5659_DEPOP_MASK (0x1 << 13) |
1404 | #define RT5659_DEPOP_SFT 13 |
1405 | #define RT5659_DEPOP_AUTO (0x0 << 13) |
1406 | #define RT5659_DEPOP_MAN (0x1 << 13) |
1407 | #define RT5659_RAMP_MASK (0x1 << 12) |
1408 | #define RT5659_RAMP_SFT 12 |
1409 | #define RT5659_RAMP_DIS (0x0 << 12) |
1410 | #define RT5659_RAMP_EN (0x1 << 12) |
1411 | #define RT5659_BPS_MASK (0x1 << 11) |
1412 | #define RT5659_BPS_SFT 11 |
1413 | #define RT5659_BPS_DIS (0x0 << 11) |
1414 | #define RT5659_BPS_EN (0x1 << 11) |
1415 | #define RT5659_FAST_UPDN_MASK (0x1 << 10) |
1416 | #define RT5659_FAST_UPDN_SFT 10 |
1417 | #define RT5659_FAST_UPDN_DIS (0x0 << 10) |
1418 | #define RT5659_FAST_UPDN_EN (0x1 << 10) |
1419 | #define RT5659_MRES_MASK (0x3 << 8) |
1420 | #define RT5659_MRES_SFT 8 |
1421 | #define RT5659_MRES_15MO (0x0 << 8) |
1422 | #define RT5659_MRES_25MO (0x1 << 8) |
1423 | #define RT5659_MRES_35MO (0x2 << 8) |
1424 | #define RT5659_MRES_45MO (0x3 << 8) |
1425 | #define RT5659_VLO_MASK (0x1 << 7) |
1426 | #define RT5659_VLO_SFT 7 |
1427 | #define RT5659_VLO_3V (0x0 << 7) |
1428 | #define RT5659_VLO_32V (0x1 << 7) |
1429 | #define RT5659_DIG_DP_MASK (0x1 << 6) |
1430 | #define RT5659_DIG_DP_SFT 6 |
1431 | #define RT5659_DIG_DP_DIS (0x0 << 6) |
1432 | #define RT5659_DIG_DP_EN (0x1 << 6) |
1433 | #define RT5659_DP_TH_MASK (0x3 << 4) |
1434 | #define RT5659_DP_TH_SFT 4 |
1435 | |
1436 | /* Depop Mode Control 3 (0x90) */ |
1437 | #define RT5659_CP_SYS_MASK (0x7 << 12) |
1438 | #define RT5659_CP_SYS_SFT 12 |
1439 | #define RT5659_CP_FQ1_MASK (0x7 << 8) |
1440 | #define RT5659_CP_FQ1_SFT 8 |
1441 | #define RT5659_CP_FQ2_MASK (0x7 << 4) |
1442 | #define RT5659_CP_FQ2_SFT 4 |
1443 | #define RT5659_CP_FQ3_MASK (0x7) |
1444 | #define RT5659_CP_FQ3_SFT 0 |
1445 | #define RT5659_CP_FQ_1_5_KHZ 0 |
1446 | #define RT5659_CP_FQ_3_KHZ 1 |
1447 | #define RT5659_CP_FQ_6_KHZ 2 |
1448 | #define RT5659_CP_FQ_12_KHZ 3 |
1449 | #define RT5659_CP_FQ_24_KHZ 4 |
1450 | #define RT5659_CP_FQ_48_KHZ 5 |
1451 | #define RT5659_CP_FQ_96_KHZ 6 |
1452 | #define RT5659_CP_FQ_192_KHZ 7 |
1453 | |
1454 | /* HPOUT charge pump 1 (0x0091) */ |
1455 | #define RT5659_OSW_L_MASK (0x1 << 11) |
1456 | #define RT5659_OSW_L_SFT 11 |
1457 | #define RT5659_OSW_L_DIS (0x0 << 11) |
1458 | #define RT5659_OSW_L_EN (0x1 << 11) |
1459 | #define RT5659_OSW_R_MASK (0x1 << 10) |
1460 | #define RT5659_OSW_R_SFT 10 |
1461 | #define RT5659_OSW_R_DIS (0x0 << 10) |
1462 | #define RT5659_OSW_R_EN (0x1 << 10) |
1463 | #define RT5659_PM_HP_MASK (0x3 << 8) |
1464 | #define RT5659_PM_HP_SFT 8 |
1465 | #define RT5659_PM_HP_LV (0x0 << 8) |
1466 | #define RT5659_PM_HP_MV (0x1 << 8) |
1467 | #define RT5659_PM_HP_HV (0x2 << 8) |
1468 | #define RT5659_IB_HP_MASK (0x3 << 6) |
1469 | #define RT5659_IB_HP_SFT 6 |
1470 | #define RT5659_IB_HP_125IL (0x0 << 6) |
1471 | #define RT5659_IB_HP_25IL (0x1 << 6) |
1472 | #define RT5659_IB_HP_5IL (0x2 << 6) |
1473 | #define RT5659_IB_HP_1IL (0x3 << 6) |
1474 | |
1475 | /* PV detection and SPK gain control (0x92) */ |
1476 | #define RT5659_PVDD_DET_MASK (0x1 << 15) |
1477 | #define RT5659_PVDD_DET_SFT 15 |
1478 | #define RT5659_PVDD_DET_DIS (0x0 << 15) |
1479 | #define RT5659_PVDD_DET_EN (0x1 << 15) |
1480 | #define RT5659_SPK_AG_MASK (0x1 << 14) |
1481 | #define RT5659_SPK_AG_SFT 14 |
1482 | #define RT5659_SPK_AG_DIS (0x0 << 14) |
1483 | #define RT5659_SPK_AG_EN (0x1 << 14) |
1484 | |
1485 | /* Micbias Control (0x93) */ |
1486 | #define RT5659_MIC1_BS_MASK (0x1 << 15) |
1487 | #define RT5659_MIC1_BS_SFT 15 |
1488 | #define RT5659_MIC1_BS_9AV (0x0 << 15) |
1489 | #define RT5659_MIC1_BS_75AV (0x1 << 15) |
1490 | #define RT5659_MIC2_BS_MASK (0x1 << 14) |
1491 | #define RT5659_MIC2_BS_SFT 14 |
1492 | #define RT5659_MIC2_BS_9AV (0x0 << 14) |
1493 | #define RT5659_MIC2_BS_75AV (0x1 << 14) |
1494 | #define RT5659_MIC1_CLK_MASK (0x1 << 13) |
1495 | #define RT5659_MIC1_CLK_SFT 13 |
1496 | #define RT5659_MIC1_CLK_DIS (0x0 << 13) |
1497 | #define RT5659_MIC1_CLK_EN (0x1 << 13) |
1498 | #define RT5659_MIC2_CLK_MASK (0x1 << 12) |
1499 | #define RT5659_MIC2_CLK_SFT 12 |
1500 | #define RT5659_MIC2_CLK_DIS (0x0 << 12) |
1501 | #define RT5659_MIC2_CLK_EN (0x1 << 12) |
1502 | #define RT5659_MIC1_OVCD_MASK (0x1 << 11) |
1503 | #define RT5659_MIC1_OVCD_SFT 11 |
1504 | #define RT5659_MIC1_OVCD_DIS (0x0 << 11) |
1505 | #define RT5659_MIC1_OVCD_EN (0x1 << 11) |
1506 | #define RT5659_MIC1_OVTH_MASK (0x3 << 9) |
1507 | #define RT5659_MIC1_OVTH_SFT 9 |
1508 | #define RT5659_MIC1_OVTH_600UA (0x0 << 9) |
1509 | #define RT5659_MIC1_OVTH_1500UA (0x1 << 9) |
1510 | #define RT5659_MIC1_OVTH_2000UA (0x2 << 9) |
1511 | #define RT5659_MIC2_OVCD_MASK (0x1 << 8) |
1512 | #define RT5659_MIC2_OVCD_SFT 8 |
1513 | #define RT5659_MIC2_OVCD_DIS (0x0 << 8) |
1514 | #define RT5659_MIC2_OVCD_EN (0x1 << 8) |
1515 | #define RT5659_MIC2_OVTH_MASK (0x3 << 6) |
1516 | #define RT5659_MIC2_OVTH_SFT 6 |
1517 | #define RT5659_MIC2_OVTH_600UA (0x0 << 6) |
1518 | #define RT5659_MIC2_OVTH_1500UA (0x1 << 6) |
1519 | #define RT5659_MIC2_OVTH_2000UA (0x2 << 6) |
1520 | #define RT5659_PWR_MB_MASK (0x1 << 5) |
1521 | #define RT5659_PWR_MB_SFT 5 |
1522 | #define RT5659_PWR_MB_PD (0x0 << 5) |
1523 | #define RT5659_PWR_MB_PU (0x1 << 5) |
1524 | #define RT5659_PWR_CLK25M_MASK (0x1 << 4) |
1525 | #define RT5659_PWR_CLK25M_SFT 4 |
1526 | #define RT5659_PWR_CLK25M_PD (0x0 << 4) |
1527 | #define RT5659_PWR_CLK25M_PU (0x1 << 4) |
1528 | |
1529 | /* REC Mixer 2 Left Control 2 (0x009c) */ |
1530 | #define RT5659_M_BST1_RM2_L (0x1 << 5) |
1531 | #define RT5659_M_BST1_RM2_L_SFT 5 |
1532 | #define RT5659_M_BST2_RM2_L (0x1 << 4) |
1533 | #define RT5659_M_BST2_RM2_L_SFT 4 |
1534 | #define RT5659_M_BST3_RM2_L (0x1 << 3) |
1535 | #define RT5659_M_BST3_RM2_L_SFT 3 |
1536 | #define RT5659_M_BST4_RM2_L (0x1 << 2) |
1537 | #define RT5659_M_BST4_RM2_L_SFT 2 |
1538 | #define RT5659_M_OUTVOLL_RM2_L (0x1 << 1) |
1539 | #define RT5659_M_OUTVOLL_RM2_L_SFT 1 |
1540 | #define RT5659_M_SPKVOL_RM2_L (0x1) |
1541 | #define RT5659_M_SPKVOL_RM2_L_SFT 0 |
1542 | |
1543 | /* REC Mixer 2 Right Control 2 (0x009e) */ |
1544 | #define RT5659_M_BST1_RM2_R (0x1 << 5) |
1545 | #define RT5659_M_BST1_RM2_R_SFT 5 |
1546 | #define RT5659_M_BST2_RM2_R (0x1 << 4) |
1547 | #define RT5659_M_BST2_RM2_R_SFT 4 |
1548 | #define RT5659_M_BST3_RM2_R (0x1 << 3) |
1549 | #define RT5659_M_BST3_RM2_R_SFT 3 |
1550 | #define RT5659_M_BST4_RM2_R (0x1 << 2) |
1551 | #define RT5659_M_BST4_RM2_R_SFT 2 |
1552 | #define RT5659_M_OUTVOLR_RM2_R (0x1 << 1) |
1553 | #define RT5659_M_OUTVOLR_RM2_R_SFT 1 |
1554 | #define RT5659_M_MONOVOL_RM2_R (0x1) |
1555 | #define RT5659_M_MONOVOL_RM2_R_SFT 0 |
1556 | |
1557 | /* Class D Output Control (0x00a0) */ |
1558 | #define RT5659_POW_CLSD_DB_MASK (0x1 << 9) |
1559 | #define RT5659_POW_CLSD_DB_EN (0x1 << 9) |
1560 | #define RT5659_POW_CLSD_DB_DIS (0x0 << 9) |
1561 | |
1562 | /* EQ Control 1 (0x00b0) */ |
1563 | #define RT5659_EQ_SRC_DAC (0x0 << 15) |
1564 | #define RT5659_EQ_SRC_ADC (0x1 << 15) |
1565 | #define RT5659_EQ_UPD (0x1 << 14) |
1566 | #define RT5659_EQ_UPD_BIT 14 |
1567 | #define RT5659_EQ_CD_MASK (0x1 << 13) |
1568 | #define RT5659_EQ_CD_SFT 13 |
1569 | #define RT5659_EQ_CD_DIS (0x0 << 13) |
1570 | #define RT5659_EQ_CD_EN (0x1 << 13) |
1571 | #define RT5659_EQ_DITH_MASK (0x3 << 8) |
1572 | #define RT5659_EQ_DITH_SFT 8 |
1573 | #define RT5659_EQ_DITH_NOR (0x0 << 8) |
1574 | #define RT5659_EQ_DITH_LSB (0x1 << 8) |
1575 | #define RT5659_EQ_DITH_LSB_1 (0x2 << 8) |
1576 | #define RT5659_EQ_DITH_LSB_2 (0x3 << 8) |
1577 | |
1578 | /* IRQ Control 1 (0x00b7) */ |
1579 | #define RT5659_JD1_1_EN_MASK (0x1 << 15) |
1580 | #define RT5659_JD1_1_EN_SFT 15 |
1581 | #define RT5659_JD1_1_DIS (0x0 << 15) |
1582 | #define RT5659_JD1_1_EN (0x1 << 15) |
1583 | #define RT5659_JD1_2_EN_MASK (0x1 << 12) |
1584 | #define RT5659_JD1_2_EN_SFT 12 |
1585 | #define RT5659_JD1_2_DIS (0x0 << 12) |
1586 | #define RT5659_JD1_2_EN (0x1 << 12) |
1587 | #define RT5659_IL_IRQ_MASK (0x1 << 3) |
1588 | #define RT5659_IL_IRQ_DIS (0x0 << 3) |
1589 | #define RT5659_IL_IRQ_EN (0x1 << 3) |
1590 | |
1591 | /* IRQ Control 5 (0x00ba) */ |
1592 | #define RT5659_IRQ_JD_EN (0x1 << 3) |
1593 | #define RT5659_IRQ_JD_EN_SFT 3 |
1594 | |
1595 | /* GPIO Control 1 (0x00c0) */ |
1596 | #define RT5659_GP1_PIN_MASK (0x1 << 15) |
1597 | #define RT5659_GP1_PIN_SFT 15 |
1598 | #define RT5659_GP1_PIN_GPIO1 (0x0 << 15) |
1599 | #define RT5659_GP1_PIN_IRQ (0x1 << 15) |
1600 | #define RT5659_GP2_PIN_MASK (0x1 << 14) |
1601 | #define RT5659_GP2_PIN_SFT 14 |
1602 | #define RT5659_GP2_PIN_GPIO2 (0x0 << 14) |
1603 | #define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14) |
1604 | #define RT5659_GP3_PIN_MASK (0x1 << 13) |
1605 | #define RT5659_GP3_PIN_SFT 13 |
1606 | #define RT5659_GP3_PIN_GPIO3 (0x0 << 13) |
1607 | #define RT5659_GP3_PIN_PDM_SCL (0x1 << 13) |
1608 | #define RT5659_GP4_PIN_MASK (0x1 << 12) |
1609 | #define RT5659_GP4_PIN_SFT 12 |
1610 | #define RT5659_GP4_PIN_GPIO4 (0x0 << 12) |
1611 | #define RT5659_GP4_PIN_PDM_SDA (0x1 << 12) |
1612 | #define RT5659_GP5_PIN_MASK (0x1 << 11) |
1613 | #define RT5659_GP5_PIN_SFT 11 |
1614 | #define RT5659_GP5_PIN_GPIO5 (0x0 << 11) |
1615 | #define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11) |
1616 | #define RT5659_GP6_PIN_MASK (0x1 << 10) |
1617 | #define RT5659_GP6_PIN_SFT 10 |
1618 | #define RT5659_GP6_PIN_GPIO6 (0x0 << 10) |
1619 | #define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10) |
1620 | #define RT5659_GP7_PIN_MASK (0x1 << 9) |
1621 | #define RT5659_GP7_PIN_SFT 9 |
1622 | #define RT5659_GP7_PIN_GPIO7 (0x0 << 9) |
1623 | #define RT5659_GP7_PIN_PDM_SCL (0x1 << 9) |
1624 | #define RT5659_GP8_PIN_MASK (0x1 << 8) |
1625 | #define RT5659_GP8_PIN_SFT 8 |
1626 | #define RT5659_GP8_PIN_GPIO8 (0x0 << 8) |
1627 | #define RT5659_GP8_PIN_PDM_SDA (0x1 << 8) |
1628 | #define RT5659_GP9_PIN_MASK (0x1 << 7) |
1629 | #define RT5659_GP9_PIN_SFT 7 |
1630 | #define RT5659_GP9_PIN_GPIO9 (0x0 << 7) |
1631 | #define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7) |
1632 | #define RT5659_GP10_PIN_MASK (0x1 << 6) |
1633 | #define RT5659_GP10_PIN_SFT 6 |
1634 | #define RT5659_GP10_PIN_GPIO10 (0x0 << 6) |
1635 | #define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6) |
1636 | #define RT5659_GP11_PIN_MASK (0x1 << 5) |
1637 | #define RT5659_GP11_PIN_SFT 5 |
1638 | #define RT5659_GP11_PIN_GPIO11 (0x0 << 5) |
1639 | #define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5) |
1640 | #define RT5659_GP12_PIN_MASK (0x1 << 4) |
1641 | #define RT5659_GP12_PIN_SFT 4 |
1642 | #define RT5659_GP12_PIN_GPIO12 (0x0 << 4) |
1643 | #define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4) |
1644 | #define RT5659_GP13_PIN_MASK (0x3 << 2) |
1645 | #define RT5659_GP13_PIN_SFT 2 |
1646 | #define RT5659_GP13_PIN_GPIO13 (0x0 << 2) |
1647 | #define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2) |
1648 | #define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2) |
1649 | #define RT5659_GP13_PIN_PDM_SCL (0x3 << 2) |
1650 | #define RT5659_GP15_PIN_MASK (0x3) |
1651 | #define RT5659_GP15_PIN_SFT 0 |
1652 | #define RT5659_GP15_PIN_GPIO15 (0x0) |
1653 | #define RT5659_GP15_PIN_DMIC3_SCL (0x1) |
1654 | #define RT5659_GP15_PIN_PDM_SDA (0x2) |
1655 | |
1656 | /* GPIO Control 2 (0x00c1)*/ |
1657 | #define RT5659_GP1_PF_IN (0x0 << 2) |
1658 | #define RT5659_GP1_PF_OUT (0x1 << 2) |
1659 | #define RT5659_GP1_PF_MASK (0x1 << 2) |
1660 | #define RT5659_GP1_PF_SFT 2 |
1661 | |
1662 | /* GPIO Control 3 (0x00c2) */ |
1663 | #define RT5659_I2S2_PIN_MASK (0x1 << 15) |
1664 | #define RT5659_I2S2_PIN_SFT 15 |
1665 | #define RT5659_I2S2_PIN_I2S (0x0 << 15) |
1666 | #define RT5659_I2S2_PIN_GPIO (0x1 << 15) |
1667 | |
1668 | /* Soft volume and zero cross control 1 (0x00d9) */ |
1669 | #define RT5659_SV_MASK (0x1 << 15) |
1670 | #define RT5659_SV_SFT 15 |
1671 | #define RT5659_SV_DIS (0x0 << 15) |
1672 | #define RT5659_SV_EN (0x1 << 15) |
1673 | #define RT5659_OUT_SV_MASK (0x1 << 13) |
1674 | #define RT5659_OUT_SV_SFT 13 |
1675 | #define RT5659_OUT_SV_DIS (0x0 << 13) |
1676 | #define RT5659_OUT_SV_EN (0x1 << 13) |
1677 | #define RT5659_HP_SV_MASK (0x1 << 12) |
1678 | #define RT5659_HP_SV_SFT 12 |
1679 | #define RT5659_HP_SV_DIS (0x0 << 12) |
1680 | #define RT5659_HP_SV_EN (0x1 << 12) |
1681 | #define RT5659_ZCD_DIG_MASK (0x1 << 11) |
1682 | #define RT5659_ZCD_DIG_SFT 11 |
1683 | #define RT5659_ZCD_DIG_DIS (0x0 << 11) |
1684 | #define RT5659_ZCD_DIG_EN (0x1 << 11) |
1685 | #define RT5659_ZCD_MASK (0x1 << 10) |
1686 | #define RT5659_ZCD_SFT 10 |
1687 | #define RT5659_ZCD_PD (0x0 << 10) |
1688 | #define RT5659_ZCD_PU (0x1 << 10) |
1689 | #define RT5659_SV_DLY_MASK (0xf) |
1690 | #define RT5659_SV_DLY_SFT 0 |
1691 | |
1692 | /* Soft volume and zero cross control 2 (0x00da) */ |
1693 | #define RT5659_ZCD_HP_MASK (0x1 << 15) |
1694 | #define RT5659_ZCD_HP_SFT 15 |
1695 | #define RT5659_ZCD_HP_DIS (0x0 << 15) |
1696 | #define RT5659_ZCD_HP_EN (0x1 << 15) |
1697 | |
1698 | /* 4 Button Inline Command Control 2 (0x00e0) */ |
1699 | #define RT5659_4BTN_IL_MASK (0x1 << 15) |
1700 | #define RT5659_4BTN_IL_EN (0x1 << 15) |
1701 | #define RT5659_4BTN_IL_DIS (0x0 << 15) |
1702 | |
1703 | /* Analog JD Control 1 (0x00f0) */ |
1704 | #define RT5659_JD1_MODE_MASK (0x3 << 0) |
1705 | #define RT5659_JD1_MODE_0 (0x0 << 0) |
1706 | #define RT5659_JD1_MODE_1 (0x1 << 0) |
1707 | #define RT5659_JD1_MODE_2 (0x2 << 0) |
1708 | |
1709 | /* Jack Detect Control 3 (0x00f8) */ |
1710 | #define RT5659_JD_TRI_HPO_SEL_MASK (0x7) |
1711 | #define RT5659_JD_TRI_HPO_SEL_SFT (0) |
1712 | #define RT5659_JD_HPO_GPIO_JD1 (0x0) |
1713 | #define RT5659_JD_HPO_JD1_1 (0x1) |
1714 | #define RT5659_JD_HPO_JD1_2 (0x2) |
1715 | #define RT5659_JD_HPO_JD2 (0x3) |
1716 | #define RT5659_JD_HPO_GPIO_JD2 (0x4) |
1717 | #define RT5659_JD_HPO_JD3 (0x5) |
1718 | #define RT5659_JD_HPO_JD_D (0x6) |
1719 | |
1720 | /* Digital Misc Control (0x00fa) */ |
1721 | #define RT5659_AM_MASK (0x1 << 7) |
1722 | #define RT5659_AM_EN (0x1 << 7) |
1723 | #define RT5659_AM_DIS (0x1 << 7) |
1724 | #define RT5659_DIG_GATE_CTRL 0x1 |
1725 | #define RT5659_DIG_GATE_CTRL_SFT (0) |
1726 | |
1727 | /* Chopper and Clock control for ADC (0x011c)*/ |
1728 | #define RT5659_M_RF_DIG_MASK (0x1 << 12) |
1729 | #define RT5659_M_RF_DIG_SFT 12 |
1730 | #define RT5659_M_RI_DIG (0x1 << 11) |
1731 | |
1732 | /* Chopper and Clock control for DAC (0x013a)*/ |
1733 | #define RT5659_CKXEN_DAC1_MASK (0x1 << 13) |
1734 | #define RT5659_CKXEN_DAC1_SFT 13 |
1735 | #define RT5659_CKGEN_DAC1_MASK (0x1 << 12) |
1736 | #define RT5659_CKGEN_DAC1_SFT 12 |
1737 | #define RT5659_CKXEN_DAC2_MASK (0x1 << 5) |
1738 | #define RT5659_CKXEN_DAC2_SFT 5 |
1739 | #define RT5659_CKGEN_DAC2_MASK (0x1 << 4) |
1740 | #define RT5659_CKGEN_DAC2_SFT 4 |
1741 | |
1742 | /* Chopper and Clock control for ADC (0x013b)*/ |
1743 | #define RT5659_CKXEN_ADC1_MASK (0x1 << 13) |
1744 | #define RT5659_CKXEN_ADC1_SFT 13 |
1745 | #define RT5659_CKGEN_ADC1_MASK (0x1 << 12) |
1746 | #define RT5659_CKGEN_ADC1_SFT 12 |
1747 | #define RT5659_CKXEN_ADC2_MASK (0x1 << 5) |
1748 | #define RT5659_CKXEN_ADC2_SFT 5 |
1749 | #define RT5659_CKGEN_ADC2_MASK (0x1 << 4) |
1750 | #define RT5659_CKGEN_ADC2_SFT 4 |
1751 | |
1752 | /* Test Mode Control 1 (0x0145) */ |
1753 | #define RT5659_AD2DA_LB_MASK (0x1 << 9) |
1754 | #define RT5659_AD2DA_LB_SFT 9 |
1755 | |
1756 | /* Stereo Noise Gate Control 1 (0x0160) */ |
1757 | #define RT5659_NG2_EN_MASK (0x1 << 15) |
1758 | #define RT5659_NG2_EN (0x1 << 15) |
1759 | #define RT5659_NG2_DIS (0x0 << 15) |
1760 | |
1761 | /* System Clock Source */ |
1762 | enum { |
1763 | RT5659_SCLK_S_MCLK, |
1764 | RT5659_SCLK_S_PLL1, |
1765 | RT5659_SCLK_S_RCCLK, |
1766 | }; |
1767 | |
1768 | /* PLL1 Source */ |
1769 | enum { |
1770 | RT5659_PLL1_S_MCLK, |
1771 | RT5659_PLL1_S_BCLK1, |
1772 | RT5659_PLL1_S_BCLK2, |
1773 | RT5659_PLL1_S_BCLK3, |
1774 | RT5659_PLL1_S_BCLK4, |
1775 | }; |
1776 | |
1777 | enum { |
1778 | RT5659_AIF1, |
1779 | RT5659_AIF2, |
1780 | RT5659_AIF3, |
1781 | RT5659_AIF4, |
1782 | RT5659_AIFS, |
1783 | }; |
1784 | |
1785 | struct rt5659_pll_code { |
1786 | bool m_bp; |
1787 | int m_code; |
1788 | int n_code; |
1789 | int k_code; |
1790 | }; |
1791 | |
1792 | struct rt5659_priv { |
1793 | struct snd_soc_component *component; |
1794 | struct rt5659_platform_data pdata; |
1795 | struct regmap *regmap; |
1796 | struct gpio_desc *gpiod_ldo1_en; |
1797 | struct gpio_desc *gpiod_reset; |
1798 | struct snd_soc_jack *hs_jack; |
1799 | struct delayed_work jack_detect_work; |
1800 | struct clk *mclk; |
1801 | |
1802 | int sysclk; |
1803 | int sysclk_src; |
1804 | int lrck[RT5659_AIFS]; |
1805 | int bclk[RT5659_AIFS]; |
1806 | int master[RT5659_AIFS]; |
1807 | int v_id; |
1808 | |
1809 | int pll_src; |
1810 | int pll_in; |
1811 | int pll_out; |
1812 | |
1813 | int jack_type; |
1814 | bool hda_hp_plugged; |
1815 | bool hda_mic_plugged; |
1816 | }; |
1817 | |
1818 | int rt5659_set_jack_detect(struct snd_soc_component *component, |
1819 | struct snd_soc_jack *hs_jack); |
1820 | |
1821 | #endif /* __RT5659_H__ */ |
1822 | |