1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * rt5670.h -- RT5670 ALSA SoC audio driver
4 *
5 * Copyright 2014 Realtek Microelectronics
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9#ifndef __RT5670_H__
10#define __RT5670_H__
11
12/* Info */
13#define RT5670_RESET 0x00
14#define RT5670_VENDOR_ID 0xfd
15#define RT5670_VENDOR_ID1 0xfe
16#define RT5670_VENDOR_ID2 0xff
17/* I/O - Output */
18#define RT5670_HP_VOL 0x02
19#define RT5670_LOUT1 0x03
20/* I/O - Input */
21#define RT5670_CJ_CTRL1 0x0a
22#define RT5670_CJ_CTRL2 0x0b
23#define RT5670_CJ_CTRL3 0x0c
24#define RT5670_IN2 0x0e
25#define RT5670_INL1_INR1_VOL 0x0f
26/* I/O - ADC/DAC/DMIC */
27#define RT5670_DAC1_DIG_VOL 0x19
28#define RT5670_DAC2_DIG_VOL 0x1a
29#define RT5670_DAC_CTRL 0x1b
30#define RT5670_STO1_ADC_DIG_VOL 0x1c
31#define RT5670_MONO_ADC_DIG_VOL 0x1d
32#define RT5670_ADC_BST_VOL1 0x1e
33#define RT5670_STO2_ADC_DIG_VOL 0x1f
34/* Mixer - D-D */
35#define RT5670_ADC_BST_VOL2 0x20
36#define RT5670_STO2_ADC_MIXER 0x26
37#define RT5670_STO1_ADC_MIXER 0x27
38#define RT5670_MONO_ADC_MIXER 0x28
39#define RT5670_AD_DA_MIXER 0x29
40#define RT5670_STO_DAC_MIXER 0x2a
41#define RT5670_DD_MIXER 0x2b
42#define RT5670_DIG_MIXER 0x2c
43#define RT5670_DSP_PATH1 0x2d
44#define RT5670_DSP_PATH2 0x2e
45#define RT5670_DIG_INF1_DATA 0x2f
46#define RT5670_DIG_INF2_DATA 0x30
47/* Mixer - PDM */
48#define RT5670_PDM_OUT_CTRL 0x31
49#define RT5670_PDM_DATA_CTRL1 0x32
50#define RT5670_PDM1_DATA_CTRL2 0x33
51#define RT5670_PDM1_DATA_CTRL3 0x34
52#define RT5670_PDM1_DATA_CTRL4 0x35
53#define RT5670_PDM2_DATA_CTRL2 0x36
54#define RT5670_PDM2_DATA_CTRL3 0x37
55#define RT5670_PDM2_DATA_CTRL4 0x38
56/* Mixer - ADC */
57#define RT5670_REC_L1_MIXER 0x3b
58#define RT5670_REC_L2_MIXER 0x3c
59#define RT5670_REC_R1_MIXER 0x3d
60#define RT5670_REC_R2_MIXER 0x3e
61/* Mixer - DAC */
62#define RT5670_HPO_MIXER 0x45
63#define RT5670_MONO_MIXER 0x4c
64#define RT5670_OUT_L1_MIXER 0x4f
65#define RT5670_OUT_R1_MIXER 0x52
66#define RT5670_LOUT_MIXER 0x53
67/* Power */
68#define RT5670_PWR_DIG1 0x61
69#define RT5670_PWR_DIG2 0x62
70#define RT5670_PWR_ANLG1 0x63
71#define RT5670_PWR_ANLG2 0x64
72#define RT5670_PWR_MIXER 0x65
73#define RT5670_PWR_VOL 0x66
74/* Private Register Control */
75#define RT5670_PRIV_INDEX 0x6a
76#define RT5670_PRIV_DATA 0x6c
77/* Format - ADC/DAC */
78#define RT5670_I2S4_SDP 0x6f
79#define RT5670_I2S1_SDP 0x70
80#define RT5670_I2S2_SDP 0x71
81#define RT5670_I2S3_SDP 0x72
82#define RT5670_ADDA_CLK1 0x73
83#define RT5670_ADDA_CLK2 0x74
84#define RT5670_DMIC_CTRL1 0x75
85#define RT5670_DMIC_CTRL2 0x76
86/* Format - TDM Control */
87#define RT5670_TDM_CTRL_1 0x77
88#define RT5670_TDM_CTRL_2 0x78
89#define RT5670_TDM_CTRL_3 0x79
90
91/* Function - Analog */
92#define RT5670_DSP_CLK 0x7f
93#define RT5670_GLB_CLK 0x80
94#define RT5670_PLL_CTRL1 0x81
95#define RT5670_PLL_CTRL2 0x82
96#define RT5670_ASRC_1 0x83
97#define RT5670_ASRC_2 0x84
98#define RT5670_ASRC_3 0x85
99#define RT5670_ASRC_4 0x86
100#define RT5670_ASRC_5 0x87
101#define RT5670_ASRC_7 0x89
102#define RT5670_ASRC_8 0x8a
103#define RT5670_ASRC_9 0x8b
104#define RT5670_ASRC_10 0x8c
105#define RT5670_ASRC_11 0x8d
106#define RT5670_DEPOP_M1 0x8e
107#define RT5670_DEPOP_M2 0x8f
108#define RT5670_DEPOP_M3 0x90
109#define RT5670_CHARGE_PUMP 0x91
110#define RT5670_MICBIAS 0x93
111#define RT5670_A_JD_CTRL1 0x94
112#define RT5670_A_JD_CTRL2 0x95
113#define RT5670_ASRC_12 0x97
114#define RT5670_ASRC_13 0x98
115#define RT5670_ASRC_14 0x99
116#define RT5670_VAD_CTRL1 0x9a
117#define RT5670_VAD_CTRL2 0x9b
118#define RT5670_VAD_CTRL3 0x9c
119#define RT5670_VAD_CTRL4 0x9d
120#define RT5670_VAD_CTRL5 0x9e
121/* Function - Digital */
122#define RT5670_ADC_EQ_CTRL1 0xae
123#define RT5670_ADC_EQ_CTRL2 0xaf
124#define RT5670_EQ_CTRL1 0xb0
125#define RT5670_EQ_CTRL2 0xb1
126#define RT5670_ALC_DRC_CTRL1 0xb2
127#define RT5670_ALC_DRC_CTRL2 0xb3
128#define RT5670_ALC_CTRL_1 0xb4
129#define RT5670_ALC_CTRL_2 0xb5
130#define RT5670_ALC_CTRL_3 0xb6
131#define RT5670_ALC_CTRL_4 0xb7
132#define RT5670_JD_CTRL 0xbb
133#define RT5670_IRQ_CTRL1 0xbd
134#define RT5670_IRQ_CTRL2 0xbe
135#define RT5670_INT_IRQ_ST 0xbf
136#define RT5670_GPIO_CTRL1 0xc0
137#define RT5670_GPIO_CTRL2 0xc1
138#define RT5670_GPIO_CTRL3 0xc2
139#define RT5670_SCRABBLE_FUN 0xcd
140#define RT5670_SCRABBLE_CTRL 0xce
141#define RT5670_BASE_BACK 0xcf
142#define RT5670_MP3_PLUS1 0xd0
143#define RT5670_MP3_PLUS2 0xd1
144#define RT5670_ADJ_HPF1 0xd3
145#define RT5670_ADJ_HPF2 0xd4
146#define RT5670_HP_CALIB_AMP_DET 0xd6
147#define RT5670_SV_ZCD1 0xd9
148#define RT5670_SV_ZCD2 0xda
149#define RT5670_IL_CMD 0xdb
150#define RT5670_IL_CMD2 0xdc
151#define RT5670_IL_CMD3 0xdd
152#define RT5670_DRC_HL_CTRL1 0xe6
153#define RT5670_DRC_HL_CTRL2 0xe7
154#define RT5670_ADC_MONO_HP_CTRL1 0xec
155#define RT5670_ADC_MONO_HP_CTRL2 0xed
156#define RT5670_ADC_STO2_HP_CTRL1 0xee
157#define RT5670_ADC_STO2_HP_CTRL2 0xef
158#define RT5670_JD_CTRL3 0xf8
159#define RT5670_JD_CTRL4 0xf9
160/* General Control */
161#define RT5670_DIG_MISC 0xfa
162#define RT5670_GEN_CTRL2 0xfb
163#define RT5670_GEN_CTRL3 0xfc
164
165
166/* Index of Codec Private Register definition */
167#define RT5670_DIG_VOL 0x00
168#define RT5670_PR_ALC_CTRL_1 0x01
169#define RT5670_PR_ALC_CTRL_2 0x02
170#define RT5670_PR_ALC_CTRL_3 0x03
171#define RT5670_PR_ALC_CTRL_4 0x04
172#define RT5670_PR_ALC_CTRL_5 0x05
173#define RT5670_PR_ALC_CTRL_6 0x06
174#define RT5670_BIAS_CUR1 0x12
175#define RT5670_BIAS_CUR3 0x14
176#define RT5670_CLSD_INT_REG1 0x1c
177#define RT5670_MAMP_INT_REG2 0x37
178#define RT5670_CHOP_DAC_ADC 0x3d
179#define RT5670_MIXER_INT_REG 0x3f
180#define RT5670_3D_SPK 0x63
181#define RT5670_WND_1 0x6c
182#define RT5670_WND_2 0x6d
183#define RT5670_WND_3 0x6e
184#define RT5670_WND_4 0x6f
185#define RT5670_WND_5 0x70
186#define RT5670_WND_8 0x73
187#define RT5670_DIP_SPK_INF 0x75
188#define RT5670_HP_DCC_INT1 0x77
189#define RT5670_EQ_BW_LOP 0xa0
190#define RT5670_EQ_GN_LOP 0xa1
191#define RT5670_EQ_FC_BP1 0xa2
192#define RT5670_EQ_BW_BP1 0xa3
193#define RT5670_EQ_GN_BP1 0xa4
194#define RT5670_EQ_FC_BP2 0xa5
195#define RT5670_EQ_BW_BP2 0xa6
196#define RT5670_EQ_GN_BP2 0xa7
197#define RT5670_EQ_FC_BP3 0xa8
198#define RT5670_EQ_BW_BP3 0xa9
199#define RT5670_EQ_GN_BP3 0xaa
200#define RT5670_EQ_FC_BP4 0xab
201#define RT5670_EQ_BW_BP4 0xac
202#define RT5670_EQ_GN_BP4 0xad
203#define RT5670_EQ_FC_HIP1 0xae
204#define RT5670_EQ_GN_HIP1 0xaf
205#define RT5670_EQ_FC_HIP2 0xb0
206#define RT5670_EQ_BW_HIP2 0xb1
207#define RT5670_EQ_GN_HIP2 0xb2
208#define RT5670_EQ_PRE_VOL 0xb3
209#define RT5670_EQ_PST_VOL 0xb4
210
211
212/* global definition */
213#define RT5670_L_MUTE (0x1 << 15)
214#define RT5670_L_MUTE_SFT 15
215#define RT5670_R_MUTE (0x1 << 7)
216#define RT5670_R_MUTE_SFT 7
217#define RT5670_L_VOL_MASK (0x3f << 8)
218#define RT5670_L_VOL_SFT 8
219#define RT5670_R_VOL_MASK (0x3f)
220#define RT5670_R_VOL_SFT 0
221
222/* SW Reset & Device ID (0x00) */
223#define RT5670_ID_MASK (0x3 << 1)
224#define RT5670_ID_5670 (0x0 << 1)
225#define RT5670_ID_5672 (0x1 << 1)
226#define RT5670_ID_5671 (0x2 << 1)
227
228/* Combo Jack Control 1 (0x0a) */
229#define RT5670_CBJ_BST1_MASK (0xf << 12)
230#define RT5670_CBJ_BST1_SFT (12)
231#define RT5670_CBJ_JD_HP_EN (0x1 << 9)
232#define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
233#define RT5670_CBJ_BST1_EN (0x1 << 2)
234
235/* Combo Jack Control 1 (0x0b) */
236#define RT5670_CBJ_MN_JD (0x1 << 12)
237#define RT5670_CAPLESS_EN (0x1 << 11)
238#define RT5670_CBJ_DET_MODE (0x1 << 7)
239
240/* IN2 Control (0x0e) */
241#define RT5670_BST_MASK1 (0xf<<12)
242#define RT5670_BST_SFT1 12
243#define RT5670_BST_MASK2 (0xf<<8)
244#define RT5670_BST_SFT2 8
245#define RT5670_IN_DF1 (0x1 << 7)
246#define RT5670_IN_SFT1 7
247#define RT5670_IN_DF2 (0x1 << 6)
248#define RT5670_IN_SFT2 6
249
250/* INL and INR Volume Control (0x0f) */
251#define RT5670_INL_SEL_MASK (0x1 << 15)
252#define RT5670_INL_SEL_SFT 15
253#define RT5670_INL_SEL_IN4P (0x0 << 15)
254#define RT5670_INL_SEL_MONOP (0x1 << 15)
255#define RT5670_INL_VOL_MASK (0x1f << 8)
256#define RT5670_INL_VOL_SFT 8
257#define RT5670_INR_SEL_MASK (0x1 << 7)
258#define RT5670_INR_SEL_SFT 7
259#define RT5670_INR_SEL_IN4N (0x0 << 7)
260#define RT5670_INR_SEL_MONON (0x1 << 7)
261#define RT5670_INR_VOL_MASK (0x1f)
262#define RT5670_INR_VOL_SFT 0
263
264/* Sidetone Control (0x18) */
265#define RT5670_ST_SEL_MASK (0x7 << 9)
266#define RT5670_ST_SEL_SFT 9
267#define RT5670_M_ST_DACR2 (0x1 << 8)
268#define RT5670_M_ST_DACR2_SFT 8
269#define RT5670_M_ST_DACL2 (0x1 << 7)
270#define RT5670_M_ST_DACL2_SFT 7
271#define RT5670_ST_EN (0x1 << 6)
272#define RT5670_ST_EN_SFT 6
273
274/* DAC1 Digital Volume (0x19) */
275#define RT5670_DAC_L1_VOL_MASK (0xff << 8)
276#define RT5670_DAC_L1_VOL_SFT 8
277#define RT5670_DAC_R1_VOL_MASK (0xff)
278#define RT5670_DAC_R1_VOL_SFT 0
279
280/* DAC2 Digital Volume (0x1a) */
281#define RT5670_DAC_L2_VOL_MASK (0xff << 8)
282#define RT5670_DAC_L2_VOL_SFT 8
283#define RT5670_DAC_R2_VOL_MASK (0xff)
284#define RT5670_DAC_R2_VOL_SFT 0
285
286/* DAC2 Control (0x1b) */
287#define RT5670_M_DAC_L2_VOL (0x1 << 13)
288#define RT5670_M_DAC_L2_VOL_SFT 13
289#define RT5670_M_DAC_R2_VOL (0x1 << 12)
290#define RT5670_M_DAC_R2_VOL_SFT 12
291#define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
292#define RT5670_DAC2_L_SEL_SFT 4
293#define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
294#define RT5670_DAC2_R_SEL_SFT 0
295
296/* ADC Digital Volume Control (0x1c) */
297#define RT5670_ADC_L_VOL_MASK (0x7f << 8)
298#define RT5670_ADC_L_VOL_SFT 8
299#define RT5670_ADC_R_VOL_MASK (0x7f)
300#define RT5670_ADC_R_VOL_SFT 0
301
302/* Mono ADC Digital Volume Control (0x1d) */
303#define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
304#define RT5670_MONO_ADC_L_VOL_SFT 8
305#define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
306#define RT5670_MONO_ADC_R_VOL_SFT 0
307
308/* ADC Boost Volume Control (0x1e) */
309#define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
310#define RT5670_STO1_ADC_L_BST_SFT 14
311#define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
312#define RT5670_STO1_ADC_R_BST_SFT 12
313#define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
314#define RT5670_STO1_ADC_COMP_SFT 10
315#define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
316#define RT5670_STO2_ADC_L_BST_SFT 8
317#define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
318#define RT5670_STO2_ADC_R_BST_SFT 6
319#define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
320#define RT5670_STO2_ADC_COMP_SFT 4
321
322/* Stereo2 ADC Mixer Control (0x26) */
323#define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
324#define RT5670_STO2_ADC_SRC_SFT 15
325
326/* Stereo ADC Mixer Control (0x26 0x27) */
327#define RT5670_M_ADC_L1 (0x1 << 14)
328#define RT5670_M_ADC_L1_SFT 14
329#define RT5670_M_ADC_L2 (0x1 << 13)
330#define RT5670_M_ADC_L2_SFT 13
331#define RT5670_ADC_1_SRC_MASK (0x1 << 12)
332#define RT5670_ADC_1_SRC_SFT 12
333#define RT5670_ADC_1_SRC_ADC (0x1 << 12)
334#define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
335#define RT5670_ADC_2_SRC_MASK (0x1 << 11)
336#define RT5670_ADC_2_SRC_SFT 11
337#define RT5670_ADC_SRC_MASK (0x1 << 10)
338#define RT5670_ADC_SRC_SFT 10
339#define RT5670_DMIC_SRC_MASK (0x3 << 8)
340#define RT5670_DMIC_SRC_SFT 8
341#define RT5670_M_ADC_R1 (0x1 << 6)
342#define RT5670_M_ADC_R1_SFT 6
343#define RT5670_M_ADC_R2 (0x1 << 5)
344#define RT5670_M_ADC_R2_SFT 5
345#define RT5670_DMIC3_SRC_MASK (0x1 << 1)
346#define RT5670_DMIC3_SRC_SFT 0
347
348/* Mono ADC Mixer Control (0x28) */
349#define RT5670_M_MONO_ADC_L1 (0x1 << 14)
350#define RT5670_M_MONO_ADC_L1_SFT 14
351#define RT5670_M_MONO_ADC_L2 (0x1 << 13)
352#define RT5670_M_MONO_ADC_L2_SFT 13
353#define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
354#define RT5670_MONO_ADC_L1_SRC_SFT 12
355#define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
356#define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
357#define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
358#define RT5670_MONO_ADC_L2_SRC_SFT 11
359#define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
360#define RT5670_MONO_ADC_L_SRC_SFT 10
361#define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
362#define RT5670_MONO_DMIC_L_SRC_SFT 8
363#define RT5670_M_MONO_ADC_R1 (0x1 << 6)
364#define RT5670_M_MONO_ADC_R1_SFT 6
365#define RT5670_M_MONO_ADC_R2 (0x1 << 5)
366#define RT5670_M_MONO_ADC_R2_SFT 5
367#define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
368#define RT5670_MONO_ADC_R1_SRC_SFT 4
369#define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
370#define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
371#define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
372#define RT5670_MONO_ADC_R2_SRC_SFT 3
373#define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
374#define RT5670_MONO_DMIC_R_SRC_SFT 0
375
376/* ADC Mixer to DAC Mixer Control (0x29) */
377#define RT5670_M_ADCMIX_L (0x1 << 15)
378#define RT5670_M_ADCMIX_L_SFT 15
379#define RT5670_M_DAC1_L (0x1 << 14)
380#define RT5670_M_DAC1_L_SFT 14
381#define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
382#define RT5670_DAC1_R_SEL_SFT 10
383#define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
384#define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
385#define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
386#define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
387#define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
388#define RT5670_DAC1_L_SEL_SFT 8
389#define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
390#define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
391#define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
392#define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
393#define RT5670_M_ADCMIX_R (0x1 << 7)
394#define RT5670_M_ADCMIX_R_SFT 7
395#define RT5670_M_DAC1_R (0x1 << 6)
396#define RT5670_M_DAC1_R_SFT 6
397
398/* Stereo DAC Mixer Control (0x2a) */
399#define RT5670_M_DAC_L1 (0x1 << 14)
400#define RT5670_M_DAC_L1_SFT 14
401#define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
402#define RT5670_DAC_L1_STO_L_VOL_SFT 13
403#define RT5670_M_DAC_L2 (0x1 << 12)
404#define RT5670_M_DAC_L2_SFT 12
405#define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
406#define RT5670_DAC_L2_STO_L_VOL_SFT 11
407#define RT5670_M_DAC_R1_STO_L (0x1 << 9)
408#define RT5670_M_DAC_R1_STO_L_SFT 9
409#define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
410#define RT5670_DAC_R1_STO_L_VOL_SFT 8
411#define RT5670_M_DAC_R1 (0x1 << 6)
412#define RT5670_M_DAC_R1_SFT 6
413#define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
414#define RT5670_DAC_R1_STO_R_VOL_SFT 5
415#define RT5670_M_DAC_R2 (0x1 << 4)
416#define RT5670_M_DAC_R2_SFT 4
417#define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
418#define RT5670_DAC_R2_STO_R_VOL_SFT 3
419#define RT5670_M_DAC_L1_STO_R (0x1 << 1)
420#define RT5670_M_DAC_L1_STO_R_SFT 1
421#define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
422#define RT5670_DAC_L1_STO_R_VOL_SFT 0
423
424/* Mono DAC Mixer Control (0x2b) */
425#define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
426#define RT5670_M_DAC_L1_MONO_L_SFT 14
427#define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
428#define RT5670_DAC_L1_MONO_L_VOL_SFT 13
429#define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
430#define RT5670_M_DAC_L2_MONO_L_SFT 12
431#define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
432#define RT5670_DAC_L2_MONO_L_VOL_SFT 11
433#define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
434#define RT5670_M_DAC_R2_MONO_L_SFT 10
435#define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
436#define RT5670_DAC_R2_MONO_L_VOL_SFT 9
437#define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
438#define RT5670_M_DAC_R1_MONO_R_SFT 6
439#define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
440#define RT5670_DAC_R1_MONO_R_VOL_SFT 5
441#define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
442#define RT5670_M_DAC_R2_MONO_R_SFT 4
443#define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
444#define RT5670_DAC_R2_MONO_R_VOL_SFT 3
445#define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
446#define RT5670_M_DAC_L2_MONO_R_SFT 2
447#define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
448#define RT5670_DAC_L2_MONO_R_VOL_SFT 1
449
450/* Digital Mixer Control (0x2c) */
451#define RT5670_M_STO_L_DAC_L (0x1 << 15)
452#define RT5670_M_STO_L_DAC_L_SFT 15
453#define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
454#define RT5670_STO_L_DAC_L_VOL_SFT 14
455#define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
456#define RT5670_M_DAC_L2_DAC_L_SFT 13
457#define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
458#define RT5670_DAC_L2_DAC_L_VOL_SFT 12
459#define RT5670_M_STO_R_DAC_R (0x1 << 11)
460#define RT5670_M_STO_R_DAC_R_SFT 11
461#define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
462#define RT5670_STO_R_DAC_R_VOL_SFT 10
463#define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
464#define RT5670_M_DAC_R2_DAC_R_SFT 9
465#define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
466#define RT5670_DAC_R2_DAC_R_VOL_SFT 8
467#define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
468#define RT5670_M_DAC_R2_DAC_L_SFT 7
469#define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
470#define RT5670_DAC_R2_DAC_L_VOL_SFT 6
471#define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
472#define RT5670_M_DAC_L2_DAC_R_SFT 5
473#define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
474#define RT5670_DAC_L2_DAC_R_VOL_SFT 4
475
476/* DSP Path Control 1 (0x2d) */
477#define RT5670_RXDP_SEL_MASK (0x7 << 13)
478#define RT5670_RXDP_SEL_SFT 13
479#define RT5670_RXDP_SRC_MASK (0x3 << 11)
480#define RT5670_RXDP_SRC_SFT 11
481#define RT5670_RXDP_SRC_NOR (0x0 << 11)
482#define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
483#define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
484#define RT5670_TXDP_SRC_MASK (0x3 << 4)
485#define RT5670_TXDP_SRC_SFT 4
486#define RT5670_TXDP_SRC_NOR (0x0 << 4)
487#define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
488#define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
489#define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
490#define RT5670_TXDP_SLOT_SEL_SFT 2
491#define RT5670_DSP_UL_SEL (0x1 << 1)
492#define RT5670_DSP_UL_SFT 1
493#define RT5670_DSP_DL_SEL 0x1
494#define RT5670_DSP_DL_SFT 0
495
496/* DSP Path Control 2 (0x2e) */
497#define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
498#define RT5670_TXDP_L_VOL_SFT 8
499#define RT5670_TXDP_R_VOL_MASK (0x7f)
500#define RT5670_TXDP_R_VOL_SFT 0
501
502/* Digital Interface Data Control (0x2f) */
503#define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
504#define RT5670_IF1_ADC2_IN_SFT 15
505#define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
506#define RT5670_IF2_ADC_IN_SFT 12
507#define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
508#define RT5670_IF2_DAC_SEL_SFT 10
509#define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
510#define RT5670_IF2_ADC_SEL_SFT 8
511
512/* Digital Interface Data Control (0x30) */
513#define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
514#define RT5670_IF4_ADC_IN_SFT 4
515
516/* PDM Output Control (0x31) */
517#define RT5670_PDM1_L_MASK (0x1 << 15)
518#define RT5670_PDM1_L_SFT 15
519#define RT5670_M_PDM1_L (0x1 << 14)
520#define RT5670_M_PDM1_L_SFT 14
521#define RT5670_PDM1_R_MASK (0x1 << 13)
522#define RT5670_PDM1_R_SFT 13
523#define RT5670_M_PDM1_R (0x1 << 12)
524#define RT5670_M_PDM1_R_SFT 12
525#define RT5670_PDM2_L_MASK (0x1 << 11)
526#define RT5670_PDM2_L_SFT 11
527#define RT5670_M_PDM2_L (0x1 << 10)
528#define RT5670_M_PDM2_L_SFT 10
529#define RT5670_PDM2_R_MASK (0x1 << 9)
530#define RT5670_PDM2_R_SFT 9
531#define RT5670_M_PDM2_R (0x1 << 8)
532#define RT5670_M_PDM2_R_SFT 8
533#define RT5670_PDM2_BUSY (0x1 << 7)
534#define RT5670_PDM1_BUSY (0x1 << 6)
535#define RT5670_PDM_PATTERN (0x1 << 5)
536#define RT5670_PDM_GAIN (0x1 << 4)
537#define RT5670_PDM_DIV_MASK (0x3)
538
539/* REC Left Mixer Control 1 (0x3b) */
540#define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
541#define RT5670_G_HP_L_RM_L_SFT 13
542#define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
543#define RT5670_G_IN_L_RM_L_SFT 10
544#define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
545#define RT5670_G_BST4_RM_L_SFT 7
546#define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
547#define RT5670_G_BST3_RM_L_SFT 4
548#define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
549#define RT5670_G_BST2_RM_L_SFT 1
550
551/* REC Left Mixer Control 2 (0x3c) */
552#define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
553#define RT5670_G_BST1_RM_L_SFT 13
554#define RT5670_M_IN_L_RM_L (0x1 << 5)
555#define RT5670_M_IN_L_RM_L_SFT 5
556#define RT5670_M_BST2_RM_L (0x1 << 3)
557#define RT5670_M_BST2_RM_L_SFT 3
558#define RT5670_M_BST1_RM_L (0x1 << 1)
559#define RT5670_M_BST1_RM_L_SFT 1
560
561/* REC Right Mixer Control 1 (0x3d) */
562#define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
563#define RT5670_G_HP_R_RM_R_SFT 13
564#define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
565#define RT5670_G_IN_R_RM_R_SFT 10
566#define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
567#define RT5670_G_BST4_RM_R_SFT 7
568#define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
569#define RT5670_G_BST3_RM_R_SFT 4
570#define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
571#define RT5670_G_BST2_RM_R_SFT 1
572
573/* REC Right Mixer Control 2 (0x3e) */
574#define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
575#define RT5670_G_BST1_RM_R_SFT 13
576#define RT5670_M_IN_R_RM_R (0x1 << 5)
577#define RT5670_M_IN_R_RM_R_SFT 5
578#define RT5670_M_BST2_RM_R (0x1 << 3)
579#define RT5670_M_BST2_RM_R_SFT 3
580#define RT5670_M_BST1_RM_R (0x1 << 1)
581#define RT5670_M_BST1_RM_R_SFT 1
582
583/* HPMIX Control (0x45) */
584#define RT5670_M_DAC2_HM (0x1 << 15)
585#define RT5670_M_DAC2_HM_SFT 15
586#define RT5670_M_HPVOL_HM (0x1 << 14)
587#define RT5670_M_HPVOL_HM_SFT 14
588#define RT5670_M_DAC1_HM (0x1 << 13)
589#define RT5670_M_DAC1_HM_SFT 13
590#define RT5670_G_HPOMIX_MASK (0x1 << 12)
591#define RT5670_G_HPOMIX_SFT 12
592#define RT5670_M_INR1_HMR (0x1 << 3)
593#define RT5670_M_INR1_HMR_SFT 3
594#define RT5670_M_DACR1_HMR (0x1 << 2)
595#define RT5670_M_DACR1_HMR_SFT 2
596#define RT5670_M_INL1_HML (0x1 << 1)
597#define RT5670_M_INL1_HML_SFT 1
598#define RT5670_M_DACL1_HML (0x1)
599#define RT5670_M_DACL1_HML_SFT 0
600
601/* Mono Output Mixer Control (0x4c) */
602#define RT5670_M_DAC_R2_MA (0x1 << 15)
603#define RT5670_M_DAC_R2_MA_SFT 15
604#define RT5670_M_DAC_L2_MA (0x1 << 14)
605#define RT5670_M_DAC_L2_MA_SFT 14
606#define RT5670_M_OV_R_MM (0x1 << 13)
607#define RT5670_M_OV_R_MM_SFT 13
608#define RT5670_M_OV_L_MM (0x1 << 12)
609#define RT5670_M_OV_L_MM_SFT 12
610#define RT5670_G_MONOMIX_MASK (0x1 << 10)
611#define RT5670_G_MONOMIX_SFT 10
612#define RT5670_M_DAC_R2_MM (0x1 << 9)
613#define RT5670_M_DAC_R2_MM_SFT 9
614#define RT5670_M_DAC_L2_MM (0x1 << 8)
615#define RT5670_M_DAC_L2_MM_SFT 8
616#define RT5670_M_BST4_MM (0x1 << 7)
617#define RT5670_M_BST4_MM_SFT 7
618
619/* Output Left Mixer Control 1 (0x4d) */
620#define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
621#define RT5670_G_BST3_OM_L_SFT 13
622#define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
623#define RT5670_G_BST2_OM_L_SFT 10
624#define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
625#define RT5670_G_BST1_OM_L_SFT 7
626#define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
627#define RT5670_G_IN_L_OM_L_SFT 4
628#define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
629#define RT5670_G_RM_L_OM_L_SFT 1
630
631/* Output Left Mixer Control 2 (0x4e) */
632#define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
633#define RT5670_G_DAC_R2_OM_L_SFT 13
634#define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
635#define RT5670_G_DAC_L2_OM_L_SFT 10
636#define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
637#define RT5670_G_DAC_L1_OM_L_SFT 7
638
639/* Output Left Mixer Control 3 (0x4f) */
640#define RT5670_M_BST1_OM_L (0x1 << 5)
641#define RT5670_M_BST1_OM_L_SFT 5
642#define RT5670_M_IN_L_OM_L (0x1 << 4)
643#define RT5670_M_IN_L_OM_L_SFT 4
644#define RT5670_M_DAC_L2_OM_L (0x1 << 1)
645#define RT5670_M_DAC_L2_OM_L_SFT 1
646#define RT5670_M_DAC_L1_OM_L (0x1)
647#define RT5670_M_DAC_L1_OM_L_SFT 0
648
649/* Output Right Mixer Control 1 (0x50) */
650#define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
651#define RT5670_G_BST4_OM_R_SFT 13
652#define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
653#define RT5670_G_BST2_OM_R_SFT 10
654#define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
655#define RT5670_G_BST1_OM_R_SFT 7
656#define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
657#define RT5670_G_IN_R_OM_R_SFT 4
658#define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
659#define RT5670_G_RM_R_OM_R_SFT 1
660
661/* Output Right Mixer Control 2 (0x51) */
662#define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
663#define RT5670_G_DAC_L2_OM_R_SFT 13
664#define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
665#define RT5670_G_DAC_R2_OM_R_SFT 10
666#define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
667#define RT5670_G_DAC_R1_OM_R_SFT 7
668
669/* Output Right Mixer Control 3 (0x52) */
670#define RT5670_M_BST2_OM_R (0x1 << 6)
671#define RT5670_M_BST2_OM_R_SFT 6
672#define RT5670_M_IN_R_OM_R (0x1 << 4)
673#define RT5670_M_IN_R_OM_R_SFT 4
674#define RT5670_M_DAC_R2_OM_R (0x1 << 1)
675#define RT5670_M_DAC_R2_OM_R_SFT 1
676#define RT5670_M_DAC_R1_OM_R (0x1)
677#define RT5670_M_DAC_R1_OM_R_SFT 0
678
679/* LOUT Mixer Control (0x53) */
680#define RT5670_M_DAC_L1_LM (0x1 << 15)
681#define RT5670_M_DAC_L1_LM_SFT 15
682#define RT5670_M_DAC_R1_LM (0x1 << 14)
683#define RT5670_M_DAC_R1_LM_SFT 14
684#define RT5670_M_OV_L_LM (0x1 << 13)
685#define RT5670_M_OV_L_LM_SFT 13
686#define RT5670_M_OV_R_LM (0x1 << 12)
687#define RT5670_M_OV_R_LM_SFT 12
688#define RT5670_G_LOUTMIX_MASK (0x1 << 11)
689#define RT5670_G_LOUTMIX_SFT 11
690
691/* Power Management for Digital 1 (0x61) */
692#define RT5670_PWR_I2S1 (0x1 << 15)
693#define RT5670_PWR_I2S1_BIT 15
694#define RT5670_PWR_I2S2 (0x1 << 14)
695#define RT5670_PWR_I2S2_BIT 14
696#define RT5670_PWR_DAC_L1 (0x1 << 12)
697#define RT5670_PWR_DAC_L1_BIT 12
698#define RT5670_PWR_DAC_R1 (0x1 << 11)
699#define RT5670_PWR_DAC_R1_BIT 11
700#define RT5670_PWR_DAC_L2 (0x1 << 7)
701#define RT5670_PWR_DAC_L2_BIT 7
702#define RT5670_PWR_DAC_R2 (0x1 << 6)
703#define RT5670_PWR_DAC_R2_BIT 6
704#define RT5670_PWR_ADC_L (0x1 << 2)
705#define RT5670_PWR_ADC_L_BIT 2
706#define RT5670_PWR_ADC_R (0x1 << 1)
707#define RT5670_PWR_ADC_R_BIT 1
708#define RT5670_PWR_CLS_D (0x1)
709#define RT5670_PWR_CLS_D_BIT 0
710
711/* Power Management for Digital 2 (0x62) */
712#define RT5670_PWR_ADC_S1F (0x1 << 15)
713#define RT5670_PWR_ADC_S1F_BIT 15
714#define RT5670_PWR_ADC_MF_L (0x1 << 14)
715#define RT5670_PWR_ADC_MF_L_BIT 14
716#define RT5670_PWR_ADC_MF_R (0x1 << 13)
717#define RT5670_PWR_ADC_MF_R_BIT 13
718#define RT5670_PWR_I2S_DSP (0x1 << 12)
719#define RT5670_PWR_I2S_DSP_BIT 12
720#define RT5670_PWR_DAC_S1F (0x1 << 11)
721#define RT5670_PWR_DAC_S1F_BIT 11
722#define RT5670_PWR_DAC_MF_L (0x1 << 10)
723#define RT5670_PWR_DAC_MF_L_BIT 10
724#define RT5670_PWR_DAC_MF_R (0x1 << 9)
725#define RT5670_PWR_DAC_MF_R_BIT 9
726#define RT5670_PWR_ADC_S2F (0x1 << 8)
727#define RT5670_PWR_ADC_S2F_BIT 8
728#define RT5670_PWR_PDM1 (0x1 << 7)
729#define RT5670_PWR_PDM1_BIT 7
730#define RT5670_PWR_PDM2 (0x1 << 6)
731#define RT5670_PWR_PDM2_BIT 6
732
733/* Power Management for Analog 1 (0x63) */
734#define RT5670_PWR_VREF1 (0x1 << 15)
735#define RT5670_PWR_VREF1_BIT 15
736#define RT5670_PWR_FV1 (0x1 << 14)
737#define RT5670_PWR_FV1_BIT 14
738#define RT5670_PWR_MB (0x1 << 13)
739#define RT5670_PWR_MB_BIT 13
740#define RT5670_PWR_LM (0x1 << 12)
741#define RT5670_PWR_LM_BIT 12
742#define RT5670_PWR_BG (0x1 << 11)
743#define RT5670_PWR_BG_BIT 11
744#define RT5670_PWR_HP_L (0x1 << 7)
745#define RT5670_PWR_HP_L_BIT 7
746#define RT5670_PWR_HP_R (0x1 << 6)
747#define RT5670_PWR_HP_R_BIT 6
748#define RT5670_PWR_HA (0x1 << 5)
749#define RT5670_PWR_HA_BIT 5
750#define RT5670_PWR_VREF2 (0x1 << 4)
751#define RT5670_PWR_VREF2_BIT 4
752#define RT5670_PWR_FV2 (0x1 << 3)
753#define RT5670_PWR_FV2_BIT 3
754#define RT5670_LDO_SEL_MASK (0x7)
755#define RT5670_LDO_SEL_SFT 0
756
757/* Power Management for Analog 2 (0x64) */
758#define RT5670_PWR_BST1 (0x1 << 15)
759#define RT5670_PWR_BST1_BIT 15
760#define RT5670_PWR_BST2 (0x1 << 13)
761#define RT5670_PWR_BST2_BIT 13
762#define RT5670_PWR_MB1 (0x1 << 11)
763#define RT5670_PWR_MB1_BIT 11
764#define RT5670_PWR_MB2 (0x1 << 10)
765#define RT5670_PWR_MB2_BIT 10
766#define RT5670_PWR_PLL (0x1 << 9)
767#define RT5670_PWR_PLL_BIT 9
768#define RT5670_PWR_BST1_P (0x1 << 6)
769#define RT5670_PWR_BST1_P_BIT 6
770#define RT5670_PWR_BST2_P (0x1 << 4)
771#define RT5670_PWR_BST2_P_BIT 4
772#define RT5670_PWR_JD1 (0x1 << 2)
773#define RT5670_PWR_JD1_BIT 2
774#define RT5670_PWR_JD (0x1 << 1)
775#define RT5670_PWR_JD_BIT 1
776
777/* Power Management for Mixer (0x65) */
778#define RT5670_PWR_OM_L (0x1 << 15)
779#define RT5670_PWR_OM_L_BIT 15
780#define RT5670_PWR_OM_R (0x1 << 14)
781#define RT5670_PWR_OM_R_BIT 14
782#define RT5670_PWR_RM_L (0x1 << 11)
783#define RT5670_PWR_RM_L_BIT 11
784#define RT5670_PWR_RM_R (0x1 << 10)
785#define RT5670_PWR_RM_R_BIT 10
786
787/* Power Management for Volume (0x66) */
788#define RT5670_PWR_HV_L (0x1 << 11)
789#define RT5670_PWR_HV_L_BIT 11
790#define RT5670_PWR_HV_R (0x1 << 10)
791#define RT5670_PWR_HV_R_BIT 10
792#define RT5670_PWR_IN_L (0x1 << 9)
793#define RT5670_PWR_IN_L_BIT 9
794#define RT5670_PWR_IN_R (0x1 << 8)
795#define RT5670_PWR_IN_R_BIT 8
796#define RT5670_PWR_MIC_DET (0x1 << 5)
797#define RT5670_PWR_MIC_DET_BIT 5
798
799/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
800#define RT5670_I2S_MS_MASK (0x1 << 15)
801#define RT5670_I2S_MS_SFT 15
802#define RT5670_I2S_MS_M (0x0 << 15)
803#define RT5670_I2S_MS_S (0x1 << 15)
804#define RT5670_I2S_IF_MASK (0x7 << 12)
805#define RT5670_I2S_IF_SFT 12
806#define RT5670_I2S_O_CP_MASK (0x3 << 10)
807#define RT5670_I2S_O_CP_SFT 10
808#define RT5670_I2S_O_CP_OFF (0x0 << 10)
809#define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
810#define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
811#define RT5670_I2S_I_CP_MASK (0x3 << 8)
812#define RT5670_I2S_I_CP_SFT 8
813#define RT5670_I2S_I_CP_OFF (0x0 << 8)
814#define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
815#define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
816#define RT5670_I2S_BP_MASK (0x1 << 7)
817#define RT5670_I2S_BP_SFT 7
818#define RT5670_I2S_BP_NOR (0x0 << 7)
819#define RT5670_I2S_BP_INV (0x1 << 7)
820#define RT5670_I2S_DL_MASK (0x3 << 2)
821#define RT5670_I2S_DL_SFT 2
822#define RT5670_I2S_DL_16 (0x0 << 2)
823#define RT5670_I2S_DL_20 (0x1 << 2)
824#define RT5670_I2S_DL_24 (0x2 << 2)
825#define RT5670_I2S_DL_8 (0x3 << 2)
826#define RT5670_I2S_DF_MASK (0x3)
827#define RT5670_I2S_DF_SFT 0
828#define RT5670_I2S_DF_I2S (0x0)
829#define RT5670_I2S_DF_LEFT (0x1)
830#define RT5670_I2S_DF_PCM_A (0x2)
831#define RT5670_I2S_DF_PCM_B (0x3)
832
833/* I2S2 Audio Serial Data Port Control (0x71) */
834#define RT5670_I2S2_SDI_MASK (0x1 << 6)
835#define RT5670_I2S2_SDI_SFT 6
836#define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
837#define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
838
839/* ADC/DAC Clock Control 1 (0x73) */
840#define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
841#define RT5670_I2S_BCLK_MS1_SFT 15
842#define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
843#define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
844#define RT5670_I2S_PD1_MASK (0x7 << 12)
845#define RT5670_I2S_PD1_SFT 12
846#define RT5670_I2S_PD1_1 (0x0 << 12)
847#define RT5670_I2S_PD1_2 (0x1 << 12)
848#define RT5670_I2S_PD1_3 (0x2 << 12)
849#define RT5670_I2S_PD1_4 (0x3 << 12)
850#define RT5670_I2S_PD1_6 (0x4 << 12)
851#define RT5670_I2S_PD1_8 (0x5 << 12)
852#define RT5670_I2S_PD1_12 (0x6 << 12)
853#define RT5670_I2S_PD1_16 (0x7 << 12)
854#define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
855#define RT5670_I2S_BCLK_MS2_SFT 11
856#define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
857#define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
858#define RT5670_I2S_PD2_MASK (0x7 << 8)
859#define RT5670_I2S_PD2_SFT 8
860#define RT5670_I2S_PD2_1 (0x0 << 8)
861#define RT5670_I2S_PD2_2 (0x1 << 8)
862#define RT5670_I2S_PD2_3 (0x2 << 8)
863#define RT5670_I2S_PD2_4 (0x3 << 8)
864#define RT5670_I2S_PD2_6 (0x4 << 8)
865#define RT5670_I2S_PD2_8 (0x5 << 8)
866#define RT5670_I2S_PD2_12 (0x6 << 8)
867#define RT5670_I2S_PD2_16 (0x7 << 8)
868#define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
869#define RT5670_I2S_BCLK_MS3_SFT 7
870#define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
871#define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
872#define RT5670_I2S_PD3_MASK (0x7 << 4)
873#define RT5670_I2S_PD3_SFT 4
874#define RT5670_I2S_PD3_1 (0x0 << 4)
875#define RT5670_I2S_PD3_2 (0x1 << 4)
876#define RT5670_I2S_PD3_3 (0x2 << 4)
877#define RT5670_I2S_PD3_4 (0x3 << 4)
878#define RT5670_I2S_PD3_6 (0x4 << 4)
879#define RT5670_I2S_PD3_8 (0x5 << 4)
880#define RT5670_I2S_PD3_12 (0x6 << 4)
881#define RT5670_I2S_PD3_16 (0x7 << 4)
882#define RT5670_DAC_OSR_MASK (0x3 << 2)
883#define RT5670_DAC_OSR_SFT 2
884#define RT5670_DAC_OSR_128 (0x0 << 2)
885#define RT5670_DAC_OSR_64 (0x1 << 2)
886#define RT5670_DAC_OSR_32 (0x2 << 2)
887#define RT5670_DAC_OSR_16 (0x3 << 2)
888#define RT5670_ADC_OSR_MASK (0x3)
889#define RT5670_ADC_OSR_SFT 0
890#define RT5670_ADC_OSR_128 (0x0)
891#define RT5670_ADC_OSR_64 (0x1)
892#define RT5670_ADC_OSR_32 (0x2)
893#define RT5670_ADC_OSR_16 (0x3)
894
895/* ADC/DAC Clock Control 2 (0x74) */
896#define RT5670_DAC_L_OSR_MASK (0x3 << 14)
897#define RT5670_DAC_L_OSR_SFT 14
898#define RT5670_DAC_L_OSR_128 (0x0 << 14)
899#define RT5670_DAC_L_OSR_64 (0x1 << 14)
900#define RT5670_DAC_L_OSR_32 (0x2 << 14)
901#define RT5670_DAC_L_OSR_16 (0x3 << 14)
902#define RT5670_ADC_R_OSR_MASK (0x3 << 12)
903#define RT5670_ADC_R_OSR_SFT 12
904#define RT5670_ADC_R_OSR_128 (0x0 << 12)
905#define RT5670_ADC_R_OSR_64 (0x1 << 12)
906#define RT5670_ADC_R_OSR_32 (0x2 << 12)
907#define RT5670_ADC_R_OSR_16 (0x3 << 12)
908#define RT5670_DAHPF_EN (0x1 << 11)
909#define RT5670_DAHPF_EN_SFT 11
910#define RT5670_ADHPF_EN (0x1 << 10)
911#define RT5670_ADHPF_EN_SFT 10
912
913/* Digital Microphone Control (0x75) */
914#define RT5670_DMIC_1_EN_MASK (0x1 << 15)
915#define RT5670_DMIC_1_EN_SFT 15
916#define RT5670_DMIC_1_DIS (0x0 << 15)
917#define RT5670_DMIC_1_EN (0x1 << 15)
918#define RT5670_DMIC_2_EN_MASK (0x1 << 14)
919#define RT5670_DMIC_2_EN_SFT 14
920#define RT5670_DMIC_2_DIS (0x0 << 14)
921#define RT5670_DMIC_2_EN (0x1 << 14)
922#define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
923#define RT5670_DMIC_1L_LH_SFT 13
924#define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
925#define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
926#define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
927#define RT5670_DMIC_1R_LH_SFT 12
928#define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
929#define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
930#define RT5670_DMIC_2_DP_MASK (0x1 << 10)
931#define RT5670_DMIC_2_DP_SFT 10
932#define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
933#define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
934#define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
935#define RT5670_DMIC_2L_LH_SFT 9
936#define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
937#define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
938#define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
939#define RT5670_DMIC_2R_LH_SFT 8
940#define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
941#define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
942#define RT5670_DMIC_CLK_MASK (0x7 << 5)
943#define RT5670_DMIC_CLK_SFT 5
944#define RT5670_DMIC_3_EN_MASK (0x1 << 4)
945#define RT5670_DMIC_3_EN_SFT 4
946#define RT5670_DMIC_3_DIS (0x0 << 4)
947#define RT5670_DMIC_3_EN (0x1 << 4)
948#define RT5670_DMIC_1_DP_MASK (0x3 << 0)
949#define RT5670_DMIC_1_DP_SFT 0
950#define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
951#define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
952#define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
953
954/* Digital Microphone Control2 (0x76) */
955#define RT5670_DMIC_3_DP_MASK (0x3 << 6)
956#define RT5670_DMIC_3_DP_SFT 6
957#define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
958#define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
959#define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
960
961/* Global Clock Control (0x80) */
962#define RT5670_SCLK_SRC_MASK (0x3 << 14)
963#define RT5670_SCLK_SRC_SFT 14
964#define RT5670_SCLK_SRC_MCLK (0x0 << 14)
965#define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
966#define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
967#define RT5670_PLL1_SRC_MASK (0x7 << 11)
968#define RT5670_PLL1_SRC_SFT 11
969#define RT5670_PLL1_SRC_MCLK (0x0 << 11)
970#define RT5670_PLL1_SRC_BCLK1 (0x1 << 11)
971#define RT5670_PLL1_SRC_BCLK2 (0x2 << 11)
972#define RT5670_PLL1_SRC_BCLK3 (0x3 << 11)
973#define RT5670_PLL1_PD_MASK (0x1 << 3)
974#define RT5670_PLL1_PD_SFT 3
975#define RT5670_PLL1_PD_1 (0x0 << 3)
976#define RT5670_PLL1_PD_2 (0x1 << 3)
977
978#define RT5670_PLL_INP_MAX 40000000
979#define RT5670_PLL_INP_MIN 256000
980/* PLL M/N/K Code Control 1 (0x81) */
981#define RT5670_PLL_N_MAX 0x1ff
982#define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7)
983#define RT5670_PLL_N_SFT 7
984#define RT5670_PLL_K_MAX 0x1f
985#define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX)
986#define RT5670_PLL_K_SFT 0
987
988/* PLL M/N/K Code Control 2 (0x82) */
989#define RT5670_PLL_M_MAX 0xf
990#define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
991#define RT5670_PLL_M_SFT 12
992#define RT5670_PLL_M_BP (0x1 << 11)
993#define RT5670_PLL_M_BP_SFT 11
994
995/* ASRC Control 1 (0x83) */
996#define RT5670_STO_T_MASK (0x1 << 15)
997#define RT5670_STO_T_SFT 15
998#define RT5670_STO_T_SCLK (0x0 << 15)
999#define RT5670_STO_T_LRCK1 (0x1 << 15)
1000#define RT5670_M1_T_MASK (0x1 << 14)
1001#define RT5670_M1_T_SFT 14
1002#define RT5670_M1_T_I2S2 (0x0 << 14)
1003#define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1004#define RT5670_I2S2_F_MASK (0x1 << 12)
1005#define RT5670_I2S2_F_SFT 12
1006#define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
1007#define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1008#define RT5670_DMIC_1_M_MASK (0x1 << 9)
1009#define RT5670_DMIC_1_M_SFT 9
1010#define RT5670_DMIC_1_M_NOR (0x0 << 9)
1011#define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1012#define RT5670_DMIC_2_M_MASK (0x1 << 8)
1013#define RT5670_DMIC_2_M_SFT 8
1014#define RT5670_DMIC_2_M_NOR (0x0 << 8)
1015#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1016
1017/* ASRC clock source selection (0x84, 0x85) */
1018#define RT5670_CLK_SEL_SYS (0x0)
1019#define RT5670_CLK_SEL_I2S1_ASRC (0x1)
1020#define RT5670_CLK_SEL_I2S2_ASRC (0x2)
1021#define RT5670_CLK_SEL_I2S3_ASRC (0x3)
1022#define RT5670_CLK_SEL_SYS2 (0x5)
1023#define RT5670_CLK_SEL_SYS3 (0x6)
1024
1025/* ASRC Control 2 (0x84) */
1026#define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
1027#define RT5670_DA_STO_CLK_SEL_SFT 12
1028#define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1029#define RT5670_DA_MONOL_CLK_SEL_SFT 8
1030#define RT5670_DA_MONOR_CLK_SEL_MASK (0xf << 4)
1031#define RT5670_DA_MONOR_CLK_SEL_SFT 4
1032#define RT5670_AD_STO1_CLK_SEL_MASK (0xf << 0)
1033#define RT5670_AD_STO1_CLK_SEL_SFT 0
1034
1035/* ASRC Control 3 (0x85) */
1036#define RT5670_UP_CLK_SEL_MASK (0xf << 12)
1037#define RT5670_UP_CLK_SEL_SFT 12
1038#define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
1039#define RT5670_DOWN_CLK_SEL_SFT 8
1040#define RT5670_AD_MONOL_CLK_SEL_MASK (0xf << 4)
1041#define RT5670_AD_MONOL_CLK_SEL_SFT 4
1042#define RT5670_AD_MONOR_CLK_SEL_MASK (0xf << 0)
1043#define RT5670_AD_MONOR_CLK_SEL_SFT 0
1044
1045/* ASRC Control 4 (0x89) */
1046#define RT5670_I2S1_PD_MASK (0x7 << 12)
1047#define RT5670_I2S1_PD_SFT 12
1048#define RT5670_I2S2_PD_MASK (0x7 << 8)
1049#define RT5670_I2S2_PD_SFT 8
1050
1051/* HPOUT Over Current Detection (0x8b) */
1052#define RT5670_HP_OVCD_MASK (0x1 << 10)
1053#define RT5670_HP_OVCD_SFT 10
1054#define RT5670_HP_OVCD_DIS (0x0 << 10)
1055#define RT5670_HP_OVCD_EN (0x1 << 10)
1056#define RT5670_HP_OC_TH_MASK (0x3 << 8)
1057#define RT5670_HP_OC_TH_SFT 8
1058#define RT5670_HP_OC_TH_90 (0x0 << 8)
1059#define RT5670_HP_OC_TH_105 (0x1 << 8)
1060#define RT5670_HP_OC_TH_120 (0x2 << 8)
1061#define RT5670_HP_OC_TH_135 (0x3 << 8)
1062
1063/* Class D Over Current Control (0x8c) */
1064#define RT5670_CLSD_OC_MASK (0x1 << 9)
1065#define RT5670_CLSD_OC_SFT 9
1066#define RT5670_CLSD_OC_PU (0x0 << 9)
1067#define RT5670_CLSD_OC_PD (0x1 << 9)
1068#define RT5670_AUTO_PD_MASK (0x1 << 8)
1069#define RT5670_AUTO_PD_SFT 8
1070#define RT5670_AUTO_PD_DIS (0x0 << 8)
1071#define RT5670_AUTO_PD_EN (0x1 << 8)
1072#define RT5670_CLSD_OC_TH_MASK (0x3f)
1073#define RT5670_CLSD_OC_TH_SFT 0
1074
1075/* Class D Output Control (0x8d) */
1076#define RT5670_CLSD_RATIO_MASK (0xf << 12)
1077#define RT5670_CLSD_RATIO_SFT 12
1078#define RT5670_CLSD_OM_MASK (0x1 << 11)
1079#define RT5670_CLSD_OM_SFT 11
1080#define RT5670_CLSD_OM_MONO (0x0 << 11)
1081#define RT5670_CLSD_OM_STO (0x1 << 11)
1082#define RT5670_CLSD_SCH_MASK (0x1 << 10)
1083#define RT5670_CLSD_SCH_SFT 10
1084#define RT5670_CLSD_SCH_L (0x0 << 10)
1085#define RT5670_CLSD_SCH_S (0x1 << 10)
1086
1087/* Depop Mode Control 1 (0x8e) */
1088#define RT5670_SMT_TRIG_MASK (0x1 << 15)
1089#define RT5670_SMT_TRIG_SFT 15
1090#define RT5670_SMT_TRIG_DIS (0x0 << 15)
1091#define RT5670_SMT_TRIG_EN (0x1 << 15)
1092#define RT5670_HP_L_SMT_MASK (0x1 << 9)
1093#define RT5670_HP_L_SMT_SFT 9
1094#define RT5670_HP_L_SMT_DIS (0x0 << 9)
1095#define RT5670_HP_L_SMT_EN (0x1 << 9)
1096#define RT5670_HP_R_SMT_MASK (0x1 << 8)
1097#define RT5670_HP_R_SMT_SFT 8
1098#define RT5670_HP_R_SMT_DIS (0x0 << 8)
1099#define RT5670_HP_R_SMT_EN (0x1 << 8)
1100#define RT5670_HP_CD_PD_MASK (0x1 << 7)
1101#define RT5670_HP_CD_PD_SFT 7
1102#define RT5670_HP_CD_PD_DIS (0x0 << 7)
1103#define RT5670_HP_CD_PD_EN (0x1 << 7)
1104#define RT5670_RSTN_MASK (0x1 << 6)
1105#define RT5670_RSTN_SFT 6
1106#define RT5670_RSTN_DIS (0x0 << 6)
1107#define RT5670_RSTN_EN (0x1 << 6)
1108#define RT5670_RSTP_MASK (0x1 << 5)
1109#define RT5670_RSTP_SFT 5
1110#define RT5670_RSTP_DIS (0x0 << 5)
1111#define RT5670_RSTP_EN (0x1 << 5)
1112#define RT5670_HP_CO_MASK (0x1 << 4)
1113#define RT5670_HP_CO_SFT 4
1114#define RT5670_HP_CO_DIS (0x0 << 4)
1115#define RT5670_HP_CO_EN (0x1 << 4)
1116#define RT5670_HP_CP_MASK (0x1 << 3)
1117#define RT5670_HP_CP_SFT 3
1118#define RT5670_HP_CP_PD (0x0 << 3)
1119#define RT5670_HP_CP_PU (0x1 << 3)
1120#define RT5670_HP_SG_MASK (0x1 << 2)
1121#define RT5670_HP_SG_SFT 2
1122#define RT5670_HP_SG_DIS (0x0 << 2)
1123#define RT5670_HP_SG_EN (0x1 << 2)
1124#define RT5670_HP_DP_MASK (0x1 << 1)
1125#define RT5670_HP_DP_SFT 1
1126#define RT5670_HP_DP_PD (0x0 << 1)
1127#define RT5670_HP_DP_PU (0x1 << 1)
1128#define RT5670_HP_CB_MASK (0x1)
1129#define RT5670_HP_CB_SFT 0
1130#define RT5670_HP_CB_PD (0x0)
1131#define RT5670_HP_CB_PU (0x1)
1132
1133/* Depop Mode Control 2 (0x8f) */
1134#define RT5670_DEPOP_MASK (0x1 << 13)
1135#define RT5670_DEPOP_SFT 13
1136#define RT5670_DEPOP_AUTO (0x0 << 13)
1137#define RT5670_DEPOP_MAN (0x1 << 13)
1138#define RT5670_RAMP_MASK (0x1 << 12)
1139#define RT5670_RAMP_SFT 12
1140#define RT5670_RAMP_DIS (0x0 << 12)
1141#define RT5670_RAMP_EN (0x1 << 12)
1142#define RT5670_BPS_MASK (0x1 << 11)
1143#define RT5670_BPS_SFT 11
1144#define RT5670_BPS_DIS (0x0 << 11)
1145#define RT5670_BPS_EN (0x1 << 11)
1146#define RT5670_FAST_UPDN_MASK (0x1 << 10)
1147#define RT5670_FAST_UPDN_SFT 10
1148#define RT5670_FAST_UPDN_DIS (0x0 << 10)
1149#define RT5670_FAST_UPDN_EN (0x1 << 10)
1150#define RT5670_MRES_MASK (0x3 << 8)
1151#define RT5670_MRES_SFT 8
1152#define RT5670_MRES_15MO (0x0 << 8)
1153#define RT5670_MRES_25MO (0x1 << 8)
1154#define RT5670_MRES_35MO (0x2 << 8)
1155#define RT5670_MRES_45MO (0x3 << 8)
1156#define RT5670_VLO_MASK (0x1 << 7)
1157#define RT5670_VLO_SFT 7
1158#define RT5670_VLO_3V (0x0 << 7)
1159#define RT5670_VLO_32V (0x1 << 7)
1160#define RT5670_DIG_DP_MASK (0x1 << 6)
1161#define RT5670_DIG_DP_SFT 6
1162#define RT5670_DIG_DP_DIS (0x0 << 6)
1163#define RT5670_DIG_DP_EN (0x1 << 6)
1164#define RT5670_DP_TH_MASK (0x3 << 4)
1165#define RT5670_DP_TH_SFT 4
1166
1167/* Depop Mode Control 3 (0x90) */
1168#define RT5670_CP_SYS_MASK (0x7 << 12)
1169#define RT5670_CP_SYS_SFT 12
1170#define RT5670_CP_FQ1_MASK (0x7 << 8)
1171#define RT5670_CP_FQ1_SFT 8
1172#define RT5670_CP_FQ2_MASK (0x7 << 4)
1173#define RT5670_CP_FQ2_SFT 4
1174#define RT5670_CP_FQ3_MASK (0x7)
1175#define RT5670_CP_FQ3_SFT 0
1176#define RT5670_CP_FQ_1_5_KHZ 0
1177#define RT5670_CP_FQ_3_KHZ 1
1178#define RT5670_CP_FQ_6_KHZ 2
1179#define RT5670_CP_FQ_12_KHZ 3
1180#define RT5670_CP_FQ_24_KHZ 4
1181#define RT5670_CP_FQ_48_KHZ 5
1182#define RT5670_CP_FQ_96_KHZ 6
1183#define RT5670_CP_FQ_192_KHZ 7
1184
1185/* HPOUT charge pump (0x91) */
1186#define RT5670_OSW_L_MASK (0x1 << 11)
1187#define RT5670_OSW_L_SFT 11
1188#define RT5670_OSW_L_DIS (0x0 << 11)
1189#define RT5670_OSW_L_EN (0x1 << 11)
1190#define RT5670_OSW_R_MASK (0x1 << 10)
1191#define RT5670_OSW_R_SFT 10
1192#define RT5670_OSW_R_DIS (0x0 << 10)
1193#define RT5670_OSW_R_EN (0x1 << 10)
1194#define RT5670_PM_HP_MASK (0x3 << 8)
1195#define RT5670_PM_HP_SFT 8
1196#define RT5670_PM_HP_LV (0x0 << 8)
1197#define RT5670_PM_HP_MV (0x1 << 8)
1198#define RT5670_PM_HP_HV (0x2 << 8)
1199#define RT5670_IB_HP_MASK (0x3 << 6)
1200#define RT5670_IB_HP_SFT 6
1201#define RT5670_IB_HP_125IL (0x0 << 6)
1202#define RT5670_IB_HP_25IL (0x1 << 6)
1203#define RT5670_IB_HP_5IL (0x2 << 6)
1204#define RT5670_IB_HP_1IL (0x3 << 6)
1205
1206/* PV detection and SPK gain control (0x92) */
1207#define RT5670_PVDD_DET_MASK (0x1 << 15)
1208#define RT5670_PVDD_DET_SFT 15
1209#define RT5670_PVDD_DET_DIS (0x0 << 15)
1210#define RT5670_PVDD_DET_EN (0x1 << 15)
1211#define RT5670_SPK_AG_MASK (0x1 << 14)
1212#define RT5670_SPK_AG_SFT 14
1213#define RT5670_SPK_AG_DIS (0x0 << 14)
1214#define RT5670_SPK_AG_EN (0x1 << 14)
1215
1216/* Micbias Control (0x93) */
1217#define RT5670_MIC1_BS_MASK (0x1 << 15)
1218#define RT5670_MIC1_BS_SFT 15
1219#define RT5670_MIC1_BS_9AV (0x0 << 15)
1220#define RT5670_MIC1_BS_75AV (0x1 << 15)
1221#define RT5670_MIC2_BS_MASK (0x1 << 14)
1222#define RT5670_MIC2_BS_SFT 14
1223#define RT5670_MIC2_BS_9AV (0x0 << 14)
1224#define RT5670_MIC2_BS_75AV (0x1 << 14)
1225#define RT5670_MIC1_CLK_MASK (0x1 << 13)
1226#define RT5670_MIC1_CLK_SFT 13
1227#define RT5670_MIC1_CLK_DIS (0x0 << 13)
1228#define RT5670_MIC1_CLK_EN (0x1 << 13)
1229#define RT5670_MIC2_CLK_MASK (0x1 << 12)
1230#define RT5670_MIC2_CLK_SFT 12
1231#define RT5670_MIC2_CLK_DIS (0x0 << 12)
1232#define RT5670_MIC2_CLK_EN (0x1 << 12)
1233#define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1234#define RT5670_MIC1_OVCD_SFT 11
1235#define RT5670_MIC1_OVCD_DIS (0x0 << 11)
1236#define RT5670_MIC1_OVCD_EN (0x1 << 11)
1237#define RT5670_MIC1_OVTH_MASK (0x3 << 9)
1238#define RT5670_MIC1_OVTH_SFT 9
1239#define RT5670_MIC1_OVTH_600UA (0x0 << 9)
1240#define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1241#define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
1242#define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1243#define RT5670_MIC2_OVCD_SFT 8
1244#define RT5670_MIC2_OVCD_DIS (0x0 << 8)
1245#define RT5670_MIC2_OVCD_EN (0x1 << 8)
1246#define RT5670_MIC2_OVTH_MASK (0x3 << 6)
1247#define RT5670_MIC2_OVTH_SFT 6
1248#define RT5670_MIC2_OVTH_600UA (0x0 << 6)
1249#define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1250#define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
1251#define RT5670_PWR_MB_MASK (0x1 << 5)
1252#define RT5670_PWR_MB_SFT 5
1253#define RT5670_PWR_MB_PD (0x0 << 5)
1254#define RT5670_PWR_MB_PU (0x1 << 5)
1255#define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1256#define RT5670_PWR_CLK25M_SFT 4
1257#define RT5670_PWR_CLK25M_PD (0x0 << 4)
1258#define RT5670_PWR_CLK25M_PU (0x1 << 4)
1259
1260/* Analog JD Control 1 (0x94) */
1261#define RT5670_JD1_MODE_MASK (0x3 << 0)
1262#define RT5670_JD1_MODE_0 (0x0 << 0)
1263#define RT5670_JD1_MODE_1 (0x1 << 0)
1264#define RT5670_JD1_MODE_2 (0x2 << 0)
1265
1266/* VAD Control 4 (0x9d) */
1267#define RT5670_VAD_SEL_MASK (0x3 << 8)
1268#define RT5670_VAD_SEL_SFT 8
1269
1270/* EQ Control 1 (0xb0) */
1271#define RT5670_EQ_SRC_MASK (0x1 << 15)
1272#define RT5670_EQ_SRC_SFT 15
1273#define RT5670_EQ_SRC_DAC (0x0 << 15)
1274#define RT5670_EQ_SRC_ADC (0x1 << 15)
1275#define RT5670_EQ_UPD (0x1 << 14)
1276#define RT5670_EQ_UPD_BIT 14
1277#define RT5670_EQ_CD_MASK (0x1 << 13)
1278#define RT5670_EQ_CD_SFT 13
1279#define RT5670_EQ_CD_DIS (0x0 << 13)
1280#define RT5670_EQ_CD_EN (0x1 << 13)
1281#define RT5670_EQ_DITH_MASK (0x3 << 8)
1282#define RT5670_EQ_DITH_SFT 8
1283#define RT5670_EQ_DITH_NOR (0x0 << 8)
1284#define RT5670_EQ_DITH_LSB (0x1 << 8)
1285#define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
1286#define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
1287
1288/* EQ Control 2 (0xb1) */
1289#define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1290#define RT5670_EQ_HPF1_M_SFT 8
1291#define RT5670_EQ_HPF1_M_HI (0x0 << 8)
1292#define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1293#define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1294#define RT5670_EQ_LPF1_M_SFT 7
1295#define RT5670_EQ_LPF1_M_LO (0x0 << 7)
1296#define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1297#define RT5670_EQ_HPF2_MASK (0x1 << 6)
1298#define RT5670_EQ_HPF2_SFT 6
1299#define RT5670_EQ_HPF2_DIS (0x0 << 6)
1300#define RT5670_EQ_HPF2_EN (0x1 << 6)
1301#define RT5670_EQ_HPF1_MASK (0x1 << 5)
1302#define RT5670_EQ_HPF1_SFT 5
1303#define RT5670_EQ_HPF1_DIS (0x0 << 5)
1304#define RT5670_EQ_HPF1_EN (0x1 << 5)
1305#define RT5670_EQ_BPF4_MASK (0x1 << 4)
1306#define RT5670_EQ_BPF4_SFT 4
1307#define RT5670_EQ_BPF4_DIS (0x0 << 4)
1308#define RT5670_EQ_BPF4_EN (0x1 << 4)
1309#define RT5670_EQ_BPF3_MASK (0x1 << 3)
1310#define RT5670_EQ_BPF3_SFT 3
1311#define RT5670_EQ_BPF3_DIS (0x0 << 3)
1312#define RT5670_EQ_BPF3_EN (0x1 << 3)
1313#define RT5670_EQ_BPF2_MASK (0x1 << 2)
1314#define RT5670_EQ_BPF2_SFT 2
1315#define RT5670_EQ_BPF2_DIS (0x0 << 2)
1316#define RT5670_EQ_BPF2_EN (0x1 << 2)
1317#define RT5670_EQ_BPF1_MASK (0x1 << 1)
1318#define RT5670_EQ_BPF1_SFT 1
1319#define RT5670_EQ_BPF1_DIS (0x0 << 1)
1320#define RT5670_EQ_BPF1_EN (0x1 << 1)
1321#define RT5670_EQ_LPF_MASK (0x1)
1322#define RT5670_EQ_LPF_SFT 0
1323#define RT5670_EQ_LPF_DIS (0x0)
1324#define RT5670_EQ_LPF_EN (0x1)
1325#define RT5670_EQ_CTRL_MASK (0x7f)
1326
1327/* Memory Test (0xb2) */
1328#define RT5670_MT_MASK (0x1 << 15)
1329#define RT5670_MT_SFT 15
1330#define RT5670_MT_DIS (0x0 << 15)
1331#define RT5670_MT_EN (0x1 << 15)
1332
1333/* DRC/AGC Control 1 (0xb4) */
1334#define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1335#define RT5670_DRC_AGC_P_SFT 15
1336#define RT5670_DRC_AGC_P_DAC (0x0 << 15)
1337#define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1338#define RT5670_DRC_AGC_MASK (0x1 << 14)
1339#define RT5670_DRC_AGC_SFT 14
1340#define RT5670_DRC_AGC_DIS (0x0 << 14)
1341#define RT5670_DRC_AGC_EN (0x1 << 14)
1342#define RT5670_DRC_AGC_UPD (0x1 << 13)
1343#define RT5670_DRC_AGC_UPD_BIT 13
1344#define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
1345#define RT5670_DRC_AGC_AR_SFT 8
1346#define RT5670_DRC_AGC_R_MASK (0x7 << 5)
1347#define RT5670_DRC_AGC_R_SFT 5
1348#define RT5670_DRC_AGC_R_48K (0x1 << 5)
1349#define RT5670_DRC_AGC_R_96K (0x2 << 5)
1350#define RT5670_DRC_AGC_R_192K (0x3 << 5)
1351#define RT5670_DRC_AGC_R_441K (0x5 << 5)
1352#define RT5670_DRC_AGC_R_882K (0x6 << 5)
1353#define RT5670_DRC_AGC_R_1764K (0x7 << 5)
1354#define RT5670_DRC_AGC_RC_MASK (0x1f)
1355#define RT5670_DRC_AGC_RC_SFT 0
1356
1357/* DRC/AGC Control 2 (0xb5) */
1358#define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
1359#define RT5670_DRC_AGC_POB_SFT 8
1360#define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1361#define RT5670_DRC_AGC_CP_SFT 7
1362#define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
1363#define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1364#define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
1365#define RT5670_DRC_AGC_CPR_SFT 5
1366#define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
1367#define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1368#define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
1369#define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
1370#define RT5670_DRC_AGC_PRB_MASK (0x1f)
1371#define RT5670_DRC_AGC_PRB_SFT 0
1372
1373/* DRC/AGC Control 3 (0xb6) */
1374#define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
1375#define RT5670_DRC_AGC_NGB_SFT 12
1376#define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
1377#define RT5670_DRC_AGC_TAR_SFT 7
1378#define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1379#define RT5670_DRC_AGC_NG_SFT 6
1380#define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
1381#define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1382#define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1383#define RT5670_DRC_AGC_NGH_SFT 5
1384#define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
1385#define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1386#define RT5670_DRC_AGC_NGT_MASK (0x1f)
1387#define RT5670_DRC_AGC_NGT_SFT 0
1388
1389/* Jack Detect Control (0xbb) */
1390#define RT5670_JD_MASK (0x7 << 13)
1391#define RT5670_JD_SFT 13
1392#define RT5670_JD_DIS (0x0 << 13)
1393#define RT5670_JD_GPIO1 (0x1 << 13)
1394#define RT5670_JD_JD1_IN4P (0x2 << 13)
1395#define RT5670_JD_JD2_IN4N (0x3 << 13)
1396#define RT5670_JD_GPIO2 (0x4 << 13)
1397#define RT5670_JD_GPIO3 (0x5 << 13)
1398#define RT5670_JD_GPIO4 (0x6 << 13)
1399#define RT5670_JD_HP_MASK (0x1 << 11)
1400#define RT5670_JD_HP_SFT 11
1401#define RT5670_JD_HP_DIS (0x0 << 11)
1402#define RT5670_JD_HP_EN (0x1 << 11)
1403#define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1404#define RT5670_JD_HP_TRG_SFT 10
1405#define RT5670_JD_HP_TRG_LO (0x0 << 10)
1406#define RT5670_JD_HP_TRG_HI (0x1 << 10)
1407#define RT5670_JD_SPL_MASK (0x1 << 9)
1408#define RT5670_JD_SPL_SFT 9
1409#define RT5670_JD_SPL_DIS (0x0 << 9)
1410#define RT5670_JD_SPL_EN (0x1 << 9)
1411#define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1412#define RT5670_JD_SPL_TRG_SFT 8
1413#define RT5670_JD_SPL_TRG_LO (0x0 << 8)
1414#define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1415#define RT5670_JD_SPR_MASK (0x1 << 7)
1416#define RT5670_JD_SPR_SFT 7
1417#define RT5670_JD_SPR_DIS (0x0 << 7)
1418#define RT5670_JD_SPR_EN (0x1 << 7)
1419#define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1420#define RT5670_JD_SPR_TRG_SFT 6
1421#define RT5670_JD_SPR_TRG_LO (0x0 << 6)
1422#define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1423#define RT5670_JD_MO_MASK (0x1 << 5)
1424#define RT5670_JD_MO_SFT 5
1425#define RT5670_JD_MO_DIS (0x0 << 5)
1426#define RT5670_JD_MO_EN (0x1 << 5)
1427#define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1428#define RT5670_JD_MO_TRG_SFT 4
1429#define RT5670_JD_MO_TRG_LO (0x0 << 4)
1430#define RT5670_JD_MO_TRG_HI (0x1 << 4)
1431#define RT5670_JD_LO_MASK (0x1 << 3)
1432#define RT5670_JD_LO_SFT 3
1433#define RT5670_JD_LO_DIS (0x0 << 3)
1434#define RT5670_JD_LO_EN (0x1 << 3)
1435#define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1436#define RT5670_JD_LO_TRG_SFT 2
1437#define RT5670_JD_LO_TRG_LO (0x0 << 2)
1438#define RT5670_JD_LO_TRG_HI (0x1 << 2)
1439#define RT5670_JD1_IN4P_MASK (0x1 << 1)
1440#define RT5670_JD1_IN4P_SFT 1
1441#define RT5670_JD1_IN4P_DIS (0x0 << 1)
1442#define RT5670_JD1_IN4P_EN (0x1 << 1)
1443#define RT5670_JD2_IN4N_MASK (0x1)
1444#define RT5670_JD2_IN4N_SFT 0
1445#define RT5670_JD2_IN4N_DIS (0x0)
1446#define RT5670_JD2_IN4N_EN (0x1)
1447
1448/* IRQ Control 1 (0xbd) */
1449#define RT5670_IRQ_JD_MASK (0x1 << 15)
1450#define RT5670_IRQ_JD_SFT 15
1451#define RT5670_IRQ_JD_BP (0x0 << 15)
1452#define RT5670_IRQ_JD_NOR (0x1 << 15)
1453#define RT5670_IRQ_OT_MASK (0x1 << 14)
1454#define RT5670_IRQ_OT_SFT 14
1455#define RT5670_IRQ_OT_BP (0x0 << 14)
1456#define RT5670_IRQ_OT_NOR (0x1 << 14)
1457#define RT5670_JD_STKY_MASK (0x1 << 13)
1458#define RT5670_JD_STKY_SFT 13
1459#define RT5670_JD_STKY_DIS (0x0 << 13)
1460#define RT5670_JD_STKY_EN (0x1 << 13)
1461#define RT5670_OT_STKY_MASK (0x1 << 12)
1462#define RT5670_OT_STKY_SFT 12
1463#define RT5670_OT_STKY_DIS (0x0 << 12)
1464#define RT5670_OT_STKY_EN (0x1 << 12)
1465#define RT5670_JD_P_MASK (0x1 << 11)
1466#define RT5670_JD_P_SFT 11
1467#define RT5670_JD_P_NOR (0x0 << 11)
1468#define RT5670_JD_P_INV (0x1 << 11)
1469#define RT5670_OT_P_MASK (0x1 << 10)
1470#define RT5670_OT_P_SFT 10
1471#define RT5670_OT_P_NOR (0x0 << 10)
1472#define RT5670_OT_P_INV (0x1 << 10)
1473#define RT5670_JD1_1_EN_MASK (0x1 << 9)
1474#define RT5670_JD1_1_EN_SFT 9
1475#define RT5670_JD1_1_DIS (0x0 << 9)
1476#define RT5670_JD1_1_EN (0x1 << 9)
1477
1478/* IRQ Control 2 (0xbe) */
1479#define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1480#define RT5670_IRQ_MB1_OC_SFT 15
1481#define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
1482#define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1483#define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1484#define RT5670_IRQ_MB2_OC_SFT 14
1485#define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
1486#define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1487#define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1488#define RT5670_MB1_OC_STKY_SFT 11
1489#define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
1490#define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1491#define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1492#define RT5670_MB2_OC_STKY_SFT 10
1493#define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
1494#define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1495#define RT5670_MB1_OC_P_MASK (0x1 << 7)
1496#define RT5670_MB1_OC_P_SFT 7
1497#define RT5670_MB1_OC_P_NOR (0x0 << 7)
1498#define RT5670_MB1_OC_P_INV (0x1 << 7)
1499#define RT5670_MB2_OC_P_MASK (0x1 << 6)
1500#define RT5670_MB2_OC_P_SFT 6
1501#define RT5670_MB2_OC_P_NOR (0x0 << 6)
1502#define RT5670_MB2_OC_P_INV (0x1 << 6)
1503#define RT5670_MB1_OC_CLR (0x1 << 3)
1504#define RT5670_MB1_OC_CLR_SFT 3
1505#define RT5670_MB2_OC_CLR (0x1 << 2)
1506#define RT5670_MB2_OC_CLR_SFT 2
1507
1508/* GPIO Control 1 (0xc0) */
1509#define RT5670_GP1_PIN_MASK (0x1 << 15)
1510#define RT5670_GP1_PIN_SFT 15
1511#define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
1512#define RT5670_GP1_PIN_IRQ (0x1 << 15)
1513#define RT5670_GP2_PIN_MASK (0x1 << 14)
1514#define RT5670_GP2_PIN_SFT 14
1515#define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
1516#define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1517#define RT5670_GP3_PIN_MASK (0x3 << 12)
1518#define RT5670_GP3_PIN_SFT 12
1519#define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
1520#define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1521#define RT5670_GP3_PIN_IRQ (0x2 << 12)
1522#define RT5670_GP4_PIN_MASK (0x1 << 11)
1523#define RT5670_GP4_PIN_SFT 11
1524#define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
1525#define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1526#define RT5670_DP_SIG_MASK (0x1 << 10)
1527#define RT5670_DP_SIG_SFT 10
1528#define RT5670_DP_SIG_TEST (0x0 << 10)
1529#define RT5670_DP_SIG_AP (0x1 << 10)
1530#define RT5670_GPIO_M_MASK (0x1 << 9)
1531#define RT5670_GPIO_M_SFT 9
1532#define RT5670_GPIO_M_FLT (0x0 << 9)
1533#define RT5670_GPIO_M_PH (0x1 << 9)
1534#define RT5670_I2S2_PIN_MASK (0x1 << 8)
1535#define RT5670_I2S2_PIN_SFT 8
1536#define RT5670_I2S2_PIN_I2S (0x0 << 8)
1537#define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1538#define RT5670_GP5_PIN_MASK (0x1 << 7)
1539#define RT5670_GP5_PIN_SFT 7
1540#define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
1541#define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1542#define RT5670_GP6_PIN_MASK (0x1 << 6)
1543#define RT5670_GP6_PIN_SFT 6
1544#define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
1545#define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1546#define RT5670_GP7_PIN_MASK (0x3 << 4)
1547#define RT5670_GP7_PIN_SFT 4
1548#define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
1549#define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1550#define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
1551#define RT5670_GP8_PIN_MASK (0x1 << 3)
1552#define RT5670_GP8_PIN_SFT 3
1553#define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
1554#define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1555#define RT5670_GP9_PIN_MASK (0x1 << 2)
1556#define RT5670_GP9_PIN_SFT 2
1557#define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
1558#define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1559#define RT5670_GP10_PIN_MASK (0x3)
1560#define RT5670_GP10_PIN_SFT 0
1561#define RT5670_GP10_PIN_GPIO9 (0x0)
1562#define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1563#define RT5670_GP10_PIN_PDM_ADT2 (0x2)
1564
1565/* GPIO Control 2 (0xc1) */
1566#define RT5670_GP4_PF_MASK (0x1 << 11)
1567#define RT5670_GP4_PF_SFT 11
1568#define RT5670_GP4_PF_IN (0x0 << 11)
1569#define RT5670_GP4_PF_OUT (0x1 << 11)
1570#define RT5670_GP4_OUT_MASK (0x1 << 10)
1571#define RT5670_GP4_OUT_SFT 10
1572#define RT5670_GP4_OUT_LO (0x0 << 10)
1573#define RT5670_GP4_OUT_HI (0x1 << 10)
1574#define RT5670_GP4_P_MASK (0x1 << 9)
1575#define RT5670_GP4_P_SFT 9
1576#define RT5670_GP4_P_NOR (0x0 << 9)
1577#define RT5670_GP4_P_INV (0x1 << 9)
1578#define RT5670_GP3_PF_MASK (0x1 << 8)
1579#define RT5670_GP3_PF_SFT 8
1580#define RT5670_GP3_PF_IN (0x0 << 8)
1581#define RT5670_GP3_PF_OUT (0x1 << 8)
1582#define RT5670_GP3_OUT_MASK (0x1 << 7)
1583#define RT5670_GP3_OUT_SFT 7
1584#define RT5670_GP3_OUT_LO (0x0 << 7)
1585#define RT5670_GP3_OUT_HI (0x1 << 7)
1586#define RT5670_GP3_P_MASK (0x1 << 6)
1587#define RT5670_GP3_P_SFT 6
1588#define RT5670_GP3_P_NOR (0x0 << 6)
1589#define RT5670_GP3_P_INV (0x1 << 6)
1590#define RT5670_GP2_PF_MASK (0x1 << 5)
1591#define RT5670_GP2_PF_SFT 5
1592#define RT5670_GP2_PF_IN (0x0 << 5)
1593#define RT5670_GP2_PF_OUT (0x1 << 5)
1594#define RT5670_GP2_OUT_MASK (0x1 << 4)
1595#define RT5670_GP2_OUT_SFT 4
1596#define RT5670_GP2_OUT_LO (0x0 << 4)
1597#define RT5670_GP2_OUT_HI (0x1 << 4)
1598#define RT5670_GP2_P_MASK (0x1 << 3)
1599#define RT5670_GP2_P_SFT 3
1600#define RT5670_GP2_P_NOR (0x0 << 3)
1601#define RT5670_GP2_P_INV (0x1 << 3)
1602#define RT5670_GP1_PF_MASK (0x1 << 2)
1603#define RT5670_GP1_PF_SFT 2
1604#define RT5670_GP1_PF_IN (0x0 << 2)
1605#define RT5670_GP1_PF_OUT (0x1 << 2)
1606#define RT5670_GP1_OUT_MASK (0x1 << 1)
1607#define RT5670_GP1_OUT_SFT 1
1608#define RT5670_GP1_OUT_LO (0x0 << 1)
1609#define RT5670_GP1_OUT_HI (0x1 << 1)
1610#define RT5670_GP1_P_MASK (0x1)
1611#define RT5670_GP1_P_SFT 0
1612#define RT5670_GP1_P_NOR (0x0)
1613#define RT5670_GP1_P_INV (0x1)
1614
1615/* Scramble Function (0xcd) */
1616#define RT5670_SCB_KEY_MASK (0xff)
1617#define RT5670_SCB_KEY_SFT 0
1618
1619/* Scramble Control (0xce) */
1620#define RT5670_SCB_SWAP_MASK (0x1 << 15)
1621#define RT5670_SCB_SWAP_SFT 15
1622#define RT5670_SCB_SWAP_DIS (0x0 << 15)
1623#define RT5670_SCB_SWAP_EN (0x1 << 15)
1624#define RT5670_SCB_MASK (0x1 << 14)
1625#define RT5670_SCB_SFT 14
1626#define RT5670_SCB_DIS (0x0 << 14)
1627#define RT5670_SCB_EN (0x1 << 14)
1628
1629/* Baseback Control (0xcf) */
1630#define RT5670_BB_MASK (0x1 << 15)
1631#define RT5670_BB_SFT 15
1632#define RT5670_BB_DIS (0x0 << 15)
1633#define RT5670_BB_EN (0x1 << 15)
1634#define RT5670_BB_CT_MASK (0x7 << 12)
1635#define RT5670_BB_CT_SFT 12
1636#define RT5670_BB_CT_A (0x0 << 12)
1637#define RT5670_BB_CT_B (0x1 << 12)
1638#define RT5670_BB_CT_C (0x2 << 12)
1639#define RT5670_BB_CT_D (0x3 << 12)
1640#define RT5670_M_BB_L_MASK (0x1 << 9)
1641#define RT5670_M_BB_L_SFT 9
1642#define RT5670_M_BB_R_MASK (0x1 << 8)
1643#define RT5670_M_BB_R_SFT 8
1644#define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1645#define RT5670_M_BB_HPF_L_SFT 7
1646#define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1647#define RT5670_M_BB_HPF_R_SFT 6
1648#define RT5670_G_BB_BST_MASK (0x3f)
1649#define RT5670_G_BB_BST_SFT 0
1650
1651/* MP3 Plus Control 1 (0xd0) */
1652#define RT5670_M_MP3_L_MASK (0x1 << 15)
1653#define RT5670_M_MP3_L_SFT 15
1654#define RT5670_M_MP3_R_MASK (0x1 << 14)
1655#define RT5670_M_MP3_R_SFT 14
1656#define RT5670_M_MP3_MASK (0x1 << 13)
1657#define RT5670_M_MP3_SFT 13
1658#define RT5670_M_MP3_DIS (0x0 << 13)
1659#define RT5670_M_MP3_EN (0x1 << 13)
1660#define RT5670_EG_MP3_MASK (0x1f << 8)
1661#define RT5670_EG_MP3_SFT 8
1662#define RT5670_MP3_HLP_MASK (0x1 << 7)
1663#define RT5670_MP3_HLP_SFT 7
1664#define RT5670_MP3_HLP_DIS (0x0 << 7)
1665#define RT5670_MP3_HLP_EN (0x1 << 7)
1666#define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1667#define RT5670_M_MP3_ORG_L_SFT 6
1668#define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1669#define RT5670_M_MP3_ORG_R_SFT 5
1670
1671/* MP3 Plus Control 2 (0xd1) */
1672#define RT5670_MP3_WT_MASK (0x1 << 13)
1673#define RT5670_MP3_WT_SFT 13
1674#define RT5670_MP3_WT_1_4 (0x0 << 13)
1675#define RT5670_MP3_WT_1_2 (0x1 << 13)
1676#define RT5670_OG_MP3_MASK (0x1f << 8)
1677#define RT5670_OG_MP3_SFT 8
1678#define RT5670_HG_MP3_MASK (0x3f)
1679#define RT5670_HG_MP3_SFT 0
1680
1681/* 3D HP Control 1 (0xd2) */
1682#define RT5670_3D_CF_MASK (0x1 << 15)
1683#define RT5670_3D_CF_SFT 15
1684#define RT5670_3D_CF_DIS (0x0 << 15)
1685#define RT5670_3D_CF_EN (0x1 << 15)
1686#define RT5670_3D_HP_MASK (0x1 << 14)
1687#define RT5670_3D_HP_SFT 14
1688#define RT5670_3D_HP_DIS (0x0 << 14)
1689#define RT5670_3D_HP_EN (0x1 << 14)
1690#define RT5670_3D_BT_MASK (0x1 << 13)
1691#define RT5670_3D_BT_SFT 13
1692#define RT5670_3D_BT_DIS (0x0 << 13)
1693#define RT5670_3D_BT_EN (0x1 << 13)
1694#define RT5670_3D_1F_MIX_MASK (0x3 << 11)
1695#define RT5670_3D_1F_MIX_SFT 11
1696#define RT5670_3D_HP_M_MASK (0x1 << 10)
1697#define RT5670_3D_HP_M_SFT 10
1698#define RT5670_3D_HP_M_SUR (0x0 << 10)
1699#define RT5670_3D_HP_M_FRO (0x1 << 10)
1700#define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1701#define RT5670_M_3D_HRTF_SFT 9
1702#define RT5670_M_3D_D2H_MASK (0x1 << 8)
1703#define RT5670_M_3D_D2H_SFT 8
1704#define RT5670_M_3D_D2R_MASK (0x1 << 7)
1705#define RT5670_M_3D_D2R_SFT 7
1706#define RT5670_M_3D_REVB_MASK (0x1 << 6)
1707#define RT5670_M_3D_REVB_SFT 6
1708
1709/* Adjustable high pass filter control 1 (0xd3) */
1710#define RT5670_2ND_HPF_MASK (0x1 << 15)
1711#define RT5670_2ND_HPF_SFT 15
1712#define RT5670_2ND_HPF_DIS (0x0 << 15)
1713#define RT5670_2ND_HPF_EN (0x1 << 15)
1714#define RT5670_HPF_CF_L_MASK (0x7 << 12)
1715#define RT5670_HPF_CF_L_SFT 12
1716#define RT5670_1ST_HPF_MASK (0x1 << 11)
1717#define RT5670_1ST_HPF_SFT 11
1718#define RT5670_1ST_HPF_DIS (0x0 << 11)
1719#define RT5670_1ST_HPF_EN (0x1 << 11)
1720#define RT5670_HPF_CF_R_MASK (0x7 << 8)
1721#define RT5670_HPF_CF_R_SFT 8
1722#define RT5670_ZD_T_MASK (0x3 << 6)
1723#define RT5670_ZD_T_SFT 6
1724#define RT5670_ZD_F_MASK (0x3 << 4)
1725#define RT5670_ZD_F_SFT 4
1726#define RT5670_ZD_F_IM (0x0 << 4)
1727#define RT5670_ZD_F_ZC_IM (0x1 << 4)
1728#define RT5670_ZD_F_ZC_IOD (0x2 << 4)
1729#define RT5670_ZD_F_UN (0x3 << 4)
1730
1731/* HP calibration control and Amp detection (0xd6) */
1732#define RT5670_SI_DAC_MASK (0x1 << 11)
1733#define RT5670_SI_DAC_SFT 11
1734#define RT5670_SI_DAC_AUTO (0x0 << 11)
1735#define RT5670_SI_DAC_TEST (0x1 << 11)
1736#define RT5670_DC_CAL_M_MASK (0x1 << 10)
1737#define RT5670_DC_CAL_M_SFT 10
1738#define RT5670_DC_CAL_M_CAL (0x0 << 10)
1739#define RT5670_DC_CAL_M_NOR (0x1 << 10)
1740#define RT5670_DC_CAL_MASK (0x1 << 9)
1741#define RT5670_DC_CAL_SFT 9
1742#define RT5670_DC_CAL_DIS (0x0 << 9)
1743#define RT5670_DC_CAL_EN (0x1 << 9)
1744#define RT5670_HPD_RCV_MASK (0x7 << 6)
1745#define RT5670_HPD_RCV_SFT 6
1746#define RT5670_HPD_PS_MASK (0x1 << 5)
1747#define RT5670_HPD_PS_SFT 5
1748#define RT5670_HPD_PS_DIS (0x0 << 5)
1749#define RT5670_HPD_PS_EN (0x1 << 5)
1750#define RT5670_CAL_M_MASK (0x1 << 4)
1751#define RT5670_CAL_M_SFT 4
1752#define RT5670_CAL_M_DEP (0x0 << 4)
1753#define RT5670_CAL_M_CAL (0x1 << 4)
1754#define RT5670_CAL_MASK (0x1 << 3)
1755#define RT5670_CAL_SFT 3
1756#define RT5670_CAL_DIS (0x0 << 3)
1757#define RT5670_CAL_EN (0x1 << 3)
1758#define RT5670_CAL_TEST_MASK (0x1 << 2)
1759#define RT5670_CAL_TEST_SFT 2
1760#define RT5670_CAL_TEST_DIS (0x0 << 2)
1761#define RT5670_CAL_TEST_EN (0x1 << 2)
1762#define RT5670_CAL_P_MASK (0x3)
1763#define RT5670_CAL_P_SFT 0
1764#define RT5670_CAL_P_NONE (0x0)
1765#define RT5670_CAL_P_CAL (0x1)
1766#define RT5670_CAL_P_DAC_CAL (0x2)
1767
1768/* Soft volume and zero cross control 1 (0xd9) */
1769#define RT5670_SV_MASK (0x1 << 15)
1770#define RT5670_SV_SFT 15
1771#define RT5670_SV_DIS (0x0 << 15)
1772#define RT5670_SV_EN (0x1 << 15)
1773#define RT5670_SPO_SV_MASK (0x1 << 14)
1774#define RT5670_SPO_SV_SFT 14
1775#define RT5670_SPO_SV_DIS (0x0 << 14)
1776#define RT5670_SPO_SV_EN (0x1 << 14)
1777#define RT5670_OUT_SV_MASK (0x1 << 13)
1778#define RT5670_OUT_SV_SFT 13
1779#define RT5670_OUT_SV_DIS (0x0 << 13)
1780#define RT5670_OUT_SV_EN (0x1 << 13)
1781#define RT5670_HP_SV_MASK (0x1 << 12)
1782#define RT5670_HP_SV_SFT 12
1783#define RT5670_HP_SV_DIS (0x0 << 12)
1784#define RT5670_HP_SV_EN (0x1 << 12)
1785#define RT5670_ZCD_DIG_MASK (0x1 << 11)
1786#define RT5670_ZCD_DIG_SFT 11
1787#define RT5670_ZCD_DIG_DIS (0x0 << 11)
1788#define RT5670_ZCD_DIG_EN (0x1 << 11)
1789#define RT5670_ZCD_MASK (0x1 << 10)
1790#define RT5670_ZCD_SFT 10
1791#define RT5670_ZCD_PD (0x0 << 10)
1792#define RT5670_ZCD_PU (0x1 << 10)
1793#define RT5670_M_ZCD_MASK (0x3f << 4)
1794#define RT5670_M_ZCD_SFT 4
1795#define RT5670_M_ZCD_RM_L (0x1 << 9)
1796#define RT5670_M_ZCD_RM_R (0x1 << 8)
1797#define RT5670_M_ZCD_SM_L (0x1 << 7)
1798#define RT5670_M_ZCD_SM_R (0x1 << 6)
1799#define RT5670_M_ZCD_OM_L (0x1 << 5)
1800#define RT5670_M_ZCD_OM_R (0x1 << 4)
1801#define RT5670_SV_DLY_MASK (0xf)
1802#define RT5670_SV_DLY_SFT 0
1803
1804/* Soft volume and zero cross control 2 (0xda) */
1805#define RT5670_ZCD_HP_MASK (0x1 << 15)
1806#define RT5670_ZCD_HP_SFT 15
1807#define RT5670_ZCD_HP_DIS (0x0 << 15)
1808#define RT5670_ZCD_HP_EN (0x1 << 15)
1809
1810/* General Control 3 (0xfc) */
1811#define RT5670_TDM_DATA_MODE_SEL (0x1 << 11)
1812#define RT5670_TDM_DATA_MODE_NOR (0x0 << 11)
1813#define RT5670_TDM_DATA_MODE_50FS (0x1 << 11)
1814
1815/* Codec Private Register definition */
1816/* 3D Speaker Control (0x63) */
1817#define RT5670_3D_SPK_MASK (0x1 << 15)
1818#define RT5670_3D_SPK_SFT 15
1819#define RT5670_3D_SPK_DIS (0x0 << 15)
1820#define RT5670_3D_SPK_EN (0x1 << 15)
1821#define RT5670_3D_SPK_M_MASK (0x3 << 13)
1822#define RT5670_3D_SPK_M_SFT 13
1823#define RT5670_3D_SPK_CG_MASK (0x1f << 8)
1824#define RT5670_3D_SPK_CG_SFT 8
1825#define RT5670_3D_SPK_SG_MASK (0x1f)
1826#define RT5670_3D_SPK_SG_SFT 0
1827
1828/* Wind Noise Detection Control 1 (0x6c) */
1829#define RT5670_WND_MASK (0x1 << 15)
1830#define RT5670_WND_SFT 15
1831#define RT5670_WND_DIS (0x0 << 15)
1832#define RT5670_WND_EN (0x1 << 15)
1833
1834/* Wind Noise Detection Control 2 (0x6d) */
1835#define RT5670_WND_FC_NW_MASK (0x3f << 10)
1836#define RT5670_WND_FC_NW_SFT 10
1837#define RT5670_WND_FC_WK_MASK (0x3f << 4)
1838#define RT5670_WND_FC_WK_SFT 4
1839
1840/* Wind Noise Detection Control 3 (0x6e) */
1841#define RT5670_HPF_FC_MASK (0x3f << 6)
1842#define RT5670_HPF_FC_SFT 6
1843#define RT5670_WND_FC_ST_MASK (0x3f)
1844#define RT5670_WND_FC_ST_SFT 0
1845
1846/* Wind Noise Detection Control 4 (0x6f) */
1847#define RT5670_WND_TH_LO_MASK (0x3ff)
1848#define RT5670_WND_TH_LO_SFT 0
1849
1850/* Wind Noise Detection Control 5 (0x70) */
1851#define RT5670_WND_TH_HI_MASK (0x3ff)
1852#define RT5670_WND_TH_HI_SFT 0
1853
1854/* Wind Noise Detection Control 8 (0x73) */
1855#define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1856#define RT5670_WND_WIND_SFT 13
1857#define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1858#define RT5670_WND_STRONG_SFT 12
1859enum {
1860 RT5670_NO_WIND,
1861 RT5670_BREEZE,
1862 RT5670_STORM,
1863};
1864
1865/* Dipole Speaker Interface (0x75) */
1866#define RT5670_DP_ATT_MASK (0x3 << 14)
1867#define RT5670_DP_ATT_SFT 14
1868#define RT5670_DP_SPK_MASK (0x1 << 10)
1869#define RT5670_DP_SPK_SFT 10
1870#define RT5670_DP_SPK_DIS (0x0 << 10)
1871#define RT5670_DP_SPK_EN (0x1 << 10)
1872
1873/* EQ Pre Volume Control (0xb3) */
1874#define RT5670_EQ_PRE_VOL_MASK (0xffff)
1875#define RT5670_EQ_PRE_VOL_SFT 0
1876
1877/* EQ Post Volume Control (0xb4) */
1878#define RT5670_EQ_PST_VOL_MASK (0xffff)
1879#define RT5670_EQ_PST_VOL_SFT 0
1880
1881/* Jack Detect Control 3 (0xf8) */
1882#define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
1883#define RT5670_JD_CBJ_EN (0x1 << 7)
1884#define RT5670_JD_CBJ_POL (0x1 << 6)
1885#define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
1886#define RT5670_JD_TRI_CBJ_SEL_SFT (3)
1887#define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
1888#define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1889#define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
1890#define RT5670_JD_CBJ_JD2 (0x3 << 3)
1891#define RT5670_JD_CBJ_JD3 (0x4 << 3)
1892#define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
1893#define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
1894#define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
1895#define RT5670_JD_TRI_HPO_SEL_SFT (0)
1896#define RT5670_JD_HPO_GPIO_JD1 (0x0)
1897#define RT5670_JD_HPO_JD1_1 (0x1)
1898#define RT5670_JD_HPO_JD1_2 (0x2)
1899#define RT5670_JD_HPO_JD2 (0x3)
1900#define RT5670_JD_HPO_JD3 (0x4)
1901#define RT5670_JD_HPO_GPIO_JD2 (0x5)
1902#define RT5670_JD_HPO_MX0B_12 (0x6)
1903
1904/* Digital Misc Control (0xfa) */
1905#define RT5670_RST_DSP (0x1 << 13)
1906#define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1907#define RT5670_IF1_ADC1_IN1_SFT 12
1908#define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1909#define RT5670_IF1_ADC1_IN2_SFT 11
1910#define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1911#define RT5670_IF1_ADC2_IN1_SFT 10
1912#define RT5670_MCLK_DET (0x1 << 3)
1913
1914/* General Control2 (0xfb) */
1915#define RT5670_RXDC_SRC_MASK (0x1 << 7)
1916#define RT5670_RXDC_SRC_STO (0x0 << 7)
1917#define RT5670_RXDC_SRC_MONO (0x1 << 7)
1918#define RT5670_RXDC_SRC_SFT (7)
1919#define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1920#define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
1921#define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1922#define RT5670_RXDP2_SEL_SFT (3)
1923
1924/* System Clock Source */
1925enum {
1926 RT5670_SCLK_S_MCLK,
1927 RT5670_SCLK_S_PLL1,
1928 RT5670_SCLK_S_RCCLK,
1929};
1930
1931/* PLL1 Source */
1932enum {
1933 RT5670_PLL1_S_MCLK,
1934 RT5670_PLL1_S_BCLK1,
1935 RT5670_PLL1_S_BCLK2,
1936 RT5670_PLL1_S_BCLK3,
1937 RT5670_PLL1_S_BCLK4,
1938};
1939
1940enum {
1941 RT5670_AIF1,
1942 RT5670_AIF2,
1943 RT5670_AIF3,
1944 RT5670_AIF4,
1945 RT5670_AIFS,
1946};
1947
1948enum {
1949 RT5670_DMIC1_DISABLED,
1950 RT5670_DMIC_DATA_GPIO6,
1951 RT5670_DMIC_DATA_IN2P,
1952 RT5670_DMIC_DATA_GPIO7,
1953};
1954
1955enum {
1956 RT5670_DMIC2_DISABLED,
1957 RT5670_DMIC_DATA_GPIO8,
1958 RT5670_DMIC_DATA_IN3N,
1959};
1960
1961enum {
1962 RT5670_DMIC3_DISABLED,
1963 RT5670_DMIC_DATA_GPIO9,
1964 RT5670_DMIC_DATA_GPIO10,
1965 RT5670_DMIC_DATA_GPIO5,
1966};
1967
1968/* filter mask */
1969enum {
1970 RT5670_DA_STEREO_FILTER = 0x1,
1971 RT5670_DA_MONO_L_FILTER = (0x1 << 1),
1972 RT5670_DA_MONO_R_FILTER = (0x1 << 2),
1973 RT5670_AD_STEREO_FILTER = (0x1 << 3),
1974 RT5670_AD_MONO_L_FILTER = (0x1 << 4),
1975 RT5670_AD_MONO_R_FILTER = (0x1 << 5),
1976 RT5670_UP_RATE_FILTER = (0x1 << 6),
1977 RT5670_DOWN_RATE_FILTER = (0x1 << 7),
1978};
1979
1980int rt5670_sel_asrc_clk_src(struct snd_soc_component *component,
1981 unsigned int filter_mask, unsigned int clk_src);
1982
1983struct rt5670_priv {
1984 struct snd_soc_component *component;
1985 struct regmap *regmap;
1986 struct snd_soc_jack *jack;
1987 struct snd_soc_jack_gpio hp_gpio;
1988
1989 int jd_mode;
1990 bool in2_diff;
1991 bool gpio1_is_irq;
1992 bool gpio1_is_ext_spk_en;
1993
1994 bool dmic_en;
1995 unsigned int dmic1_data_pin;
1996 /* 0 = GPIO6; 1 = IN2P; 3 = GPIO7*/
1997 unsigned int dmic2_data_pin;
1998 /* 0 = GPIO8; 1 = IN3N; */
1999 unsigned int dmic3_data_pin;
2000 /* 0 = GPIO9; 1 = GPIO10; 2 = GPIO5*/
2001
2002 int sysclk;
2003 int sysclk_src;
2004 int lrck[RT5670_AIFS];
2005 int bclk[RT5670_AIFS];
2006 int master[RT5670_AIFS];
2007
2008 int pll_src;
2009 int pll_in;
2010 int pll_out;
2011
2012 int dsp_sw; /* expected parameter setting */
2013 int dsp_rate;
2014 int jack_type;
2015 int jack_type_saved;
2016
2017 bool dac1_mixl_dac1_switch;
2018 bool dac1_mixr_dac1_switch;
2019 bool dac1_playback_switch_l;
2020 bool dac1_playback_switch_r;
2021};
2022
2023void rt5670_jack_suspend(struct snd_soc_component *component);
2024void rt5670_jack_resume(struct snd_soc_component *component);
2025int rt5670_set_jack_detect(struct snd_soc_component *component,
2026 struct snd_soc_jack *jack);
2027const char *rt5670_components(void);
2028
2029#endif /* __RT5670_H__ */
2030

source code of linux/sound/soc/codecs/rt5670.h