1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * sma1303.h -- sma1303 ALSA SoC Audio driver |
4 | * |
5 | * Copyright 2023 Iron Device Corporation |
6 | * |
7 | * Author: Kiseok Jo <kiseok.jo@irondevice.com> |
8 | * |
9 | */ |
10 | |
11 | #ifndef _SMA1303_H |
12 | #define _SMA1303_H |
13 | |
14 | #define SMA1303_I2C_ADDR_00 0x1e |
15 | #define SMA1303_I2C_ADDR_01 0x3e |
16 | #define SMA1303_I2C_ADDR_10 0x5e |
17 | #define SMA1303_I2C_ADDR_11 0x7e |
18 | |
19 | #define SMA1303_EXTERNAL_CLOCK_19_2 0x00 |
20 | #define SMA1303_EXTERNAL_CLOCK_24_576 0x01 |
21 | #define SMA1303_PLL_CLKIN_MCLK 0x02 |
22 | #define SMA1303_PLL_CLKIN_BCLK 0x03 |
23 | |
24 | #define SMA1303_MONO 0x00 |
25 | #define SMA1303_STEREO 0x01 |
26 | |
27 | #define SMA1303_I2C_RETRY_COUNT 3 |
28 | |
29 | /* |
30 | * SMA1303 Register Definition |
31 | */ |
32 | |
33 | /* SMA1303 Register Addresses */ |
34 | #define SMA1303_00_SYSTEM_CTRL 0x00 |
35 | #define SMA1303_01_INPUT1_CTRL1 0x01 |
36 | #define SMA1303_02_INPUT1_CTRL2 0x02 |
37 | #define SMA1303_03_INPUT1_CTRL3 0x03 |
38 | #define SMA1303_04_INPUT1_CTRL4 0x04 |
39 | /* 0x05 ~ 0x08 : Reserved */ |
40 | #define SMA1303_09_OUTPUT_CTRL 0x09 |
41 | #define SMA1303_0A_SPK_VOL 0x0a |
42 | #define SMA1303_0B_BST_TEST 0x0b |
43 | #define SMA1303_0C_BST_TEST1 0x0c |
44 | #define SMA1303_0D_SPK_TEST 0x0d |
45 | #define SMA1303_0E_MUTE_VOL_CTRL 0x0e |
46 | /* 0x0F : Reserved */ |
47 | #define SMA1303_10_SYSTEM_CTRL1 0x10 |
48 | #define SMA1303_11_SYSTEM_CTRL2 0x11 |
49 | #define SMA1303_12_SYSTEM_CTRL3 0x12 |
50 | /* 0x13 : Reserved */ |
51 | #define SMA1303_14_MODULATOR 0x14 |
52 | #define SMA1303_15_BASS_SPK1 0x15 |
53 | #define SMA1303_16_BASS_SPK2 0x16 |
54 | #define SMA1303_17_BASS_SPK3 0x17 |
55 | #define SMA1303_18_BASS_SPK4 0x18 |
56 | #define SMA1303_19_BASS_SPK5 0x19 |
57 | #define SMA1303_1A_BASS_SPK6 0x1a |
58 | #define SMA1303_1B_BASS_SPK7 0x1b |
59 | /* 0x1C ~ 0x22 : Reserved */ |
60 | #define SMA1303_23_COMP_LIM1 0x23 |
61 | #define SMA1303_24_COMP_LIM2 0x24 |
62 | #define SMA1303_25_COMP_LIM3 0x25 |
63 | #define SMA1303_26_COMP_LIM4 0x26 |
64 | /* 0x27 ~ 0x32 : Reserved */ |
65 | #define SMA1303_33_SDM_CTRL 0x33 |
66 | #define SMA1303_34_OTP_DATA1 0x34 |
67 | /* 0x35 : Reserved */ |
68 | #define SMA1303_36_PROTECTION 0x36 |
69 | #define SMA1303_37_SLOPE_CTRL 0x37 |
70 | #define SMA1303_38_OTP_TRM0 0x38 |
71 | /* 0x39 ~ 0x3A : Reserved */ |
72 | #define SMA1303_3B_TEST1 0x3b |
73 | #define SMA1303_3C_TEST2 0x3c |
74 | #define SMA1303_3D_TEST3 0x3d |
75 | #define SMA1303_3E_ATEST1 0x3e |
76 | #define SMA1303_3F_ATEST2 0x3f |
77 | /* 0x40 ~ 0x8A : Reserved */ |
78 | #define SMA1303_8B_PLL_POST_N 0x8b |
79 | #define SMA1303_8C_PLL_N 0x8c |
80 | #define SMA1303_8D_PLL_A_SETTING 0x8d |
81 | #define SMA1303_8E_PLL_CTRL 0x8e |
82 | #define SMA1303_8F_PLL_P_CP 0x8f |
83 | #define SMA1303_90_POSTSCALER 0x90 |
84 | #define SMA1303_91_CLASS_G_CTRL 0x91 |
85 | #define SMA1303_92_FDPEC_CTRL 0x92 |
86 | /* 0x93 : Reserved */ |
87 | #define SMA1303_94_BOOST_CTRL1 0x94 |
88 | #define SMA1303_95_BOOST_CTRL2 0x95 |
89 | #define SMA1303_96_BOOST_CTRL3 0x96 |
90 | #define SMA1303_97_BOOST_CTRL4 0x97 |
91 | /* 0x98 ~ 0x9F : Reserved */ |
92 | #define SMA1303_A0_PAD_CTRL0 0xa0 |
93 | #define SMA1303_A1_PAD_CTRL1 0xa1 |
94 | #define SMA1303_A2_TOP_MAN1 0xa2 |
95 | #define SMA1303_A3_TOP_MAN2 0xa3 |
96 | #define SMA1303_A4_TOP_MAN3 0xa4 |
97 | #define SMA1303_A5_TDM1 0xa5 |
98 | #define SMA1303_A6_TDM2 0xa6 |
99 | #define SMA1303_A7_CLK_MON 0xa7 |
100 | /* 0xA8 ~ 0xF9 : Reserved */ |
101 | #define SMA1303_FA_STATUS1 0xfa |
102 | #define SMA1303_FB_STATUS2 0xfb |
103 | /* 0xFC ~ 0xFE : Reserved */ |
104 | #define SMA1303_FF_DEVICE_INDEX 0xff |
105 | |
106 | /* SMA1303 Registers Bit Fields */ |
107 | |
108 | /* SYSTEM_CTRL : 0x00 */ |
109 | #define SMA1303_RESETBYI2C_MASK (1<<1) |
110 | #define SMA1303_RESETBYI2C_NORMAL (0<<1) |
111 | #define SMA1303_RESETBYI2C_RESET (1<<1) |
112 | |
113 | #define SMA1303_POWER_MASK (1<<0) |
114 | #define SMA1303_POWER_OFF (0<<0) |
115 | #define SMA1303_POWER_ON (1<<0) |
116 | |
117 | /* INTPUT CTRL1 : 0x01 */ |
118 | #define SMA1303_CONTROLLER_DEVICE_MASK (1<<7) |
119 | #define SMA1303_DEVICE_MODE (0<<7) |
120 | #define SMA1303_CONTROLLER_MODE (1<<7) |
121 | |
122 | #define SMA1303_I2S_MODE_MASK (7<<4) |
123 | #define SMA1303_STANDARD_I2S (0<<4) |
124 | #define SMA1303_LJ (1<<4) |
125 | #define SMA1303_RJ_16BIT (4<<4) |
126 | #define SMA1303_RJ_18BIT (5<<4) |
127 | #define SMA1303_RJ_20BIT (6<<4) |
128 | #define SMA1303_RJ_24BIT (7<<4) |
129 | |
130 | #define SMA1303_LEFTPOL_MASK (1<<3) |
131 | #define SMA1303_LOW_FIRST_CH (0<<3) |
132 | #define SMA1303_HIGH_FIRST_CH (1<<3) |
133 | |
134 | #define SMA1303_SCK_RISING_MASK (1<<2) |
135 | #define SMA1303_SCK_FALLING_EDGE (0<<2) |
136 | #define SMA1303_SCK_RISING_EDGE (1<<2) |
137 | |
138 | /* INTPUT CTRL2 : 0x02 */ |
139 | #define SMA1303_IMODE_MASK (3<<6) |
140 | #define SMA1303_I2S (0<<6) |
141 | #define SMA1303_PCM_SHORT (1<<6) |
142 | #define SMA1303_PCM_LONG (2<<6) |
143 | |
144 | #define RSMA1303_IGHT_FIRST_MASK (1<<5) |
145 | #define SMA1303_LEFT_NORMAL (0<<5) |
146 | #define SMA1303_RIGHT_INVERTED (1<<5) |
147 | |
148 | #define SMA1303_PCM_ALAW_MASK (1<<4) |
149 | #define SMA1303_PCM_U_DECODING (0<<4) |
150 | #define SMA1303_PCM_A_DECODING (1<<4) |
151 | |
152 | #define SMA1303_PCM_COMP_MASK (1<<3) |
153 | #define SMA1303_PCM_LINEAR (0<<3) |
154 | #define SMA1303_PCM_COMPANDING (1<<3) |
155 | |
156 | #define SMA1303_INPUTSEL_MASK (1<<2) |
157 | #define SMA1303_PCM_8KHZ (0<<2) |
158 | #define SMA1303_PCM_16KHZ (1<<2) |
159 | |
160 | #define SMA1303_PCM_STEREO_MASK (1<<1) |
161 | #define SMA1303_PCM_MONO (0<<1) |
162 | #define SMA1303_PCM_STEREO (1<<1) |
163 | |
164 | #define SMA1303_PCM_DL_MASK (1<<0) |
165 | #define SMA1303_PCM_8BIT (0<<0) |
166 | #define SMA1303_PCM_16BIT (1<<0) |
167 | |
168 | /* INTPUT CTRL3 : 0x03 */ |
169 | #define SMA1303_PCM_N_SLOT_MASK (15<<0) |
170 | #define SMA1303_PCM_N_SLOT1 (0<<0) |
171 | #define SMA1303_PCM_N_SLOT2 (1<<0) |
172 | #define SMA1303_PCM_N_SLOT3 (2<<0) |
173 | #define SMA1303_PCM_N_SLOT4 (3<<0) |
174 | #define SMA1303_PCM_N_SLOT5 (4<<0) |
175 | #define SMA1303_PCM_N_SLOT6 (5<<0) |
176 | #define SMA1303_PCM_N_SLOT7 (6<<0) |
177 | #define SMA1303_PCM_N_SLOT8 (7<<0) |
178 | #define SMA1303_PCM_N_SLOT9 (8<<0) |
179 | #define SMA1303_PCM_N_SLOT10 (9<<0) |
180 | #define SMA1303_PCM_N_SLOT11 (10<<0) |
181 | #define SMA1303_PCM_N_SLOT12 (11<<0) |
182 | #define SMA1303_PCM_N_SLOT13 (12<<0) |
183 | #define SMA1303_PCM_N_SLOT14 (13<<0) |
184 | #define SMA1303_PCM_N_SLOT15 (14<<0) |
185 | #define SMA1303_PCM_N_SLOT16 (15<<0) |
186 | |
187 | /* INTPUT CTRL4 : 0x04 */ |
188 | #define SMA1303_PCM1_SLOT_MASK (15<<4) |
189 | #define SMA1303_PCM1_SLOT1 (0<<4) |
190 | #define SMA1303_PCM1_SLOT2 (1<<4) |
191 | #define SMA1303_PCM1_SLOT3 (2<<4) |
192 | #define SMA1303_PCM1_SLOT4 (3<<4) |
193 | #define SMA1303_PCM1_SLOT5 (4<<4) |
194 | #define SMA1303_PCM1_SLOT6 (5<<4) |
195 | #define SMA1303_PCM1_SLOT7 (6<<4) |
196 | #define SMA1303_PCM1_SLOT8 (7<<4) |
197 | #define SMA1303_PCM1_SLOT9 (8<<4) |
198 | #define SMA1303_PCM1_SLOT10 (9<<4) |
199 | #define SMA1303_PCM1_SLOT11 (10<<4) |
200 | #define SMA1303_PCM1_SLOT12 (11<<4) |
201 | #define SMA1303_PCM1_SLOT13 (12<<4) |
202 | #define SMA1303_PCM1_SLOT14 (13<<4) |
203 | #define SMA1303_PCM1_SLOT15 (14<<4) |
204 | #define SMA1303_PCM1_SLOT16 (15<<4) |
205 | |
206 | #define SMA1303_PCM2_SLOT_MASK (15<<0) |
207 | #define SMA1303_PCM2_SLOT1 (0<<0) |
208 | #define SMA1303_PCM2_SLOT2 (1<<0) |
209 | #define SMA1303_PCM2_SLOT3 (2<<0) |
210 | #define SMA1303_PCM2_SLOT4 (3<<0) |
211 | #define SMA1303_PCM2_SLOT5 (4<<0) |
212 | #define SMA1303_PCM2_SLOT6 (5<<0) |
213 | #define SMA1303_PCM2_SLOT7 (6<<0) |
214 | #define SMA1303_PCM2_SLOT8 (7<<0) |
215 | #define SMA1303_PCM2_SLOT9 (8<<0) |
216 | #define SMA1303_PCM2_SLOT10 (9<<0) |
217 | #define SMA1303_PCM2_SLOT11 (10<<0) |
218 | #define SMA1303_PCM2_SLOT12 (11<<0) |
219 | #define SMA1303_PCM2_SLOT13 (12<<0) |
220 | #define SMA1303_PCM2_SLOT14 (13<<0) |
221 | #define SMA1303_PCM2_SLOT15 (14<<0) |
222 | #define SMA1303_PCM2_SLOT16 (15<<0) |
223 | |
224 | /* OUTPUT CTRL : 0x09 */ |
225 | #define SMA1303_PORT_CONFIG_MASK (3<<5) |
226 | #define SMA1303_INPUT_PORT_ONLY (0<<5) |
227 | #define SMA1303_OUTPUT_PORT_ENABLE (2<<5) |
228 | |
229 | #define SMA1303_PORT_OUT_SEL_MASK (7<<0) |
230 | #define SMA1303_OUT_SEL_DISABLE (0<<0) |
231 | #define SMA1303_FORMAT_CONVERTER (1<<0) |
232 | #define SMA1303_MIXER_OUTPUT (2<<0) |
233 | #define SMA1303_SPEAKER_PATH (3<<0) |
234 | #define SMA1303_POSTSCALER_OUTPUT (4<<0) |
235 | |
236 | /* BST_TEST : 0x0B */ |
237 | #define SMA1303_BST_OFF_SLOPE_MASK (3<<6) |
238 | #define SMA1303_BST_OFF_SLOPE_6_7ns (0<<6) |
239 | #define SMA1303_BST_OFF_SLOPE_4_8ns (1<<6) |
240 | #define SMA1303_BST_OFF_SLOPE_2_6ns (2<<6) |
241 | #define SMA1303_BST_OFF_SLOPE_1_2ns (3<<6) |
242 | |
243 | #define SMA1303_OCP_TEST_MASK (1<<5) |
244 | #define SMA1303_OCP_NORMAL_MODE (0<<5) |
245 | #define SMA1303_OCP_TEST_MODE (1<<5) |
246 | |
247 | #define SMA1303_BST_FAST_LEBN_MASK (1<<4) |
248 | #define SMA1303_BST_SHORT_LEB (0<<4) |
249 | #define SMA1303_BST_LONG_LEB (1<<4) |
250 | |
251 | #define SMA1303_HIGH_PGAIN_MASK (1<<3) |
252 | #define SMA1303_NORMAL_P_GAIN (0<<3) |
253 | #define SMA1303_HIGH_P_GAIN (1<<3) |
254 | |
255 | #define SMA1303_VCOMP_MASK (1<<2) |
256 | #define SMA1303_VCOMP_NORMAL_MODE (0<<2) |
257 | #define SMA1303_VCOMP_V_MON_MODE (1<<2) |
258 | |
259 | #define SMA1303_PMOS_ON_MASK (1<<1) |
260 | #define SMA1303_PMOS_NORMAL_MODE (0<<1) |
261 | #define SMA1303_PMOS_TEST_MODE (1<<1) |
262 | |
263 | #define SMA1303_NMOS_ON_MASK (1<<0) |
264 | #define SMA1303_NMOS_NORMAL_MODE (0<<0) |
265 | #define SMA1303_NMOS_TEST_MODE (1<<0) |
266 | |
267 | /* BST_TEST1 : 0x0C */ |
268 | #define SMA1303_SET_OCP_H_MASK (3<<6) |
269 | #define SMA1303_HIGH_OCP_4_5_LVL (0<<6) |
270 | #define SMA1303_HIGH_OCP_3_2_LVL (1<<6) |
271 | #define SMA1303_HIGH_OCP_2_1_LVL (2<<6) |
272 | #define SMA1303_HIGH_OCP_0_9_LVL (3<<6) |
273 | |
274 | #define SMA1303_OCL_TEST_MASK (1<<5) |
275 | #define SMA1303_OCL_NORMAL_MODE (0<<5) |
276 | #define SMA1303_OCL_TEST_MODE (1<<5) |
277 | |
278 | #define SMA1303_LOOP_CHECK_MASK (1<<4) |
279 | #define SMA1303_BST_LOOP_NORMAL_MODE (0<<4) |
280 | #define SMA1303_BST_LOOP_CHECK_MODE (1<<4) |
281 | |
282 | #define SMA1303_EN_SH_PRT_MASK (1<<3) |
283 | #define SMA1303_EN_SH_PRT_DISABLE (0<<3) |
284 | #define SMA1303_EN_SH_PRT_ENABLE (1<<3) |
285 | |
286 | /* SPK_TEST : 0x0D */ |
287 | #define SMA1303_VREF_MON_MASK (1<<3) |
288 | #define SMA1303_VREF_NORMAL_MODE (0<<3) |
289 | #define SMA1303_VREF_V_MON_MODE (1<<3) |
290 | |
291 | #define SMA1303_SPK_OCP_DLYN_MASK (1<<2) |
292 | #define SMA1303_SPK_OCP_LONG_DELAY (0<<2) |
293 | #define SMA1303_SPK_OCP_NORMAL (1<<2) |
294 | |
295 | #define SMA1303_SPK_OFF_SLOPE_MASK (3<<0) |
296 | #define SMA1303_SPK_OFF_SLOPE_SLOW (0<<0) |
297 | #define SMA1303_SPK_OFF_SLOPE_FAST (3<<0) |
298 | |
299 | /* MUTE_VOL_CTRL : 0x0E */ |
300 | #define SMA1303_VOL_SLOPE_MASK (3<<6) |
301 | #define SMA1303_VOL_SLOPE_OFF (0<<6) |
302 | #define SMA1303_VOL_SLOPE_SLOW (1<<6) |
303 | #define SMA1303_VOL_SLOPE_MID (2<<6) |
304 | #define SMA1303_VOL_SLOPE_FAST (3<<6) |
305 | |
306 | #define SMA1303_MUTE_SLOPE_MASK (3<<4) |
307 | #define SMA1303_MUTE_SLOPE_OFF (0<<4) |
308 | #define SMA1303_MUTE_SLOPE_SLOW (1<<4) |
309 | #define SMA1303_MUTE_SLOPE_MID (2<<4) |
310 | #define SMA1303_MUTE_SLOPE_FAST (3<<4) |
311 | |
312 | #define SMA1303_SPK_MUTE_MASK (1<<0) |
313 | #define SMA1303_SPK_UNMUTE (0<<0) |
314 | #define SMA1303_SPK_MUTE (1<<0) |
315 | |
316 | /* SYSTEM_CTRL1 :0x10 */ |
317 | #define SMA1303_SPK_MODE_MASK (7<<2) |
318 | #define SMA1303_SPK_OFF (0<<2) |
319 | #define SMA1303_SPK_MONO (1<<2) |
320 | #define SMA1303_SPK_STEREO (4<<2) |
321 | |
322 | /* SYSTEM_CTRL2 : 0x11 */ |
323 | #define SMA1303_SPK_BS_MASK (1<<6) |
324 | #define SMA1303_SPK_BS_BYP (0<<6) |
325 | #define SMA1303_SPK_BS_EN (1<<6) |
326 | #define SMA1303_SPK_LIM_MASK (1<<5) |
327 | #define SMA1303_SPK_LIM_BYP (0<<5) |
328 | #define SMA1303_SPK_LIM_EN (1<<5) |
329 | |
330 | #define SMA1303_LR_DATA_SW_MASK (1<<4) |
331 | #define SMA1303_LR_DATA_SW_NORMAL (0<<4) |
332 | #define SMA1303_LR_DATA_SW_SWAP (1<<4) |
333 | |
334 | #define SMA1303_MONOMIX_MASK (1<<0) |
335 | #define SMA1303_MONOMIX_OFF (0<<0) |
336 | #define SMA1303_MONOMIX_ON (1<<0) |
337 | |
338 | /* SYSTEM_CTRL3 : 0x12 */ |
339 | #define SMA1303_INPUT_MASK (3<<6) |
340 | #define SMA1303_INPUT_0_DB (0<<6) |
341 | #define SMA1303_INPUT_M6_DB (1<<6) |
342 | #define SMA1303_INPUT_M12_DB (2<<6) |
343 | #define SMA1303_INPUT_INFI_DB (3<<6) |
344 | #define SMA1303_INPUT_R_MASK (3<<4) |
345 | #define SMA1303_INPUT_R_0_DB (0<<4) |
346 | #define SMA1303_INPUT_R_M6_DB (1<<4) |
347 | #define SMA1303_INPUT_R_M12_DB (2<<4) |
348 | #define SMA1303_INPUT_R_INFI_DB (3<<4) |
349 | |
350 | /* Modulator : 0x14 */ |
351 | #define SMA1303_SPK_HYSFB_MASK (3<<6) |
352 | #define SMA1303_HYSFB_625K (0<<6) |
353 | #define SMA1303_HYSFB_414K (1<<6) |
354 | #define SMA1303_HYSFB_297K (2<<6) |
355 | #define SMA1303_HYSFB_226K (3<<6) |
356 | #define SMA1303_SPK_BDELAY_MASK (63<<0) |
357 | |
358 | /* SDM CONTROL : 0x33 */ |
359 | #define SMA1303_SDM_Q_SEL_MASK (1<<2) |
360 | #define SMA1303_QUART_SEL_1_DIV_4 (0<<2) |
361 | #define SMA1303_QUART_SEL_1_DIV_8 (1<<2) |
362 | |
363 | /* OTP_DATA1 : 0x34 */ |
364 | #define SMA1303_OTP_LVL_MASK (1<<5) |
365 | #define SMA1303_OTP_LVL_NORMAL (0<<5) |
366 | #define SMA1303_OTP_LVL_LOW (1<<5) |
367 | |
368 | /* PROTECTION : 0x36 */ |
369 | #define SMA1303_EDGE_DIS_MASK (1<<7) |
370 | #define SMA1303_EDGE_DIS_ENABLE (0<<7) |
371 | #define SMA1303_EDGE_DIS_DISABLE (1<<7) |
372 | |
373 | #define SMA1303_SPK_OCP_DIS_MASK (1<<3) |
374 | #define SMA1303_SPK_OCP_ENABLE (0<<3) |
375 | #define SMA1303_SPK_OCP_DISABLE (1<<3) |
376 | |
377 | #define SMA1303_OCP_MODE_MASK (1<<2) |
378 | #define SMA1303_AUTO_RECOVER (0<<2) |
379 | #define SMA1303_SHUT_DOWN_PERMANENT (1<<2) |
380 | |
381 | #define SMA1303_OTP_MODE_MASK (3<<0) |
382 | #define SMA1303_OTP_MODE_DISABLE (0<<0) |
383 | #define SMA1303_IG_THR1_SHUT_THR2 (1<<0) |
384 | #define SMA1303_REC_THR1_SHUT_THR2 (2<<0) |
385 | #define SMA1303_SHUT_THR1_SHUT_THR2 (3<<0) |
386 | |
387 | /* TEST2 : 0x3C */ |
388 | #define SMA1303_SPK_HSDM_BP_MASK (1<<4) |
389 | #define SMA1303_SPK_HSDM_ENABLE (0<<4) |
390 | #define SMA1303_SPK_HSDM_BYPASS (1<<4) |
391 | |
392 | #define SMA1303_SDM_SYNC_DIS_MASK (1<<5) |
393 | #define SMA1303_SDM_SYNC_NORMAL (0<<5) |
394 | #define SMA1303_SDM_SYNC_DISABLE (1<<5) |
395 | |
396 | /* ATEST2 : 0x3F */ |
397 | #define SMA1303_SPK_OUT_FREQ_MASK (1<<2) |
398 | #define SMA1303_SPK_OUT_FREQ_360K (0<<2) |
399 | #define SMA1303_SPK_OUT_FREQ_410K (1<<2) |
400 | |
401 | #define SMA1303_LOW_POWER_MODE_MASK (1<<3) |
402 | #define SMA1303_LOW_POWER_MODE_DISABLE (0<<3) |
403 | #define SMA1303_LOW_POWER_MODE_ENABLE (1<<3) |
404 | |
405 | #define SMA1303_THERMAL_ADJUST_MASK (3<<5) |
406 | #define SMA1303_THERMAL_150_110 (0<<5) |
407 | #define SMA1303_THERMAL_160_120 (1<<5) |
408 | #define SMA1303_THERMAL_140_100 (2<<5) |
409 | |
410 | #define SMA1303_FAST_OFF_DRIVE_SPK_MASK (1<<0) |
411 | #define SMA1303_FAST_OFF_DRIVE_SPK_DISABLE (0<<0) |
412 | #define SMA1303_FAST_OFF_DRIVE_SPK_ENABLE (1<<0) |
413 | |
414 | /* PLL_CTRL : 0x8E */ |
415 | #define SMA1303_TRM_LVL_MASK (1<<4) |
416 | #define SMA1303_TRM_LVL_NORMAL (0<<4) |
417 | #define SMA1303_TRM_LVL_LOW (1<<4) |
418 | |
419 | #define SMA1303_LOW_OCL_MODE_MASK (1<<3) |
420 | #define SMA1303_LOW_OCL_MODE (0<<3) |
421 | #define SMA1303_NORMAL_OCL_MODE (1<<3) |
422 | |
423 | #define SMA1303_PLL_PD2_MASK (7<<0) |
424 | #define SMA1303_PLL_PD2 (7<<0) |
425 | #define SMA1303_PLL_OPERATION2 (0<<0) |
426 | |
427 | /* POSTSCALER : 0x90 */ |
428 | #define SMA1303_BYP_POST_MASK (1<<0) |
429 | #define SMA1303_EN_POST_SCALER (0<<0) |
430 | #define SMA1303_BYP_POST_SCALER (1<<0) |
431 | |
432 | /* FDPEC CONTROL : 0x92 */ |
433 | #define SMA1303_FLT_VDD_GAIN_MASK (15<<4) |
434 | #define SMA1303_FLT_VDD_GAIN_2P40 (0<<4) |
435 | #define SMA1303_FLT_VDD_GAIN_2P45 (1<<4) |
436 | #define SMA1303_FLT_VDD_GAIN_2P50 (2<<4) |
437 | #define SMA1303_FLT_VDD_GAIN_2P55 (3<<4) |
438 | #define SMA1303_FLT_VDD_GAIN_2P60 (4<<4) |
439 | #define SMA1303_FLT_VDD_GAIN_2P65 (5<<4) |
440 | #define SMA1303_FLT_VDD_GAIN_2P70 (6<<4) |
441 | #define SMA1303_FLT_VDD_GAIN_2P75 (7<<4) |
442 | #define SMA1303_FLT_VDD_GAIN_2P80 (8<<4) |
443 | #define SMA1303_FLT_VDD_GAIN_2P85 (9<<4) |
444 | #define SMA1303_FLT_VDD_GAIN_2P90 (10<<4) |
445 | #define SMA1303_FLT_VDD_GAIN_2P95 (11<<4) |
446 | #define SMA1303_FLT_VDD_GAIN_3P00 (12<<4) |
447 | #define SMA1303_FLT_VDD_GAIN_3P05 (13<<4) |
448 | #define SMA1303_FLT_VDD_GAIN_3P10 (14<<4) |
449 | #define SMA1303_FLT_VDD_GAIN_3P15 (15<<4) |
450 | |
451 | #define SMA1303_DIS_FCHG_MASK (1<<2) |
452 | #define SMA1303_EN_FAST_CHARGE (0<<2) |
453 | #define SMA1303_DIS_FAST_CHARGE (1<<2) |
454 | |
455 | /* BOOST_CONTROL4 : 0x97 */ |
456 | #define SMA1303_TRM_VBST_MASK (7<<2) |
457 | #define SMA1303_TRM_VBST_5P5 (0<<2) |
458 | #define SMA1303_TRM_VBST_5P6 (1<<2) |
459 | #define SMA1303_TRM_VBST_5P7 (2<<2) |
460 | #define SMA1303_TRM_VBST_5P8 (3<<2) |
461 | #define SMA1303_TRM_VBST_5P9 (4<<2) |
462 | #define SMA1303_TRM_VBST_6P0 (5<<2) |
463 | #define SMA1303_TRM_VBST_6P1 (6<<2) |
464 | #define SMA1303_TRM_VBST_6P2 (7<<2) |
465 | |
466 | /* TOP_MAN1 : 0xA2 */ |
467 | #define SMA1303_PLL_LOCK_SKIP_MASK (1<<7) |
468 | #define SMA1303_PLL_LOCK_ENABLE (0<<7) |
469 | #define SMA1303_PLL_LOCK_DISABLE (1<<7) |
470 | |
471 | #define SMA1303_PLL_PD_MASK (1<<6) |
472 | #define SMA1303_PLL_OPERATION (0<<6) |
473 | #define SMA1303_PLL_PD (1<<6) |
474 | |
475 | #define SMA1303_PLL_DIV_MASK (3<<4) |
476 | #define SMA1303_PLL_OUT (0<<4) |
477 | #define SMA1303_PLL_OUT_2 (1<<4) |
478 | #define SMA1303_PLL_OUT_4 (2<<4) |
479 | #define SMA1303_PLL_OUT_8 (3<<4) |
480 | |
481 | #define SMA1303_PLL_REF_CLK_MASK (1<<3) |
482 | #define SMA1303_PLL_REF_CLK1 (0<<3) |
483 | #define SMA1303_PLL_SCK (1<<3) |
484 | |
485 | #define SMA1303_DAC_DN_CONV_MASK (1<<2) |
486 | #define SMA1303_DAC_DN_CONV_DISABLE (0<<2) |
487 | #define SMA1303_DAC_DN_CONV_ENABLE (1<<2) |
488 | |
489 | #define SMA1303_SDO_IO_MASK (1<<1) |
490 | #define SMA1303_HIGH_Z_LRCK_H (0<<1) |
491 | #define SMA1303_HIGH_Z_LRCK_L (1<<1) |
492 | |
493 | #define SMA1303_SDO_OUTPUT2_MASK (1<<0) |
494 | #define SMA1303_SDO_NORMAL (0<<0) |
495 | #define SMA1303_SDO_OUTPUT_ONLY (1<<0) |
496 | |
497 | /* TOP_MAN2 : 0xA3 */ |
498 | #define SMA1303_MON_OSC_PLL_MASK (1<<7) |
499 | #define SMA1303_PLL_SDO (0<<7) |
500 | #define SMA1303_OSC_SDO (1<<7) |
501 | |
502 | #define SMA1303_TEST_CLKO_EN_MASK (1<<6) |
503 | #define SMA1303_NORMAL_SDO (0<<6) |
504 | #define SMA1303_CLK_OUT_SDO (1<<6) |
505 | |
506 | #define SMA1303_SDO_OUTPUT_MASK (1<<3) |
507 | #define SMA1303_NORMAL_OUT (0<<3) |
508 | #define SMA1303_HIGH_Z_OUT (1<<3) |
509 | |
510 | #define SMA1303_CLOCK_MON_MASK (1<<1) |
511 | #define SMA1303_CLOCK_MON (0<<1) |
512 | #define SMA1303_CLOCK_NOT_MON (1<<1) |
513 | |
514 | #define SMA1303_OSC_PD_MASK (1<<0) |
515 | #define SMA1303_NORMAL_OPERATION_OSC (0<<0) |
516 | #define SMA1303_POWER_DOWN_OSC (1<<0) |
517 | |
518 | /* TOP_MAN3 0xA4 */ |
519 | #define SMA1303_O_FORMAT_MASK (7<<5) |
520 | #define SMA1303_O_FMT_LJ (1<<5) |
521 | #define SMA1303_O_FMT_I2S (2<<5) |
522 | #define SMA1303_O_FMT_TDM (4<<5) |
523 | |
524 | #define SMA1303_SCK_RATE_MASK (1<<3) |
525 | #define SMA1303_SCK_64FS (0<<3) |
526 | #define SMA1303_SCK_32FS (2<<3) |
527 | |
528 | #define SMA1303_LRCK_POL_MASK (1<<0) |
529 | #define SMA1303_L_VALID (0<<0) |
530 | #define SMA1303_R_VALID (1<<0) |
531 | |
532 | /* TDM1 FORMAT : 0xA5 */ |
533 | #define SMA1303_TDM_CLK_POL_MASK (1<<7) |
534 | #define SMA1303_TDM_CLK_POL_RISE (0<<7) |
535 | #define SMA1303_TDM_CLK_POL_FALL (1<<7) |
536 | |
537 | #define SMA1303_TDM_TX_MODE_MASK (1<<6) |
538 | #define SMA1303_TDM_TX_MONO (0<<6) |
539 | #define SMA1303_TDM_TX_STEREO (1<<6) |
540 | |
541 | #define SMA1303_TDM_SLOT1_RX_POS_MASK (7<<3) |
542 | #define SMA1303_TDM_SLOT1_RX_POS_0 (0<<3) |
543 | #define SMA1303_TDM_SLOT1_RX_POS_1 (1<<3) |
544 | #define SMA1303_TDM_SLOT1_RX_POS_2 (2<<3) |
545 | #define SMA1303_TDM_SLOT1_RX_POS_3 (3<<3) |
546 | #define SMA1303_TDM_SLOT1_RX_POS_4 (4<<3) |
547 | #define SMA1303_TDM_SLOT1_RX_POS_5 (5<<3) |
548 | #define SMA1303_TDM_SLOT1_RX_POS_6 (6<<3) |
549 | #define SMA1303_TDM_SLOT1_RX_POS_7 (7<<3) |
550 | |
551 | #define SMA1303_TDM_SLOT2_RX_POS_MASK (7<<0) |
552 | #define SMA1303_TDM_SLOT2_RX_POS_0 (0<<0) |
553 | #define SMA1303_TDM_SLOT2_RX_POS_1 (1<<0) |
554 | #define SMA1303_TDM_SLOT2_RX_POS_2 (2<<0) |
555 | #define SMA1303_TDM_SLOT2_RX_POS_3 (3<<0) |
556 | #define SMA1303_TDM_SLOT2_RX_POS_4 (4<<0) |
557 | #define SMA1303_TDM_SLOT2_RX_POS_5 (5<<0) |
558 | #define SMA1303_TDM_SLOT2_RX_POS_6 (6<<0) |
559 | #define SMA1303_TDM_SLOT2_RX_POS_7 (7<<0) |
560 | |
561 | /* TDM2 FORMAT : 0xA6 */ |
562 | #define SMA1303_TDM_DL_MASK (1<<7) |
563 | #define SMA1303_TDM_DL_16 (0<<7) |
564 | #define SMA1303_TDM_DL_32 (1<<7) |
565 | |
566 | #define SMA1303_TDM_N_SLOT_MASK (1<<6) |
567 | #define SMA1303_TDM_N_SLOT_4 (0<<6) |
568 | #define SMA1303_TDM_N_SLOT_8 (1<<6) |
569 | |
570 | #define SMA1303_TDM_SLOT1_TX_POS_MASK (7<<3) |
571 | #define SMA1303_TDM_SLOT1_TX_POS_0 (0<<3) |
572 | #define SMA1303_TDM_SLOT1_TX_POS_1 (1<<3) |
573 | #define SMA1303_TDM_SLOT1_TX_POS_2 (2<<3) |
574 | #define SMA1303_TDM_SLOT1_TX_POS_3 (3<<3) |
575 | #define SMA1303_TDM_SLOT1_TX_POS_4 (4<<3) |
576 | #define SMA1303_TDM_SLOT1_TX_POS_5 (5<<3) |
577 | #define SMA1303_TDM_SLOT1_TX_POS_6 (6<<3) |
578 | #define SMA1303_TDM_SLOT1_TX_POS_7 (7<<3) |
579 | |
580 | #define SMA1303_TDM_SLOT2_TX_POS_MASK (7<<0) |
581 | #define SMA1303_TDM_SLOT2_TX_POS_0 (0<<0) |
582 | #define SMA1303_TDM_SLOT2_TX_POS_1 (1<<0) |
583 | #define SMA1303_TDM_SLOT2_TX_POS_2 (2<<0) |
584 | #define SMA1303_TDM_SLOT2_TX_POS_3 (3<<0) |
585 | #define SMA1303_TDM_SLOT2_TX_POS_4 (4<<0) |
586 | #define SMA1303_TDM_SLOT2_TX_POS_5 (5<<0) |
587 | #define SMA1303_TDM_SLOT2_TX_POS_6 (6<<0) |
588 | #define SMA1303_TDM_SLOT2_TX_POS_7 (7<<0) |
589 | |
590 | /* STATUS1 : 0xFA */ |
591 | #define SMA1303_OT1_OK_STATUS (1<<7) |
592 | #define SMA1303_OT2_OK_STATUS (1<<6) |
593 | |
594 | /* STATUS2 : 0xFB */ |
595 | #define SMA1303_OCP_SPK_STATUS (1<<5) |
596 | #define SMA1303_OCP_BST_STATUS (1<<4) |
597 | #define SMA1303_OTP_STAT_OK_0 (5<<1) |
598 | #define SMA1303_OTP_STAT_OK_1 (2<<2) |
599 | |
600 | #define SMA1303_CLK_MON_STATUS (1<<0) |
601 | |
602 | /* DEVICE_INFO : 0xFF */ |
603 | #define SMA1303_DEVICE_ID (2<<3) |
604 | #define SMA1303_UVLO_BST_STATUS (1<<2) |
605 | #define SMA1303_REV_NUM_STATUS (3<<0) |
606 | #define SMA1303_REV_NUM_TV0 (0<<0) |
607 | #define SMA1303_REV_NUM_TV1 (1<<0) |
608 | |
609 | #endif |
610 | |