| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system |
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| 4 | * |
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| 5 | * Copyright: 2011 Raumfeld GmbH |
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| 6 | * Author: Sven Brandau <info@brandau.biz> |
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| 7 | * |
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| 8 | * based on code from: |
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| 9 | * Raumfeld GmbH |
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| 10 | * Johannes Stezenbach <js@sig21.net> |
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| 11 | * Wolfson Microelectronics PLC. |
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| 12 | * Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| 13 | */ |
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| 14 | #ifndef _ASOC_STA_350_H |
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| 15 | #define _ASOC_STA_350_H |
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| 16 | |
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| 17 | /* STA350 register addresses */ |
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| 18 | |
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| 19 | #define STA350_REGISTER_COUNT 0x4D |
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| 20 | #define STA350_COEF_COUNT 62 |
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| 21 | |
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| 22 | #define STA350_CONFA 0x00 |
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| 23 | #define STA350_CONFB 0x01 |
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| 24 | #define STA350_CONFC 0x02 |
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| 25 | #define STA350_CONFD 0x03 |
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| 26 | #define STA350_CONFE 0x04 |
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| 27 | #define STA350_CONFF 0x05 |
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| 28 | #define STA350_MMUTE 0x06 |
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| 29 | #define STA350_MVOL 0x07 |
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| 30 | #define STA350_C1VOL 0x08 |
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| 31 | #define STA350_C2VOL 0x09 |
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| 32 | #define STA350_C3VOL 0x0a |
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| 33 | #define STA350_AUTO1 0x0b |
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| 34 | #define STA350_AUTO2 0x0c |
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| 35 | #define STA350_AUTO3 0x0d |
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| 36 | #define STA350_C1CFG 0x0e |
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| 37 | #define STA350_C2CFG 0x0f |
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| 38 | #define STA350_C3CFG 0x10 |
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| 39 | #define STA350_TONE 0x11 |
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| 40 | #define STA350_L1AR 0x12 |
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| 41 | #define STA350_L1ATRT 0x13 |
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| 42 | #define STA350_L2AR 0x14 |
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| 43 | #define STA350_L2ATRT 0x15 |
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| 44 | #define STA350_CFADDR2 0x16 |
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| 45 | #define STA350_B1CF1 0x17 |
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| 46 | #define STA350_B1CF2 0x18 |
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| 47 | #define STA350_B1CF3 0x19 |
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| 48 | #define STA350_B2CF1 0x1a |
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| 49 | #define STA350_B2CF2 0x1b |
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| 50 | #define STA350_B2CF3 0x1c |
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| 51 | #define STA350_A1CF1 0x1d |
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| 52 | #define STA350_A1CF2 0x1e |
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| 53 | #define STA350_A1CF3 0x1f |
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| 54 | #define STA350_A2CF1 0x20 |
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| 55 | #define STA350_A2CF2 0x21 |
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| 56 | #define STA350_A2CF3 0x22 |
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| 57 | #define STA350_B0CF1 0x23 |
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| 58 | #define STA350_B0CF2 0x24 |
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| 59 | #define STA350_B0CF3 0x25 |
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| 60 | #define STA350_CFUD 0x26 |
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| 61 | #define STA350_MPCC1 0x27 |
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| 62 | #define STA350_MPCC2 0x28 |
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| 63 | #define STA350_DCC1 0x29 |
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| 64 | #define STA350_DCC2 0x2a |
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| 65 | #define STA350_FDRC1 0x2b |
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| 66 | #define STA350_FDRC2 0x2c |
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| 67 | #define STA350_STATUS 0x2d |
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| 68 | /* reserved: 0x2d - 0x30 */ |
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| 69 | #define STA350_EQCFG 0x31 |
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| 70 | #define STA350_EATH1 0x32 |
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| 71 | #define STA350_ERTH1 0x33 |
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| 72 | #define STA350_EATH2 0x34 |
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| 73 | #define STA350_ERTH2 0x35 |
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| 74 | #define STA350_CONFX 0x36 |
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| 75 | #define STA350_SVCA 0x37 |
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| 76 | #define STA350_SVCB 0x38 |
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| 77 | #define STA350_RMS0A 0x39 |
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| 78 | #define STA350_RMS0B 0x3a |
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| 79 | #define STA350_RMS0C 0x3b |
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| 80 | #define STA350_RMS1A 0x3c |
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| 81 | #define STA350_RMS1B 0x3d |
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| 82 | #define STA350_RMS1C 0x3e |
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| 83 | #define STA350_EVOLRES 0x3f |
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| 84 | /* reserved: 0x40 - 0x47 */ |
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| 85 | #define STA350_NSHAPE 0x48 |
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| 86 | #define STA350_CTXB4B1 0x49 |
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| 87 | #define STA350_CTXB7B5 0x4a |
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| 88 | #define STA350_MISC1 0x4b |
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| 89 | #define STA350_MISC2 0x4c |
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| 90 | |
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| 91 | /* 0x00 CONFA */ |
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| 92 | #define STA350_CONFA_MCS_MASK 0x03 |
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| 93 | #define STA350_CONFA_MCS_SHIFT 0 |
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| 94 | #define STA350_CONFA_IR_MASK 0x18 |
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| 95 | #define STA350_CONFA_IR_SHIFT 3 |
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| 96 | #define STA350_CONFA_TWRB BIT(5) |
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| 97 | #define STA350_CONFA_TWAB BIT(6) |
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| 98 | #define STA350_CONFA_FDRB BIT(7) |
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| 99 | |
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| 100 | /* 0x01 CONFB */ |
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| 101 | #define STA350_CONFB_SAI_MASK 0x0f |
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| 102 | #define STA350_CONFB_SAI_SHIFT 0 |
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| 103 | #define STA350_CONFB_SAIFB BIT(4) |
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| 104 | #define STA350_CONFB_DSCKE BIT(5) |
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| 105 | #define STA350_CONFB_C1IM BIT(6) |
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| 106 | #define STA350_CONFB_C2IM BIT(7) |
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| 107 | |
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| 108 | /* 0x02 CONFC */ |
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| 109 | #define STA350_CONFC_OM_MASK 0x03 |
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| 110 | #define STA350_CONFC_OM_SHIFT 0 |
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| 111 | #define STA350_CONFC_CSZ_MASK 0x3c |
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| 112 | #define STA350_CONFC_CSZ_SHIFT 2 |
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| 113 | #define STA350_CONFC_OCRB BIT(7) |
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| 114 | |
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| 115 | /* 0x03 CONFD */ |
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| 116 | #define STA350_CONFD_HPB_SHIFT 0 |
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| 117 | #define STA350_CONFD_DEMP_SHIFT 1 |
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| 118 | #define STA350_CONFD_DSPB_SHIFT 2 |
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| 119 | #define STA350_CONFD_PSL_SHIFT 3 |
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| 120 | #define STA350_CONFD_BQL_SHIFT 4 |
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| 121 | #define STA350_CONFD_DRC_SHIFT 5 |
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| 122 | #define STA350_CONFD_ZDE_SHIFT 6 |
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| 123 | #define STA350_CONFD_SME_SHIFT 7 |
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| 124 | |
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| 125 | /* 0x04 CONFE */ |
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| 126 | #define STA350_CONFE_MPCV BIT(0) |
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| 127 | #define STA350_CONFE_MPCV_SHIFT 0 |
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| 128 | #define STA350_CONFE_MPC BIT(1) |
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| 129 | #define STA350_CONFE_MPC_SHIFT 1 |
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| 130 | #define STA350_CONFE_NSBW BIT(2) |
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| 131 | #define STA350_CONFE_NSBW_SHIFT 2 |
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| 132 | #define STA350_CONFE_AME BIT(3) |
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| 133 | #define STA350_CONFE_AME_SHIFT 3 |
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| 134 | #define STA350_CONFE_PWMS BIT(4) |
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| 135 | #define STA350_CONFE_PWMS_SHIFT 4 |
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| 136 | #define STA350_CONFE_DCCV BIT(5) |
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| 137 | #define STA350_CONFE_DCCV_SHIFT 5 |
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| 138 | #define STA350_CONFE_ZCE BIT(6) |
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| 139 | #define STA350_CONFE_ZCE_SHIFT 6 |
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| 140 | #define STA350_CONFE_SVE BIT(7) |
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| 141 | #define STA350_CONFE_SVE_SHIFT 7 |
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| 142 | |
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| 143 | /* 0x05 CONFF */ |
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| 144 | #define STA350_CONFF_OCFG_MASK 0x03 |
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| 145 | #define STA350_CONFF_OCFG_SHIFT 0 |
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| 146 | #define STA350_CONFF_IDE BIT(2) |
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| 147 | #define STA350_CONFF_BCLE BIT(3) |
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| 148 | #define STA350_CONFF_LDTE BIT(4) |
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| 149 | #define STA350_CONFF_ECLE BIT(5) |
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| 150 | #define STA350_CONFF_PWDN BIT(6) |
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| 151 | #define STA350_CONFF_EAPD BIT(7) |
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| 152 | |
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| 153 | /* 0x06 MMUTE */ |
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| 154 | #define STA350_MMUTE_MMUTE 0x01 |
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| 155 | #define STA350_MMUTE_MMUTE_SHIFT 0 |
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| 156 | #define STA350_MMUTE_C1M 0x02 |
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| 157 | #define STA350_MMUTE_C1M_SHIFT 1 |
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| 158 | #define STA350_MMUTE_C2M 0x04 |
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| 159 | #define STA350_MMUTE_C2M_SHIFT 2 |
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| 160 | #define STA350_MMUTE_C3M 0x08 |
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| 161 | #define STA350_MMUTE_C3M_SHIFT 3 |
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| 162 | #define STA350_MMUTE_LOC_MASK 0xC0 |
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| 163 | #define STA350_MMUTE_LOC_SHIFT 6 |
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| 164 | |
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| 165 | /* 0x0b AUTO1 */ |
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| 166 | #define STA350_AUTO1_AMGC_MASK 0x30 |
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| 167 | #define STA350_AUTO1_AMGC_SHIFT 4 |
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| 168 | |
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| 169 | /* 0x0c AUTO2 */ |
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| 170 | #define STA350_AUTO2_AMAME 0x01 |
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| 171 | #define STA350_AUTO2_AMAM_MASK 0x0e |
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| 172 | #define STA350_AUTO2_AMAM_SHIFT 1 |
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| 173 | #define STA350_AUTO2_XO_MASK 0xf0 |
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| 174 | #define STA350_AUTO2_XO_SHIFT 4 |
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| 175 | |
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| 176 | /* 0x0d AUTO3 */ |
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| 177 | #define STA350_AUTO3_PEQ_MASK 0x1f |
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| 178 | #define STA350_AUTO3_PEQ_SHIFT 0 |
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| 179 | |
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| 180 | /* 0x0e 0x0f 0x10 CxCFG */ |
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| 181 | #define STA350_CxCFG_TCB_SHIFT 0 |
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| 182 | #define STA350_CxCFG_EQBP_SHIFT 1 |
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| 183 | #define STA350_CxCFG_VBP_SHIFT 2 |
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| 184 | #define STA350_CxCFG_BO_SHIFT 3 |
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| 185 | #define STA350_CxCFG_LS_SHIFT 4 |
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| 186 | #define STA350_CxCFG_OM_MASK 0xc0 |
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| 187 | #define STA350_CxCFG_OM_SHIFT 6 |
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| 188 | |
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| 189 | /* 0x11 TONE */ |
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| 190 | #define STA350_TONE_BTC_SHIFT 0 |
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| 191 | #define STA350_TONE_TTC_SHIFT 4 |
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| 192 | |
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| 193 | /* 0x12 0x13 0x14 0x15 limiter attack/release */ |
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| 194 | #define STA350_LxA_SHIFT 0 |
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| 195 | #define STA350_LxR_SHIFT 4 |
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| 196 | |
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| 197 | /* 0x26 CFUD */ |
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| 198 | #define STA350_CFUD_W1 0x01 |
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| 199 | #define STA350_CFUD_WA 0x02 |
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| 200 | #define STA350_CFUD_R1 0x04 |
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| 201 | #define STA350_CFUD_RA 0x08 |
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| 202 | |
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| 203 | |
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| 204 | /* biquad filter coefficient table offsets */ |
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| 205 | #define STA350_C1_BQ_BASE 0 |
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| 206 | #define STA350_C2_BQ_BASE 20 |
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| 207 | #define STA350_CH_BQ_NUM 4 |
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| 208 | #define STA350_BQ_NUM_COEF 5 |
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| 209 | #define STA350_XO_HP_BQ_BASE 40 |
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| 210 | #define STA350_XO_LP_BQ_BASE 45 |
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| 211 | #define STA350_C1_PRESCALE 50 |
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| 212 | #define STA350_C2_PRESCALE 51 |
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| 213 | #define STA350_C1_POSTSCALE 52 |
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| 214 | #define STA350_C2_POSTSCALE 53 |
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| 215 | #define STA350_C3_POSTSCALE 54 |
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| 216 | #define STA350_TW_POSTSCALE 55 |
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| 217 | #define STA350_C1_MIX1 56 |
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| 218 | #define STA350_C1_MIX2 57 |
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| 219 | #define STA350_C2_MIX1 58 |
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| 220 | #define STA350_C2_MIX2 59 |
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| 221 | #define STA350_C3_MIX1 60 |
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| 222 | #define STA350_C3_MIX2 61 |
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| 223 | |
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| 224 | /* miscellaneous register 1 */ |
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| 225 | #define STA350_MISC1_CPWMEN BIT(2) |
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| 226 | #define STA350_MISC1_BRIDGOFF BIT(5) |
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| 227 | #define STA350_MISC1_NSHHPEN BIT(6) |
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| 228 | #define STA350_MISC1_RPDNEN BIT(7) |
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| 229 | |
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| 230 | /* miscellaneous register 2 */ |
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| 231 | #define STA350_MISC2_PNDLSL_MASK 0x1c |
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| 232 | #define STA350_MISC2_PNDLSL_SHIFT 2 |
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| 233 | |
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| 234 | #endif /* _ASOC_STA_350_H */ |
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| 235 | |
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