| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * tfa9879.h -- driver for NXP Semiconductors TFA9879 |
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| 4 | * |
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| 5 | * Copyright (C) 2014 Axentia Technologies AB |
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| 6 | * Author: Peter Rosin <peda@axentia.se> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _TFA9879_H |
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| 10 | #define _TFA9879_H |
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| 11 | |
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| 12 | #define TFA9879_DEVICE_CONTROL 0x00 |
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| 13 | #define TFA9879_SERIAL_INTERFACE_1 0x01 |
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| 14 | #define TFA9879_PCM_IOM2_FORMAT_1 0x02 |
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| 15 | #define TFA9879_SERIAL_INTERFACE_2 0x03 |
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| 16 | #define TFA9879_PCM_IOM2_FORMAT_2 0x04 |
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| 17 | #define TFA9879_EQUALIZER_A1 0x05 |
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| 18 | #define TFA9879_EQUALIZER_A2 0x06 |
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| 19 | #define TFA9879_EQUALIZER_B1 0x07 |
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| 20 | #define TFA9879_EQUALIZER_B2 0x08 |
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| 21 | #define TFA9879_EQUALIZER_C1 0x09 |
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| 22 | #define TFA9879_EQUALIZER_C2 0x0a |
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| 23 | #define TFA9879_EQUALIZER_D1 0x0b |
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| 24 | #define TFA9879_EQUALIZER_D2 0x0c |
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| 25 | #define TFA9879_EQUALIZER_E1 0x0d |
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| 26 | #define TFA9879_EQUALIZER_E2 0x0e |
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| 27 | #define TFA9879_BYPASS_CONTROL 0x0f |
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| 28 | #define TFA9879_DYNAMIC_RANGE_COMPR 0x10 |
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| 29 | #define TFA9879_BASS_TREBLE 0x11 |
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| 30 | #define TFA9879_HIGH_PASS_FILTER 0x12 |
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| 31 | #define TFA9879_VOLUME_CONTROL 0x13 |
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| 32 | #define TFA9879_MISC_CONTROL 0x14 |
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| 33 | #define TFA9879_MISC_STATUS 0x15 |
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| 34 | |
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| 35 | /* TFA9879_DEVICE_CONTROL */ |
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| 36 | #define TFA9879_INPUT_SEL_MASK 0x0010 |
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| 37 | #define TFA9879_INPUT_SEL_SHIFT 4 |
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| 38 | #define TFA9879_OPMODE_MASK 0x0008 |
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| 39 | #define TFA9879_OPMODE_SHIFT 3 |
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| 40 | #define TFA9879_RESET_MASK 0x0002 |
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| 41 | #define TFA9879_RESET_SHIFT 1 |
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| 42 | #define TFA9879_POWERUP_MASK 0x0001 |
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| 43 | #define TFA9879_POWERUP_SHIFT 0 |
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| 44 | |
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| 45 | /* TFA9879_SERIAL_INTERFACE */ |
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| 46 | #define TFA9879_MONO_SEL_MASK 0x0c00 |
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| 47 | #define TFA9879_MONO_SEL_SHIFT 10 |
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| 48 | #define TFA9879_MONO_SEL_LEFT 0 |
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| 49 | #define TFA9879_MONO_SEL_RIGHT 1 |
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| 50 | #define TFA9879_MONO_SEL_BOTH 2 |
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| 51 | #define TFA9879_I2S_FS_MASK 0x03c0 |
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| 52 | #define TFA9879_I2S_FS_SHIFT 6 |
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| 53 | #define TFA9879_I2S_FS_8000 0 |
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| 54 | #define TFA9879_I2S_FS_11025 1 |
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| 55 | #define TFA9879_I2S_FS_12000 2 |
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| 56 | #define TFA9879_I2S_FS_16000 3 |
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| 57 | #define TFA9879_I2S_FS_22050 4 |
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| 58 | #define TFA9879_I2S_FS_24000 5 |
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| 59 | #define TFA9879_I2S_FS_32000 6 |
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| 60 | #define TFA9879_I2S_FS_44100 7 |
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| 61 | #define TFA9879_I2S_FS_48000 8 |
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| 62 | #define TFA9879_I2S_FS_64000 9 |
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| 63 | #define TFA9879_I2S_FS_88200 10 |
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| 64 | #define TFA9879_I2S_FS_96000 11 |
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| 65 | #define TFA9879_I2S_SET_MASK 0x0038 |
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| 66 | #define TFA9879_I2S_SET_SHIFT 3 |
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| 67 | #define TFA9879_I2S_SET_MSB_J_24 2 |
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| 68 | #define TFA9879_I2S_SET_I2S_24 3 |
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| 69 | #define TFA9879_I2S_SET_LSB_J_16 4 |
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| 70 | #define TFA9879_I2S_SET_LSB_J_18 5 |
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| 71 | #define TFA9879_I2S_SET_LSB_J_20 6 |
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| 72 | #define TFA9879_I2S_SET_LSB_J_24 7 |
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| 73 | #define TFA9879_SCK_POL_MASK 0x0004 |
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| 74 | #define TFA9879_SCK_POL_SHIFT 2 |
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| 75 | #define TFA9879_SCK_POL_NORMAL 0 |
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| 76 | #define TFA9879_SCK_POL_INVERSE 1 |
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| 77 | #define TFA9879_I_MODE_MASK 0x0003 |
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| 78 | #define TFA9879_I_MODE_SHIFT 0 |
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| 79 | #define TFA9879_I_MODE_I2S 0 |
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| 80 | #define TFA9879_I_MODE_PCM_IOM2_SHORT 1 |
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| 81 | #define TFA9879_I_MODE_PCM_IOM2_LONG 2 |
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| 82 | |
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| 83 | /* TFA9879_PCM_IOM2_FORMAT */ |
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| 84 | #define TFA9879_PCM_FS_MASK 0x0800 |
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| 85 | #define TFA9879_PCM_FS_SHIFT 11 |
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| 86 | #define TFA9879_A_LAW_MASK 0x0400 |
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| 87 | #define TFA9879_A_LAW_SHIFT 10 |
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| 88 | #define TFA9879_PCM_COMP_MASK 0x0200 |
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| 89 | #define TFA9879_PCM_COMP_SHIFT 9 |
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| 90 | #define TFA9879_PCM_DL_MASK 0x0100 |
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| 91 | #define TFA9879_PCM_DL_SHIFT 8 |
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| 92 | #define TFA9879_D1_SLOT_MASK 0x00f0 |
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| 93 | #define TFA9879_D1_SLOT_SHIFT 4 |
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| 94 | #define TFA9879_D2_SLOT_MASK 0x000f |
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| 95 | #define TFA9879_D2_SLOT_SHIFT 0 |
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| 96 | |
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| 97 | /* TFA9879_EQUALIZER_X1 */ |
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| 98 | #define TFA9879_T1_MASK 0x8000 |
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| 99 | #define TFA9879_T1_SHIFT 15 |
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| 100 | #define TFA9879_K1M_MASK 0x7ff0 |
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| 101 | #define TFA9879_K1M_SHIFT 4 |
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| 102 | #define TFA9879_K1E_MASK 0x000f |
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| 103 | #define TFA9879_K1E_SHIFT 0 |
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| 104 | |
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| 105 | /* TFA9879_EQUALIZER_X2 */ |
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| 106 | #define TFA9879_T2_MASK 0x8000 |
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| 107 | #define TFA9879_T2_SHIFT 15 |
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| 108 | #define TFA9879_K2M_MASK 0x7800 |
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| 109 | #define TFA9879_K2M_SHIFT 11 |
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| 110 | #define TFA9879_K2E_MASK 0x0700 |
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| 111 | #define TFA9879_K2E_SHIFT 8 |
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| 112 | #define TFA9879_K0_MASK 0x00fe |
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| 113 | #define TFA9879_K0_SHIFT 1 |
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| 114 | #define TFA9879_S_MASK 0x0001 |
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| 115 | #define TFA9879_S_SHIFT 0 |
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| 116 | |
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| 117 | /* TFA9879_BYPASS_CONTROL */ |
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| 118 | #define TFA9879_L_OCP_MASK 0x00c0 |
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| 119 | #define TFA9879_L_OCP_SHIFT 6 |
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| 120 | #define TFA9879_L_OTP_MASK 0x0030 |
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| 121 | #define TFA9879_L_OTP_SHIFT 4 |
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| 122 | #define TFA9879_CLIPCTRL_MASK 0x0008 |
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| 123 | #define TFA9879_CLIPCTRL_SHIFT 3 |
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| 124 | #define TFA9879_HPF_BP_MASK 0x0004 |
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| 125 | #define TFA9879_HPF_BP_SHIFT 2 |
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| 126 | #define TFA9879_DRC_BP_MASK 0x0002 |
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| 127 | #define TFA9879_DRC_BP_SHIFT 1 |
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| 128 | #define TFA9879_EQ_BP_MASK 0x0001 |
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| 129 | #define TFA9879_EQ_BP_SHIFT 0 |
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| 130 | |
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| 131 | /* TFA9879_DYNAMIC_RANGE_COMPR */ |
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| 132 | #define TFA9879_AT_LVL_MASK 0xf000 |
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| 133 | #define TFA9879_AT_LVL_SHIFT 12 |
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| 134 | #define TFA9879_AT_RATE_MASK 0x0f00 |
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| 135 | #define TFA9879_AT_RATE_SHIFT 8 |
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| 136 | #define TFA9879_RL_LVL_MASK 0x00f0 |
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| 137 | #define TFA9879_RL_LVL_SHIFT 4 |
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| 138 | #define TFA9879_RL_RATE_MASK 0x000f |
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| 139 | #define TFA9879_RL_RATE_SHIFT 0 |
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| 140 | |
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| 141 | /* TFA9879_BASS_TREBLE */ |
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| 142 | #define TFA9879_G_TRBLE_MASK 0x3e00 |
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| 143 | #define TFA9879_G_TRBLE_SHIFT 9 |
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| 144 | #define TFA9879_F_TRBLE_MASK 0x0180 |
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| 145 | #define TFA9879_F_TRBLE_SHIFT 7 |
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| 146 | #define TFA9879_G_BASS_MASK 0x007c |
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| 147 | #define TFA9879_G_BASS_SHIFT 2 |
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| 148 | #define TFA9879_F_BASS_MASK 0x0003 |
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| 149 | #define TFA9879_F_BASS_SHIFT 0 |
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| 150 | |
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| 151 | /* TFA9879_HIGH_PASS_FILTER */ |
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| 152 | #define TFA9879_HP_CTRL_MASK 0x00ff |
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| 153 | #define TFA9879_HP_CTRL_SHIFT 0 |
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| 154 | |
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| 155 | /* TFA9879_VOLUME_CONTROL */ |
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| 156 | #define 0x1000 |
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| 157 | #define 12 |
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| 158 | #define TFA9879_VOL_MASK 0x00ff |
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| 159 | #define TFA9879_VOL_SHIFT 0 |
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| 160 | |
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| 161 | /* TFA9879_MISC_CONTROL */ |
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| 162 | #define TFA9879_DE_PHAS_MASK 0x0c00 |
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| 163 | #define TFA9879_DE_PHAS_SHIFT 10 |
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| 164 | #define TFA9879_H_MUTE_MASK 0x0200 |
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| 165 | #define TFA9879_H_MUTE_SHIFT 9 |
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| 166 | #define TFA9879_S_MUTE_MASK 0x0100 |
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| 167 | #define TFA9879_S_MUTE_SHIFT 8 |
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| 168 | #define TFA9879_P_LIM_MASK 0x00ff |
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| 169 | #define TFA9879_P_LIM_SHIFT 0 |
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| 170 | |
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| 171 | /* TFA9879_MISC_STATUS */ |
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| 172 | #define TFA9879_PS_MASK 0x4000 |
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| 173 | #define TFA9879_PS_SHIFT 14 |
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| 174 | #define TFA9879_PORA_MASK 0x2000 |
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| 175 | #define TFA9879_PORA_SHIFT 13 |
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| 176 | #define TFA9879_AMP_MASK 0x0600 |
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| 177 | #define TFA9879_AMP_SHIFT 9 |
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| 178 | #define TFA9879_IBP_2_MASK 0x0100 |
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| 179 | #define TFA9879_IBP_2_SHIFT 8 |
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| 180 | #define TFA9879_OFP_2_MASK 0x0080 |
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| 181 | #define TFA9879_OFP_2_SHIFT 7 |
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| 182 | #define TFA9879_UFP_2_MASK 0x0040 |
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| 183 | #define TFA9879_UFP_2_SHIFT 6 |
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| 184 | #define TFA9879_IBP_1_MASK 0x0020 |
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| 185 | #define TFA9879_IBP_1_SHIFT 5 |
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| 186 | #define TFA9879_OFP_1_MASK 0x0010 |
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| 187 | #define TFA9879_OFP_1_SHIFT 4 |
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| 188 | #define TFA9879_UFP_1_MASK 0x0008 |
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| 189 | #define TFA9879_UFP_1_SHIFT 3 |
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| 190 | #define TFA9879_OCPOKA_MASK 0x0004 |
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| 191 | #define TFA9879_OCPOKA_SHIFT 2 |
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| 192 | #define TFA9879_OCPOKB_MASK 0x0002 |
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| 193 | #define TFA9879_OCPOKB_SHIFT 1 |
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| 194 | #define TFA9879_OTPOK_MASK 0x0001 |
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| 195 | #define TFA9879_OTPOK_SHIFT 0 |
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| 196 | |
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| 197 | #endif |
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| 198 | |
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