| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | // TLV320ADCX140 Sound driver |
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| 3 | // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ |
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| 4 | |
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| 5 | #ifndef _TLV320ADCX140_H |
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| 6 | #define _TLV320ADCX140_H |
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| 7 | |
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| 8 | #define ADCX140_RATES (SNDRV_PCM_RATE_44100 | \ |
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| 9 | SNDRV_PCM_RATE_48000 | \ |
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| 10 | SNDRV_PCM_RATE_96000 | \ |
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| 11 | SNDRV_PCM_RATE_192000) |
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| 12 | |
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| 13 | #define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
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| 14 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
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| 15 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
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| 16 | SNDRV_PCM_FMTBIT_S24_LE | \ |
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| 17 | SNDRV_PCM_FMTBIT_S32_LE) |
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| 18 | |
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| 19 | #define ADCX140_PAGE_SELECT 0x00 |
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| 20 | #define ADCX140_SW_RESET 0x01 |
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| 21 | #define ADCX140_SLEEP_CFG 0x02 |
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| 22 | #define ADCX140_SHDN_CFG 0x05 |
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| 23 | #define ADCX140_ASI_CFG0 0x07 |
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| 24 | #define ADCX140_ASI_CFG1 0x08 |
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| 25 | #define ADCX140_ASI_CFG2 0x09 |
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| 26 | #define ADCX140_ASI_CH1 0x0b |
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| 27 | #define ADCX140_ASI_CH2 0x0c |
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| 28 | #define ADCX140_ASI_CH3 0x0d |
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| 29 | #define ADCX140_ASI_CH4 0x0e |
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| 30 | #define ADCX140_ASI_CH5 0x0f |
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| 31 | #define ADCX140_ASI_CH6 0x10 |
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| 32 | #define ADCX140_ASI_CH7 0x11 |
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| 33 | #define ADCX140_ASI_CH8 0x12 |
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| 34 | #define ADCX140_MST_CFG0 0x13 |
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| 35 | #define ADCX140_MST_CFG1 0x14 |
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| 36 | #define ADCX140_ASI_STS 0x15 |
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| 37 | #define ADCX140_CLK_SRC 0x16 |
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| 38 | #define ADCX140_PDMCLK_CFG 0x1f |
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| 39 | #define ADCX140_PDM_CFG 0x20 |
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| 40 | #define ADCX140_GPIO_CFG0 0x21 |
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| 41 | #define ADCX140_GPO_CFG0 0x22 |
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| 42 | #define ADCX140_GPO_CFG1 0x23 |
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| 43 | #define ADCX140_GPO_CFG2 0x24 |
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| 44 | #define ADCX140_GPO_CFG3 0x25 |
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| 45 | #define ADCX140_GPO_VAL 0x29 |
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| 46 | #define ADCX140_GPIO_MON 0x2a |
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| 47 | #define ADCX140_GPI_CFG0 0x2b |
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| 48 | #define ADCX140_GPI_CFG1 0x2c |
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| 49 | #define ADCX140_GPI_MON 0x2f |
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| 50 | #define ADCX140_INT_CFG 0x32 |
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| 51 | #define ADCX140_INT_MASK0 0x33 |
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| 52 | #define ADCX140_INT_LTCH0 0x36 |
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| 53 | #define ADCX140_BIAS_CFG 0x3b |
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| 54 | #define ADCX140_CH1_CFG0 0x3c |
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| 55 | #define ADCX140_CH1_CFG1 0x3d |
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| 56 | #define ADCX140_CH1_CFG2 0x3e |
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| 57 | #define ADCX140_CH1_CFG3 0x3f |
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| 58 | #define ADCX140_CH1_CFG4 0x40 |
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| 59 | #define ADCX140_CH2_CFG0 0x41 |
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| 60 | #define ADCX140_CH2_CFG1 0x42 |
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| 61 | #define ADCX140_CH2_CFG2 0x43 |
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| 62 | #define ADCX140_CH2_CFG3 0x44 |
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| 63 | #define ADCX140_CH2_CFG4 0x45 |
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| 64 | #define ADCX140_CH3_CFG0 0x46 |
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| 65 | #define ADCX140_CH3_CFG1 0x47 |
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| 66 | #define ADCX140_CH3_CFG2 0x48 |
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| 67 | #define ADCX140_CH3_CFG3 0x49 |
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| 68 | #define ADCX140_CH3_CFG4 0x4a |
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| 69 | #define ADCX140_CH4_CFG0 0x4b |
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| 70 | #define ADCX140_CH4_CFG1 0x4c |
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| 71 | #define ADCX140_CH4_CFG2 0x4d |
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| 72 | #define ADCX140_CH4_CFG3 0x4e |
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| 73 | #define ADCX140_CH4_CFG4 0x4f |
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| 74 | #define ADCX140_CH5_CFG2 0x52 |
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| 75 | #define ADCX140_CH5_CFG3 0x53 |
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| 76 | #define ADCX140_CH5_CFG4 0x54 |
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| 77 | #define ADCX140_CH6_CFG2 0x57 |
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| 78 | #define ADCX140_CH6_CFG3 0x58 |
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| 79 | #define ADCX140_CH6_CFG4 0x59 |
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| 80 | #define ADCX140_CH7_CFG2 0x5c |
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| 81 | #define ADCX140_CH7_CFG3 0x5d |
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| 82 | #define ADCX140_CH7_CFG4 0x5e |
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| 83 | #define ADCX140_CH8_CFG2 0x61 |
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| 84 | #define ADCX140_CH8_CFG3 0x62 |
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| 85 | #define ADCX140_CH8_CFG4 0x63 |
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| 86 | #define ADCX140_DSP_CFG0 0x6b |
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| 87 | #define ADCX140_DSP_CFG1 0x6c |
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| 88 | #define ADCX140_DRE_CFG0 0x6d |
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| 89 | #define ADCX140_AGC_CFG0 0x70 |
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| 90 | #define ADCX140_IN_CH_EN 0x73 |
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| 91 | #define ADCX140_ASI_OUT_CH_EN 0x74 |
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| 92 | #define ADCX140_PWR_CFG 0x75 |
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| 93 | #define ADCX140_DEV_STS0 0x76 |
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| 94 | #define ADCX140_DEV_STS1 0x77 |
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| 95 | #define ADCX140_PHASE_CALIB 0X7b |
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| 96 | |
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| 97 | #define ADCX140_RESET BIT(0) |
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| 98 | |
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| 99 | #define ADCX140_WAKE_DEV BIT(0) |
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| 100 | #define ADCX140_AREG_INTERNAL BIT(7) |
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| 101 | |
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| 102 | #define ADCX140_BCLKINV_BIT BIT(2) |
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| 103 | #define ADCX140_FSYNCINV_BIT BIT(3) |
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| 104 | #define ADCX140_INV_MSK (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT) |
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| 105 | #define ADCX140_BCLK_FSYNC_MASTER BIT(7) |
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| 106 | #define ADCX140_I2S_MODE_BIT BIT(6) |
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| 107 | #define ADCX140_LEFT_JUST_BIT BIT(7) |
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| 108 | #define ADCX140_ASI_FORMAT_MSK (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT) |
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| 109 | |
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| 110 | #define ADCX140_16_BIT_WORD 0x0 |
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| 111 | #define ADCX140_20_BIT_WORD BIT(4) |
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| 112 | #define ADCX140_24_BIT_WORD BIT(5) |
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| 113 | #define ADCX140_32_BIT_WORD (BIT(4) | BIT(5)) |
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| 114 | #define ADCX140_WORD_LEN_MSK 0x30 |
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| 115 | |
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| 116 | #define ADCX140_MAX_CHANNELS 8 |
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| 117 | |
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| 118 | #define ADCX140_MIC_BIAS_VAL_VREF 0 |
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| 119 | #define ADCX140_MIC_BIAS_VAL_VREF_1096 1 |
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| 120 | #define ADCX140_MIC_BIAS_VAL_AVDD 6 |
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| 121 | #define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4) |
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| 122 | #define ADCX140_MIC_BIAS_SHIFT 4 |
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| 123 | |
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| 124 | #define ADCX140_MIC_BIAS_VREF_275V 0 |
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| 125 | #define ADCX140_MIC_BIAS_VREF_25V 1 |
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| 126 | #define ADCX140_MIC_BIAS_VREF_1375V 2 |
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| 127 | #define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0) |
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| 128 | |
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| 129 | #define ADCX140_PWR_CTRL_MSK GENMASK(7, 5) |
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| 130 | #define ADCX140_PWR_CFG_BIAS_PDZ BIT(7) |
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| 131 | #define ADCX140_PWR_CFG_ADC_PDZ BIT(6) |
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| 132 | #define ADCX140_PWR_CFG_PLL_PDZ BIT(5) |
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| 133 | |
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| 134 | #define ADCX140_TX_OFFSET_MASK GENMASK(4, 0) |
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| 135 | |
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| 136 | #define ADCX140_NUM_PDM_EDGES 4 |
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| 137 | #define ADCX140_PDM_EDGE_SHIFT 7 |
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| 138 | |
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| 139 | #define ADCX140_NUM_GPI_PINS 4 |
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| 140 | #define ADCX140_GPI_SHIFT 4 |
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| 141 | #define ADCX140_GPI1_INDEX 0 |
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| 142 | #define ADCX140_GPI2_INDEX 1 |
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| 143 | #define ADCX140_GPI3_INDEX 2 |
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| 144 | #define ADCX140_GPI4_INDEX 3 |
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| 145 | |
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| 146 | #define ADCX140_NUM_GPOS 4 |
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| 147 | #define ADCX140_NUM_GPO_CFGS 2 |
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| 148 | #define ADCX140_GPO_SHIFT 4 |
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| 149 | #define ADCX140_GPO_CFG_MAX 4 |
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| 150 | #define ADCX140_GPO_DRV_MAX 5 |
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| 151 | |
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| 152 | #define ADCX140_TX_FILL BIT(0) |
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| 153 | |
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| 154 | #define ADCX140_NUM_GPIO_CFGS 2 |
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| 155 | #define ADCX140_GPIO_SHIFT 4 |
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| 156 | #define ADCX140_GPIO_CFG_MAX 15 |
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| 157 | #define ADCX140_GPIO_DRV_MAX 5 |
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| 158 | |
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| 159 | #endif /* _TLV320ADCX140_ */ |
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| 160 | |
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