| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tlv320aic32x4.h |
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| 4 | */ |
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| 5 | |
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| 6 | |
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| 7 | #ifndef _TLV320AIC32X4_H |
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| 8 | #define _TLV320AIC32X4_H |
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| 9 | |
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| 10 | struct device; |
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| 11 | struct regmap_config; |
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| 12 | |
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| 13 | enum aic32x4_type { |
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| 14 | AIC32X4_TYPE_AIC32X4 = 0, |
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| 15 | AIC32X4_TYPE_AIC32X6, |
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| 16 | AIC32X4_TYPE_TAS2505, |
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| 17 | }; |
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| 18 | |
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| 19 | extern const struct regmap_config aic32x4_regmap_config; |
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| 20 | int aic32x4_probe(struct device *dev, struct regmap *regmap, |
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| 21 | enum aic32x4_type type); |
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| 22 | void aic32x4_remove(struct device *dev); |
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| 23 | int aic32x4_register_clocks(struct device *dev, const char *mclk_name); |
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| 24 | |
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| 25 | /* tlv320aic32x4 register space (in decimal to match datasheet) */ |
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| 26 | |
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| 27 | #define AIC32X4_REG(page, reg) ((page * 128) + reg) |
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| 28 | |
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| 29 | #define AIC32X4_PSEL AIC32X4_REG(0, 0) |
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| 30 | |
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| 31 | #define AIC32X4_RESET AIC32X4_REG(0, 1) |
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| 32 | #define AIC32X4_CLKMUX AIC32X4_REG(0, 4) |
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| 33 | #define AIC32X4_PLLPR AIC32X4_REG(0, 5) |
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| 34 | #define AIC32X4_PLLJ AIC32X4_REG(0, 6) |
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| 35 | #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7) |
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| 36 | #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8) |
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| 37 | #define AIC32X4_NDAC AIC32X4_REG(0, 11) |
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| 38 | #define AIC32X4_MDAC AIC32X4_REG(0, 12) |
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| 39 | #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13) |
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| 40 | #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14) |
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| 41 | #define AIC32X4_NADC AIC32X4_REG(0, 18) |
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| 42 | #define AIC32X4_MADC AIC32X4_REG(0, 19) |
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| 43 | #define AIC32X4_AOSR AIC32X4_REG(0, 20) |
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| 44 | #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25) |
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| 45 | #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26) |
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| 46 | #define AIC32X4_IFACE1 AIC32X4_REG(0, 27) |
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| 47 | #define AIC32X4_IFACE2 AIC32X4_REG(0, 28) |
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| 48 | #define AIC32X4_IFACE3 AIC32X4_REG(0, 29) |
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| 49 | #define AIC32X4_BCLKN AIC32X4_REG(0, 30) |
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| 50 | #define AIC32X4_IFACE4 AIC32X4_REG(0, 31) |
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| 51 | #define AIC32X4_IFACE5 AIC32X4_REG(0, 32) |
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| 52 | #define AIC32X4_IFACE6 AIC32X4_REG(0, 33) |
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| 53 | #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52) |
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| 54 | #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53) |
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| 55 | #define AIC32X4_DINCTL AIC32X4_REG(0, 54) |
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| 56 | #define AIC32X4_MISOCTL AIC32X4_REG(0, 55) |
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| 57 | #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56) |
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| 58 | #define AIC32X4_DACSPB AIC32X4_REG(0, 60) |
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| 59 | #define AIC32X4_ADCSPB AIC32X4_REG(0, 61) |
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| 60 | #define AIC32X4_DACSETUP AIC32X4_REG(0, 63) |
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| 61 | #define AIC32X4_DACMUTE AIC32X4_REG(0, 64) |
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| 62 | #define AIC32X4_LDACVOL AIC32X4_REG(0, 65) |
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| 63 | #define AIC32X4_RDACVOL AIC32X4_REG(0, 66) |
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| 64 | #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81) |
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| 65 | #define AIC32X4_ADCFGA AIC32X4_REG(0, 82) |
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| 66 | #define AIC32X4_LADCVOL AIC32X4_REG(0, 83) |
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| 67 | #define AIC32X4_RADCVOL AIC32X4_REG(0, 84) |
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| 68 | #define AIC32X4_LAGC1 AIC32X4_REG(0, 86) |
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| 69 | #define AIC32X4_LAGC2 AIC32X4_REG(0, 87) |
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| 70 | #define AIC32X4_LAGC3 AIC32X4_REG(0, 88) |
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| 71 | #define AIC32X4_LAGC4 AIC32X4_REG(0, 89) |
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| 72 | #define AIC32X4_LAGC5 AIC32X4_REG(0, 90) |
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| 73 | #define AIC32X4_LAGC6 AIC32X4_REG(0, 91) |
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| 74 | #define AIC32X4_LAGC7 AIC32X4_REG(0, 92) |
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| 75 | #define AIC32X4_RAGC1 AIC32X4_REG(0, 94) |
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| 76 | #define AIC32X4_RAGC2 AIC32X4_REG(0, 95) |
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| 77 | #define AIC32X4_RAGC3 AIC32X4_REG(0, 96) |
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| 78 | #define AIC32X4_RAGC4 AIC32X4_REG(0, 97) |
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| 79 | #define AIC32X4_RAGC5 AIC32X4_REG(0, 98) |
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| 80 | #define AIC32X4_RAGC6 AIC32X4_REG(0, 99) |
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| 81 | #define AIC32X4_RAGC7 AIC32X4_REG(0, 100) |
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| 82 | |
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| 83 | #define AIC32X4_PWRCFG AIC32X4_REG(1, 1) |
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| 84 | #define AIC32X4_LDOCTL AIC32X4_REG(1, 2) |
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| 85 | #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3) |
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| 86 | #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4) |
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| 87 | #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9) |
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| 88 | #define AIC32X4_CMMODE AIC32X4_REG(1, 10) |
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| 89 | #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12) |
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| 90 | #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13) |
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| 91 | #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14) |
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| 92 | #define AIC32X4_LORROUTE AIC32X4_REG(1, 15) |
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| 93 | #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16) |
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| 94 | #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17) |
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| 95 | #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18) |
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| 96 | #define AIC32X4_LORGAIN AIC32X4_REG(1, 19) |
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| 97 | #define AIC32X4_HEADSTART AIC32X4_REG(1, 20) |
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| 98 | #define TAS2505_SPK AIC32X4_REG(1, 45) |
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| 99 | #define TAS2505_SPKVOL1 AIC32X4_REG(1, 46) |
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| 100 | #define TAS2505_SPKVOL2 AIC32X4_REG(1, 48) |
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| 101 | #define AIC32X4_MICBIAS AIC32X4_REG(1, 51) |
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| 102 | #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52) |
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| 103 | #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54) |
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| 104 | #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55) |
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| 105 | #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57) |
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| 106 | #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) |
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| 107 | #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) |
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| 108 | #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) |
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| 109 | #define TAS2505_REFPOWERUP AIC32X4_REG(1, 122) |
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| 110 | #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123) |
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| 111 | |
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| 112 | /* Bits, masks, and shifts */ |
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| 113 | |
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| 114 | /* AIC32X4_CLKMUX */ |
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| 115 | #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2) |
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| 116 | #define AIC32X4_PLL_CLKIN_SHIFT (2) |
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| 117 | #define AIC32X4_PLL_CLKIN_MCLK (0x00) |
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| 118 | #define AIC32X4_PLL_CLKIN_BCKL (0x01) |
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| 119 | #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) |
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| 120 | #define AIC32X4_PLL_CLKIN_DIN (0x03) |
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| 121 | #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0) |
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| 122 | #define AIC32X4_CODEC_CLKIN_SHIFT (0) |
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| 123 | #define AIC32X4_CODEC_CLKIN_MCLK (0x00) |
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| 124 | #define AIC32X4_CODEC_CLKIN_BCLK (0x01) |
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| 125 | #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) |
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| 126 | #define AIC32X4_CODEC_CLKIN_PLL (0x03) |
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| 127 | |
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| 128 | /* AIC32X4_PLLPR */ |
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| 129 | #define AIC32X4_PLLEN BIT(7) |
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| 130 | #define AIC32X4_PLL_P_MASK GENMASK(6, 4) |
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| 131 | #define AIC32X4_PLL_P_SHIFT (4) |
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| 132 | #define AIC32X4_PLL_R_MASK GENMASK(3, 0) |
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| 133 | |
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| 134 | /* AIC32X4_NDAC */ |
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| 135 | #define AIC32X4_NDACEN BIT(7) |
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| 136 | #define AIC32X4_NDAC_MASK GENMASK(6, 0) |
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| 137 | |
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| 138 | /* AIC32X4_MDAC */ |
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| 139 | #define AIC32X4_MDACEN BIT(7) |
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| 140 | #define AIC32X4_MDAC_MASK GENMASK(6, 0) |
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| 141 | |
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| 142 | /* AIC32X4_NADC */ |
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| 143 | #define AIC32X4_NADCEN BIT(7) |
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| 144 | #define AIC32X4_NADC_MASK GENMASK(6, 0) |
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| 145 | |
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| 146 | /* AIC32X4_MADC */ |
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| 147 | #define AIC32X4_MADCEN BIT(7) |
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| 148 | #define AIC32X4_MADC_MASK GENMASK(6, 0) |
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| 149 | |
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| 150 | /* AIC32X4_BCLKN */ |
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| 151 | #define AIC32X4_BCLKEN BIT(7) |
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| 152 | #define AIC32X4_BCLK_MASK GENMASK(6, 0) |
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| 153 | |
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| 154 | /* AIC32X4_IFACE1 */ |
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| 155 | #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6) |
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| 156 | #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) |
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| 157 | #define AIC32X4_I2S_MODE (0x00) |
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| 158 | #define AIC32X4_DSP_MODE (0x01) |
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| 159 | #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) |
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| 160 | #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) |
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| 161 | #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4) |
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| 162 | #define AIC32X4_IFACE1_DATALEN_SHIFT (4) |
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| 163 | #define AIC32X4_WORD_LEN_16BITS (0x00) |
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| 164 | #define AIC32X4_WORD_LEN_20BITS (0x01) |
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| 165 | #define AIC32X4_WORD_LEN_24BITS (0x02) |
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| 166 | #define AIC32X4_WORD_LEN_32BITS (0x03) |
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| 167 | #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2) |
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| 168 | #define AIC32X4_BCLKMASTER BIT(2) |
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| 169 | #define AIC32X4_WCLKMASTER BIT(3) |
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| 170 | |
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| 171 | /* AIC32X4_IFACE2 */ |
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| 172 | #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0) |
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| 173 | |
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| 174 | /* AIC32X4_IFACE3 */ |
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| 175 | #define AIC32X4_BCLKINV_MASK BIT(3) |
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| 176 | #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0) |
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| 177 | #define AIC32X4_BDIVCLK_SHIFT (0) |
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| 178 | #define AIC32X4_DAC2BCLK (0x00) |
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| 179 | #define AIC32X4_DACMOD2BCLK (0x01) |
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| 180 | #define AIC32X4_ADC2BCLK (0x02) |
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| 181 | #define AIC32X4_ADCMOD2BCLK (0x03) |
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| 182 | |
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| 183 | /* AIC32X4_DACSETUP */ |
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| 184 | #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2) |
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| 185 | #define AIC32X4_LDAC2RCHN BIT(5) |
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| 186 | #define AIC32X4_LDAC2LCHN BIT(4) |
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| 187 | #define AIC32X4_RDAC2LCHN BIT(3) |
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| 188 | #define AIC32X4_RDAC2RCHN BIT(2) |
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| 189 | |
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| 190 | /* AIC32X4_DACMUTE */ |
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| 191 | #define AIC32X4_MUTEON 0x0C |
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| 192 | |
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| 193 | /* AIC32X4_ADCSETUP */ |
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| 194 | #define AIC32X4_LADC_EN BIT(7) |
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| 195 | #define AIC32X4_RADC_EN BIT(6) |
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| 196 | |
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| 197 | /* AIC32X4_PWRCFG */ |
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| 198 | #define AIC32X4_AVDDWEAKDISABLE BIT(3) |
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| 199 | |
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| 200 | /* AIC32X4_LDOCTL */ |
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| 201 | #define AIC32X4_LDOCTLEN BIT(0) |
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| 202 | |
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| 203 | /* AIC32X4_CMMODE */ |
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| 204 | #define AIC32X4_LDOIN_18_36 BIT(0) |
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| 205 | #define AIC32X4_LDOIN2HP BIT(1) |
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| 206 | |
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| 207 | /* AIC32X4_MICBIAS */ |
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| 208 | #define AIC32X4_MICBIAS_LDOIN BIT(3) |
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| 209 | #define AIC32X4_MICBIAS_2075V 0x60 |
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| 210 | #define AIC32x4_MICBIAS_MASK GENMASK(6, 3) |
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| 211 | |
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| 212 | /* AIC32X4_LMICPGANIN */ |
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| 213 | #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 |
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| 214 | #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 |
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| 215 | |
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| 216 | /* AIC32X4_RMICPGANIN */ |
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| 217 | #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 |
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| 218 | #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 |
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| 219 | |
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| 220 | /* AIC32X4_REFPOWERUP */ |
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| 221 | #define AIC32X4_REFPOWERUP_SLOW 0x04 |
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| 222 | #define AIC32X4_REFPOWERUP_40MS 0x05 |
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| 223 | #define AIC32X4_REFPOWERUP_80MS 0x06 |
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| 224 | #define AIC32X4_REFPOWERUP_120MS 0x07 |
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| 225 | |
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| 226 | /* Common mask and enable for all of the dividers */ |
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| 227 | #define AIC32X4_DIVEN BIT(7) |
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| 228 | #define AIC32X4_DIV_MASK GENMASK(6, 0) |
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| 229 | #define AIC32X4_DIV_MAX 128 |
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| 230 | |
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| 231 | /* Clock Limits */ |
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| 232 | #define AIC32X4_MAX_DOSR_FREQ 6200000 |
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| 233 | #define AIC32X4_MIN_DOSR_FREQ 2800000 |
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| 234 | #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 |
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| 235 | #define AIC32X4_MAX_PLL_CLKIN 20000000 |
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| 236 | |
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| 237 | #endif /* _TLV320AIC32X4_H */ |
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| 238 | |
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